A 1.2-V current-mode RMS-to-DC converter based on a novel two-quadrant electronically simulated MOS translinear loop

A novel current-mode CMOS RMS-to-DC converter using translinear techniques is introduced. It is based on a squarer/divider cell that is implemented using an electronically simulated loop with a novel biasing scheme that allows its operation in two quadrants. The cell is designed using a differential input current and a small signal first order filter to implement the voltage averaging, leading to a compact solution that can be used with low voltage supplies. The converter has been fabricated in a standard 130-nm CMOS process, and measurement results are provided to demonstrate the feasibility of the system. This work was supported in part by Agencia Estatal de Investigación/Fondo Europeo de Desarrollo Regional under Grant TEC2016-80396-C2-1-R, and in part by the Obra Social La Caixa - Fundación Caja Navarra (Convocatoria 2018 de Captación de Talento).