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3D integration technologies are becoming increasingly viable to mitigate the limitations and slowdown in traditional 2D transistor scaling. 3D-Split SRAMs, realized by splitting the bitlines (BL) and/or wordlines (WL) across two or more 3D-arranged tiers, promise improved power/performance due to reduced RC parasitics. However, their feasibility and efficacy depend on the pitch and RC parasitics of the inter-tier BEOL connections (3D-BEOL). In this work, we analyze the impact of 3D-BEOL on the 3D-Split SRAM gains, in a face-to-face (F2F) hybrid wafer bonding 3D integration technology. Two separate approaches for reducing 3D-BEOL parasitics viz (1) M Z -Supervia, & (2) M Z -less 3D-BEOL are proposed. Measurements from 64 Kb 12 nm FinFET SRAM prototype, reconfigured to capture the BL-split and the WL-split 3D SRAM effects, show up to 107 mV lower V min as well as $\sim$15% better access-time, equivalent to the performance gains from one technology node dimensional scaling.

A high-density-3D test-vehicle showcasing a synchronous cache coherent mesh interconnect design (Arm Neoverse® CMN-600) operational at frequencies up to 2.4 GHz and partitioned in 3D using 5.76µm pitch face-to-face wafer-bond 3D connections on a 12nm FinFET process is presented. The test-vehicle is designed using an industry tool compatible innovative physical implementation flow and serves as the first known industry demonstration of the IEEE 1838 3DIC Design-for-Test (DFT) standard. We demonstrate a 3D aggregate bandwidth of 307 GB/s, a record bandwidth density of 3.4 TB/s/mm2, and an energy efficiency of 0.02 pJ/bit for the 3D-stacked dies. We present measurement and analysis data from 945 dies where a total of 13.5 million signal 3D wafer-bond nets and 20 million power-delivery 3D wafer-bond nets on multiple wafer-bonded pairs are tested showing robust functionality, paving the path for 3D-stacked high performance logic-on-logic applications.

An 8Kx192b charge trap transistor one time programmable memory (OTPM) is designed and manufactured in GLOBALFOUNDRIES 14-nm bulk FinFET technology without process adders or additional masks. A write timer state machine issues multicycle 192b parallel programming with per bit overwrite protection to minimize stress conditions during a write. On-chip generated voltages are temperature dependent, enabling writes and reads at military grade temperatures. A differential current sense amplifier with self-biased margining circuitry enables programming the OTPM twin cell with known repeatable margin across process–voltage–temperature. Hardware qualification certifies the OTPM to a 10-year 105 °C data retention specification and

This paper describes the design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity. Charge trap transistors (CTTs) that exploit charge trapping and de-trapping behavior in high-K dielectric of 32-/22-nm Logic FETs are used as storage elements with logic-compatible programming voltages. A high-gain slew-sense amplifier (SA) is used to efficiently detect the threshold voltage difference ( $\Delta V_{\textrm {DIF}}$ ) between the true and complement FETs in the twin cell. Design-assist techniques including multi-step programming with over-write protection and block write algorithm are used to enhance the programming efficiency without causing a dielectric breakdown. High-temperature stress results show a projected data retention of 10 years at 125 °C with a signal loss of

A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with $\hbox{0.0174}~\mu\hbox{m}^{2}$ deep-trench capacitor cell. A Gated-feedback sense amplifier enables a high voltage gain of a power-gated inverter at mid-level input voltage, while supporting 66 cells per local bit-line. A dynamic-and-gate-thin-oxide word-line driver that tracks standard logic process variation improves the eDRAM array performance with reduced area. The 1.1 $~$ Mb macro composed of 8 $\times$ 2 72 Kb subarrays is organized with a center interface block architecture, allowing 1 ns access latency and 1 ns bank interleaving operation using two banks, each having 2 ns random access cycle. 5 GHz operation has been demonstrated in a system prototype, which includes 6 instances of 1.1 Mb eDRAM macros, integrated with an array-built-in-self-test engine, phase-locked loop (PLL), and word-line high and word-line low voltage generators. The advantage of the 14 nm FinFET array over the 22 nm array was confirmed using direct tester control of the 1.1 Mb eDRAM macros integrated in 16 Mb inline monitor.

Ramped programming optimization is investigated in order to limit the risk of gate oxide breakdown (BD) during the programming of a Multi-Time Programmable Memory. Optimization of the programming ramp rate has been proven to be beneficial at both device level and array level. This allows for inline monitoring of programmability and BD-risk reduction as a function of process changes.

An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (∼30%) to satisfy 10 year retention at 105° C.

High performance processors and ASICs typically require multiple voltages and multi-domain voltage controls across the die. Conventional approaches distribute the voltage regulation elements between the processor, the package laminate, and the printed circuit board. We propose an alternative approach where the voltage regulator is embodied in a 3D configuration such that the inductor, capacitor and the switches are formed on a separate silicon chip sandwiched between the processor and the laminate. Due to the close proximity of regulator to the processor, this approach can enable granular voltage domains, while minimizing disruptions to the processor layout. We describe a 4-f DC-DC buck converter fabricated on 32nm SOI wafers using TSVs to connect the switches on the front-side of the wafer to the inductors on the grind-side. The process builds on a 32nm SOI CMOS flow, adding deep trench (DT) capacitors and TSV's. Down conversion from a standard I/O voltage under various load conditions was evaluated, and an efficiency of 77% was achieved.

An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively.

A random intrinsic chip ID method generates a pair of 4Kb binary strings using retention fails in 32nm SOI embedded DRAM. Hardware results show ID overlap distance mean=0.58 and σ=0.76 and demonstrate 100% authentication for 346 chips. The analytical model predicts > 99.999% unique IDs for 106 parts.

We present industry's smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressively scaled at 58% (vs. 45nm) and features the key innovation of High-K Metal (HK/M) stack in the Deep Trench (DT) capacitor. This has enabled 25% higher capacitance and 70% lower resistance compared to conventional SiON/Poly stack at matched leakage and reliability. The HKMG access transistor developed in high performance optimized technology features sub 3fA leakage and well-controlled threshold voltage sigma of 40mV. The fully integrated 32Mb product prototypes demonstrate state of the art performance with excellent retention and yield characteristics. The sub 1.5ns latency and 2ns cycle time have been verified with preliminary testing whereas even better performance is expected with further characterization. In addition, the trench capacitors set the industry benchmark for the most efficient decoupling in any 32nm technology.

A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRAM technology fully compatible with high performance logic with high-к metal gate access transistor and high-к node dielectric for the deep trench storage capacitor. We also describe the technology advancements required to scale the deep trench as well as the access transistor for optimal cell retention and performance. A clear scaling path is seen for the 22nm technology node.

Demonstrating a >10X density increase over traditional VLSI fuse circuits, a compact eFUSE programmable array memory configured as a 4 Kb one-time programmable ROM (OTPROM) is presented using a 6.2 mum2 NiSix silicide electromigration ITIR cell in 65 nm SOI CMOS. A 20 mus programming time at 1.5 V is achieved by asymmetrical scaling of the fuse and a shared differential sensing scheme. Having zero process cost adder, eFUSE is fully compatible with standard VLSI manufacturing.