Search

Your search keyword '"ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)"' showing total 21 results
Start Over Author "ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)"
21 results on '"ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)"'

1. Impact of the pre amorphization by Ge implantation on Ni$_{0.9}$Pt$_{0.1}$ silicide

Author

Delwail, C., Joblot, S., Mazen, F., Abbate, F., Lachal, L., Milesi, F., Bertoglio, M., Papon, A.M., Gregoire, M., Rodriguez, P.H., Mangelinck, D., Mangelinck, Dominique, STMicroelectronics [Crolles] (ST-CROLLES), Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
[CHIM.MATE]Chemical Sciences/Material chemistry, Electrical and Electronic Engineering, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials
Abstract

International audience; The impact of the Pre Amorphization by Ge Implantation (PAI) on Ni0.9Pt0.1 silicide is studied. Reactions between a 10 nm thick Ni0.9Pt0.1 film and Si (100) substrate are analyzed as a function of the induced amorphous-Si thicknesses. In view of being compatible with the integration constraint of the 28 nm CMOS technologies, the Ge implantation dose is fixed at a low level. The relative position of the amorphous-Si/crystalline-Si interface and the silicide growth front is defined for each sample. Then, in-situ XRD analyses, X-Ray Reflectometry (XRR) and Sheet resistance (Rs) measurements are achieved to provide a deep study of silicide growth kinetics and silicide properties. First, a clear relationship is established between the silicide growth rate and the amorphous-Si thickness. Secondly, an easier NiSi nucleation and a decrease of its resistivity is observed when NiSi nucleates at the θ-Ni2Si/a-Si interface. These observations are discussed considering the impact of the amorphous-Si layer on the driving force, the nucleation barrier, the lateral growth rate, and NiSi roughness.

Published
2022
Full Text
View/download PDF

2. Advanced characterizations of fluorine-free tungsten film and its application as low resistance liner for PCRAM

Author

B.-N. Bozon, J.-Ph. Reynard, Y. Le Friec, Sylvie Favier, Yann Mazel, K. Dabertrand, Patrice Gergaud, R. Famulok, Ph. Rodriguez, Fabrice Nemouchi, C. Jahan, Bernard Previtali, F. Boyer, Département Intégration Hétérogène sur Silicium (DIHS), Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics, Applied Materials France, ANR-11-EQPX-0010,CRGF,Lignes synchrotron françaises à l'ESRF(2011), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), ANR-10-AIRT-0005,NANOELEC,NANOELEC(2010), and ANR: ANR-10-AIRT-05,Programme Investissements d’Avenir

Subjects
Materials science, Interconnects, Analytical chemistry, chemistry.chemical_element, 02 engineering and technology, Substrate (electronics), Tungsten, 01 natural sciences, [SPI.MAT]Engineering Sciences [physics]/Materials, Atomic layer deposition, Plasma-enhanced chemical vapor deposition, Low resistance, Contact, 0103 physical sciences, General Materials Science, Thin film, Composite material, 010302 applied physics, Mechanical Engineering, 021001 nanoscience & nanotechnology, Condensed Matter Physics, [SPI.TRON]Engineering Sciences [physics]/Electronics, X-ray reflectivity, Tungsten film, chemistry, Mechanics of Materials, PCRAM, Liner, 0210 nano-technology, Layer (electronics)
Abstract

International audience; Using a metal-organic tungsten based precursor, a fluorine-free tungsten thin film has been obtained. The process deposition recipe includes a plasma-enhanced CVD (PECVD) step and atomic layer deposition (ALD) cycles. A set of physicochemical characterizations including X-ray reflectivity (XRR), in-plane X-ray diffraction (XRD), wavelength dispersive X-ray fluorescence (WDXRF), plasma profiling time of flight mass spectrometry (PPTOFMS) and microscope observations has been realized in order to study the W thin film structure and properties. The film is perfectly conformal whatever the structure size investigated (from tens of nanometers to micrometers wide). It was also highlighted that the F-free W film exhibits the lowest electrical resistivity phase (α-W) but is not pure. Indeed, in addition to a top surface oxidation, a layer located at the W film / substrate interface is present. This interface layer (IL) contains impurities, including carbon and oxygen, due to ligand decomposition. This IL might be deposited during the soak step or during the PECVD step. The W liner with thicknesses ranging from 3 to 4 nm has been implemented on PCRAM structures in order to evaluate its impact on contact plug resistivity. First electrical results are promising and demonstrate the interest of using a F-free low resistance W liner. At the aspect ratio studied, the gain in terms of contact plug resistivity is about 20% compared to the process of reference using a TiN liner. Modeling shows that this benefit is mainly due to the reduction of interface resistances.

Published
2017
Full Text
View/download PDF

3. A Spatial Adaptation of the Time Delay Neural Network for Solving ECGI Inverse Problem

Author

Mostafa Bendahmane, Nejib Zemzemi, Amel Karoui, Modélisation et calculs pour l'électrophysiologie cardiaque (CARMEN), IHU-LIRYC, Université Bordeaux Segalen - Bordeaux 2-CHU Bordeaux [Bordeaux]-Université Bordeaux Segalen - Bordeaux 2-CHU Bordeaux [Bordeaux]-Institut de Mathématiques de Bordeaux (IMB), Université Bordeaux Segalen - Bordeaux 2-Université Sciences et Technologies - Bordeaux 1-Université de Bordeaux (UB)-Institut Polytechnique de Bordeaux (Bordeaux INP)-Centre National de la Recherche Scientifique (CNRS)-Université Sciences et Technologies - Bordeaux 1-Université de Bordeaux (UB)-Institut Polytechnique de Bordeaux (Bordeaux INP)-Centre National de la Recherche Scientifique (CNRS)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Institut de Mathématiques de Bordeaux (IMB), Université Bordeaux Segalen - Bordeaux 2-Université Sciences et Technologies - Bordeaux 1-Université de Bordeaux (UB)-Institut Polytechnique de Bordeaux (Bordeaux INP)-Centre National de la Recherche Scientifique (CNRS), Yves Coudière, Valéry Ozenne, Edward Vigmond, Nejib Zemzemi, ANR-10-IAHU-0004,LIRYC,L'Institut de Rythmologie et modélisation Cardiaque(2010), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), Université Bordeaux Segalen - Bordeaux 2-Université Sciences et Technologies - Bordeaux 1 (UB)-Université de Bordeaux (UB)-Institut Polytechnique de Bordeaux (Bordeaux INP)-Centre National de la Recherche Scientifique (CNRS)-Université Bordeaux Segalen - Bordeaux 2-Université Sciences et Technologies - Bordeaux 1 (UB)-Université de Bordeaux (UB)-Institut Polytechnique de Bordeaux (Bordeaux INP)-Centre National de la Recherche Scientifique (CNRS)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-IHU-LIRYC, Université Bordeaux Segalen - Bordeaux 2-CHU Bordeaux [Bordeaux]-CHU Bordeaux [Bordeaux], and Université Bordeaux Segalen - Bordeaux 2-Université Sciences et Technologies - Bordeaux 1 (UB)-Université de Bordeaux (UB)-Institut Polytechnique de Bordeaux (Bordeaux INP)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Common area, Computer science, 0206 medical engineering, 02 engineering and technology, 030218 nuclear medicine & medical imaging, 03 medical and health sciences, Electrocardiography, Spatial adaptation, 0302 clinical medicine, Operator (computer programming), [SDV.MHEP.CSC]Life Sciences [q-bio]/Human health and pathology/Cardiology and cardiovascular system, [STAT.ML]Statistics [stat]/Machine Learning [stat.ML], [MATH.MATH-ST]Mathematics [math]/Statistics [math.ST], Adjacency matrix, [NLIN]Nonlinear Sciences [physics], Spatial dependence, Artificial neural network, Inverse problem Electrocardiography, Time delay neural network, Inverse problem, 020601 biomedical engineering, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, Adjacency list, Time-delay neural network, Algorithm
Abstract

International audience; The ECGI inverse problem is still a common area of research. Since the results in the state of the art are not yet satisfactory, exploring new methods for the resolution of the inverse problem of electrocardiography is the main goal of this paper. To this purpose, we suggest to use temporal and spatial constraints to solve the inverse problem using neural networks methods. First, we use a time-delay neural network initialized with the spatial adjacency operator of the heart surface mesh. Then, we suggest a new approach to reconstruct the heart surface potential from the body surface potential using a spatial adaptation of time delay neural network. It consists on taking into account temporal and spatial dependence between potential measures. This allows to exploit the local and dynamic potential propagation properties. We test these approaches on simulated data. Results show that the new approach outperforms the classic time-delay neural network and has considerableimprovements with respect to the state-of-the-art methods.

Published
2019
Full Text
View/download PDF

4. Performance and Reliability of a Fully Integrated 3D Sequential Technology

Author

M. Vinet, M. Casse, F. Gaillard, Perrine Batude, Gerard Ghibaudo, A. Tsiara, C. Fenouillet-Beranger, K. Triantopoulos, Laurent Brunet, X. Garros, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Nano 2017, ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), and ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010)

Subjects
010302 applied physics, Computer science, Transistor, Process (computing), 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, PMOS logic, law.invention, Reliability engineering, Reliability (semiconductor), law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Inverter, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, NMOS logic
Abstract

session T7: Process and Material Technology; International audience; We investigate in detail, for the first time, both performance and reliability of a 3D sequential integration process. It is clearly demonstrated that the top level transistor can be successfully processed at 630°C with almost no impact on the performance and reliability of the bottom level. It is also highlighted that top level devices meet the P&NBTI reliability requirements. Finally an example of successful and robust 3D logic integration is proposed based on a 3D inverter combining a top-level PMOS with a bottom-level NMOS.

Published
2018
Full Text
View/download PDF

5. New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration

Author

J.-P. Colinge, Gerard Ghibaudo, Perrine Batude, C-M. V. Lu, F. Allain, C. Le Royer, C. Fenouillet-Beranger, M. Vinet, Sorin Cristoloveanu, C. Diaz Llorente, Sebastien Martinie, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
Materials science, Fabrication, Tunnel FET, Schottky barrier, Silicon on insulator, 02 engineering and technology, Epitaxy, 01 natural sciences, Planar, TFET, 0103 physical sciences, Materials Chemistry, Low temperature, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Quantum tunnelling, 3D integration, 010302 applied physics, SOI, business.industry, SPER, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Tunnelling BTBT, Electronic, Optical and Magnetic Materials, Threshold voltage, Optoelectronics, 0210 nano-technology, business, Voltage
Abstract

International audience; This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.

Published
2018
Full Text
View/download PDF

6. Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs

Author

C. Vizioz, J.M. Hartmann, Maud Vinet, Sotirios Athanasiou, Jean-Charles Barbe, Francois Andrieu, Sebastien Martinie, Thomas Ernst, Olivier Rozeau, C. Comboroure, V. Lapras, Marie-Anne Jaud, François Triozon, Bernard Previtali, Joris Lacord, M.-P. Samson, Sylvain Barraud, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), and European Project: 688101,H2020,H2020-ICT-2015,SUPERAID7(2016)

Subjects
010302 applied physics, Flexibility (engineering), Electron mobility, Materials science, Transistor, Nanowire, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 021001 nanoscience & nanotechnology, 01 natural sciences, 7. Clean energy, Engineering physics, Capacitance, law.invention, Gallium arsenide, chemistry.chemical_compound, [SPI]Engineering Sciences [physics], chemistry, law, Logic gate, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0210 nano-technology, Nanosheet
Abstract

International audience; This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.

Published
2017
Full Text
View/download PDF

7. Thermal effects in 3D sequential technology

Author

C. Fenouillet-Beranger, Perrine Batude, M. Casse, B. Mathieu, G. Reimbold, Gerard Ghibaudo, Laurent Brunet, M. Vinet, K. Triantopoulos, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), nano 2017, and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, Work (thermodynamics), Materials science, Transistor, Dielectric, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, Subthreshold slope, law.invention, law, 0103 physical sciences, Thermal, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, State (computer science), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Communication channel
Abstract

session 7: Characterization, Reliability, and Yield: Reliability of Advanced Devices (7.6); International audience; We present for the first time an experimental study of thermal effects in 3D sequential integration, including Self-Heating Effect (SHE) and thermal coupling between the two levels of ultra-thin body FDSOI transistors. We extracted a large set of experimental data using different thermometry techniques, and different heater-sensor configurations allowed by this specific stacked integration. We described SHE in top and bottom transistor levels, as well as the influence of a transistor in ON state on a transistor stacked above or below. At the same time, we provide for the first time an experimental validation that the temperature increase given by gate resistance thermometry technique is equal to the temperature in the channel given by the subthreshold slope. Finally, this work can be also used to manage thermal effects for logic or analog applications, and help further optimization of 3D sequential integrated circuits through both technology and design solutions.

Published
2017
Full Text
View/download PDF

8. High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration

Author

J. Micout, M. Casse, J.-P. Colinge, L. Desvoivres, Vincent Delaye, C. Fenouillet-Beranger, S. Barraud, X. Garros, Perrine Batude, J.M. Hartmann, R. Bortolin, V. Mazzocchi, Frédéric Mazen, G. Romano, B. Mathieu, N. Rambal, V. Balan, Zineb Saghi, F. Allain, M.-P. Samson, P. Besombes, C. Comboroure, M. Vinet, Quentin Rafhay, Joris Lacord, Claude Tabone, Alain Toffoli, Gerard Ghibaudo, C. Vizioz, Benoit Sklenard, V. Lapras, L. Lachal, Laurent Brunet, Virginie Loup, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire des technologies de la microélectronique (LTM ), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
Materials science, Fabrication, business.industry, 020208 electrical & electronic engineering, Doping, Recrystallization (metallurgy), 02 engineering and technology, Epitaxy, Logic gate, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, 020201 artificial intelligence & image processing, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

Published
2017
Full Text
View/download PDF

9. Self-heating assessment and cold current extraction in FDSOI MOSFETs

Author

C. Fenouillet-Beranger, Laurent Brunet, Perrine Batude, K. Triantopoulos, G. Reimbold, Gerard Ghibaudo, Mikael Casse, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Nano 2017, and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, Materials science, business.industry, Thermal resistance, Transistor, 01 natural sciences, PMOS logic, Ion, law.invention, law, 0103 physical sciences, Thermal, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Current (fluid), Thin film, business, NMOS logic
Abstract

session: Modeling and Characterization; International audience; We present an experimental study of thermal effects in thin film FDSOI MOSFETs, with a focus on the impact of self-heating effect (SHE) on drain current. We have performed thermal resistance extraction using the gate thermometry method, and calculated the resulting cold drain current (Id0), i.e. without SHE. We demonstrate that SHE is more pronounced in shorter and narrower devices without essential differences between nMOS and pMOS transistors. Our experiments show that although the temperature increases significantly in the channel due to SHE, its effect on the ION performances could be limited at operating voltage.

Published
2017
Full Text
View/download PDF

10. Precise EOT regrowth extraction enabling performance analysis of Low Temperature Extension First devices

Author

L. Pasini, Jean Coignus, Perrine Batude, J. Micout, N. Rambal, R. Gassilloud, Claire Fenouillet-Beranger, Maud Vinet, C.-M. V. Lu, Mikael Casse, Xavier Garros, Quentin Rafhay, G. Romano, Gerard Ghibaudo, Laurent Brunet, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics, This work is partly funded by the French Public Authorities through NANO 2017 program and EQUIPEX FDSOI11, ST-LETI Alliance program and by LabEx Minos ANR-10-LABX-55-01., IEEE, ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
0209 industrial biotechnology, Work (thermodynamics), Materials science, business.industry, 020206 networking & telecommunications, 02 engineering and technology, Temperature measurement, Length measurement, 020901 industrial engineering & automation, Logic gate, MOSFET, Thermal, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Optoelectronics, Degradation (geology), Extraction (military), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

session B2L-G: Advanced CMOS Characterization and Reliability; International audience; — 3D sequential integration requires top FETs processing with a low thermal budget (500°C). The analysis of the origin of the performance difference between Low Temperature (LT) MOSFET and high temperature standard process must take into account a potential EOT modification for short gate lengths. In this work, the difficulty of precise EOT extraction for scaled devices is observed by CV measurements and an alternative methodology using IV measurements is proposed. This methodology has been applied to an extension first integration, and the extraction accuracy is high enough to conclude to an EOT regrowth for the low temperature nFETs only. Thus, the origin of performance degradation between LT and HT, previously attributed to larger access resistance, highlights also a detrimental role of gate stack instability. The origin of this variation is attributed to oxygen ingress, through the thin extension first liner which should be suppressed by minor process optimizations.

Published
2017
Full Text
View/download PDF

11. First SOI Tunnel FETs with low-temperature process

Author

C. Diaz Llorente, Sebastien Martinie, Gerard Ghibaudo, M. Vinet, Perrine Batude, C. Le Royer, C. Fenouillet-Beranger, Sorin Cristoloveanu, F. Allain, C-M. V. Lu, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
Fabrication, Materials science, Silicon, Tunnel FET, Silicon on insulator, chemistry.chemical_element, low temperature, Epitaxy, 01 natural sciences, tunneling, TFET, 3D sequential integration, 0103 physical sciences, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, BTBT, Quantum tunnelling, 010302 applied physics, business.industry, Electrical engineering, CoolCube, SPER, Threshold voltage, chemistry, Logic gate, Optoelectronics, business, Voltage
Abstract

session 1: Nanoscale FETs; International audience; We demonstrate for the first time the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) with low temperature (LT) processes devoted to 3D sequential integration. The electrical behavior of these TFETs, with junctions obtained by Solid Phase Epitaxy Regrowth (SPER), is analyzed and compared to reference samples (regular process at high temperature, HT). The threshold voltage (VTH) of p-mode operating TFETs shows a 300 mV reduction with similar ON state currents (wrt HT reference), opening path towards optimized devices (very low VTH & supply voltage VDD).

Published
2017
Full Text
View/download PDF

12. Reaction of Ni film with In0.53Ga0.47As: Phase formation and texture

Author

Tra Nguyen-Thanh, Nathalie Boudet, Patrice Gergaud, Laetitia Rapenne, Philippe Rodriguez, S. Zhiou, Nils Blanc, Fabrice Nemouchi, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), CRG et Grands Instruments (CRG ), Institut Néel (NEEL), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Laboratoire des matériaux et du génie physique (LMGP ), Institut National Polytechnique de Grenoble (INPG)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS), ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), ANR-11-EQPX-0010,CRGF,Lignes synchrotron françaises à l'ESRF(2011), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), ANR-10-LABX-0044,CEMAM,Center of Excellence in Multifunctional Architectured Materials(2010), CRG & Grands instruments (NEEL - CRG), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Materials science, Annealing (metallurgy), Intermetallic, General Physics and Astronomy, 02 engineering and technology, Crystal structure, 021001 nanoscience & nanotechnology, 01 natural sciences, [SPI.MAT]Engineering Sciences [physics]/Materials, Crystallography, Reciprocal lattice, Lattice constant, 0103 physical sciences, X-ray crystallography, Scanning transmission electron microscopy, 0210 nano-technology, Stoichiometry
Abstract

International audience; The solid-state reaction between Ni and In In$_{0.53}$Ga$_{0.47}$As on an InP substrate was studied by X-ray diffraction (XRD) and scanning transmission electron microscopy-energy-dispersive X-ray spec-troscopy techniques. Due to the monocrystalline structural aspect of the so-formed intermetallic, it was necessary to measure by XRD a full 3D reciprocal space mapping in order to have a complete overlook over the crystalline structure and texture of the intermetallic. The formation of the inter-metallic was studied upon several different Rapid Thermal Annealings on the as-deposited samples. Pole figures analysis shows that the intermetallic features a hexagonal structure (P6$_3$$/mmc$) with an NiAs-type (B8) structure. Although only one hexagonal structure is highlighted, the intermetallic exhibits two different domains characterized by different azimuthal orientations, axiotaxial relationship, and lattice parameters. The intermetallic phases seem to present a rather wide range of stoichiometry according to annealing temperature. The texture, structure, and stoichiometry of the intermetallic are discussed along with the evolution of lattice parameters of the Ni-InGaAs phase.

Published
2016
Full Text
View/download PDF

13. High performance CMOS FDSOI devices activated at low temperature

Author

Louis Hutin, J. Mazurier, D. Barge, L. Pasini, Olivier Weber, Frédéric Mazen, F. Piegas Luce, Claire Fenouillet-Beranger, M. Vinet, Antoine Cros, E. Ghegin, B. Mathieu, S. Chhun, J. Borrel, Frederic Boeuf, Quentin Rafhay, Anthony Payet, Michel Haond, Perrine Batude, M. Casse, Fuccio Cristiano, Benoit Sklenard, Zineb Saghi, Joris Lacord, D. Blachier, J.P. Barnes, Gerard Ghibaudo, Francois Andrieu, V. Mazzocchi, N. Rambal, J. Micout, Vincent Delaye, V. Lapras, Laurent Brunet, R. Daubriac, Pascal Besson, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Équipe Matériaux et Procédés pour la Nanoélectronique (LAAS-MPN), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Nano 2017, ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
010302 applied physics, Materials science, business.industry, 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, PMOS logic, CMOS, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [PHYS.COND.CM-MS]Physics [physics]/Condensed Matter [cond-mat]/Materials Science [cond-mat.mtrl-sci], Optoelectronics, business, NMOS logic
Abstract

International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

Published
2016
Full Text
View/download PDF

14. Contacts for Monolithic 3D architecture: Study of Ni$_{0.9}$Co$_{0.1}$ Silicide Formation

Author

C. Sese, F. Deprat, Fabrice Nemouchi, Ph. Rodriguez, Claire Fenouillet-Beranger, Patrice Gergaud, S. Favier, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), ANR-11-EQPX-0010,CRGF,Lignes synchrotron françaises à l'ESRF(2011), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
Diffraction, Materials science, Silicon, NiCo, chemistry.chemical_element, 02 engineering and technology, Substrate (electronics), silicide, 01 natural sciences, law.invention, chemistry.chemical_compound, law, Phase (matter), 0103 physical sciences, Silicide, Thermal stability, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Sheet resistance, 010302 applied physics, business.industry, Transistor, 021001 nanoscience & nanotechnology, Crystallography, chemistry, solid-state reaction, Optoelectronics, 0210 nano-technology, business
Abstract

Auteur correspondant: "philippe.rodriguez@cea.fr"; International audience; In this work, we studied the solid-state reaction between a Ni$_{0.9}$Co$_{0.1}$ film and a silicon substrate. NiCo silicide is considered to substitute Ni-and NiPt-based silicides in 3D integration in order to extend the bottom transistor thermal stability. Thanks to the combined analysis of sheet resistance data, X-ray reflectivity spectra modelling, X-ray diffraction and wavelength dispersive X-ray fluorescence analyses on Ni$_{0.9}$Co$_{0.1}$ /Si samples annealed at various temperatures, we were able to describe the phase sequence of the NiCo silicide formation.

Published
2016
Full Text
View/download PDF

15. In situ cleaning of InGaAs surfaces prior to low contact resistance metallization

Author

E. Ghegin, Laura Toselli, Ph. Rodriguez, Fabrice Nemouchi, Nicolas Chevalier, Eugénie Martinez, Névine Rochat, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), ANR-13-NANO-0001,MOSINAS,MOSFET à hétérostructure et film ultra mince d'InAs sur substrat silicium(2013), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), ANR: ANR-10-AIRT-05,Programme Investissements d’Avenir, and ANR-10-AIRT-0005,NANOELEC,NANOELEC(2010)

Subjects
inorganic chemicals, Materials science, InGaAs, Hydrogen, Analytical chemistry, chemistry.chemical_element, Native oxides, 02 engineering and technology, Surface finish, 01 natural sciences, X-ray photoelectron spectroscopy, 0103 physical sciences, Remote plasma, XPS, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Arsenic, 010302 applied physics, Contact resistance, Plasma, Surface pretreatment, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Direct plasma, chemistry, FTIR, 0210 nano-technology, Indium
Abstract

International audience; In this work, we studied the pretreatment of InGaAs layers by employing Ar-and He-based direct plasmas and NH$_3$ , H$_2$ , NF$_3$ /NH$_3$ remote plasmas. All the remote plasmas involved in this study were inadequate to remove the InGaAs native oxides. Moreover, for NF$_3$ /NH$_3$ exposed samples, we noticed the addition of undesirable In–F and Ga–F bonds. Concerning Ar and He direct plasmas, investigations exhibited that both seem to be efficient for removing arsenic oxides whereas the elimination of indium oxides is more effective with Ar plasma. We also studied the addition of hydrogen into He direct plasma and we demonstrated that increasing the H2 content leads to decreasing the removal of arsenic oxides. The impact on indium oxides is also notable as we observed a reducing effect of hydrogen on indium and the emergence of In–In type bonds. Finally, whatever the plasma pretreatment, no degradation of surface morphology and roughness was observed by AFM. The RMS values obtained after surface treatments are similar with the ones acquired for reference samples.

Published
2016
Full Text
View/download PDF

16. Study of the formation and degradation of intermetallics formed by solid-state reaction of Ni on InGaAs

Author

Zhiou, Seifeddine, Nguyen, Thanh Tra, Rodriguez, Philippe, Nemouchi, Fabrice, Gergaud, Patrice, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), CRG & Grands instruments (NEEL - CRG), Institut Néel (NEEL), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), ANR-11-EQPX-0010,CRGF,Lignes synchrotron françaises à l'ESRF(2011), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), Rodriguez, Philippe, Laboratoires d'excellence - Minatec Novel Devices Scaling Laboratory - - MINOS Lab2010 - ANR-10-LABX-0055 - LABX - VALID, Equipements d'excellence - Lignes synchrotron françaises à l'ESRF - - CRGF2011 - ANR-11-EQPX-0010 - EQPX - VALID, Equipements d'excellence - Plateforme FDSOI pour le node 11nm - - FDSOI112010 - ANR-10-EQPX-0030 - EQPX - VALID, and CRG et Grands Instruments (CRG )

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2016

17. 3DVLSI with CoolCube process: An alternative path to scaling

Author

Maud Vinet, Thomas Signamarcheix, V. Lu, Julie Widiez, Fabien Clermidy, A. Royer, J. Mazurier, M.-P. Samson, F. Piegas-Luce, Fabrice Nemouchi, L. Pasini, J.M. Hartmann, M. Casse, F. Deprat, Laurent Brunet, N. Rambal, Maurice Rivoire, Perceval Coudrain, M. Bidaud, Ogun Turkyilmaz, Hossam Sarhan, F. Ponthenier, G. Ghibaudo, C. Euvard-Colnat, Perrine Batude, Louis Hutin, Sebastien Kerdiles, Claude Tabone, Emmanuel Josse, L. Benaissa, E. Petitprez, Remi Beneyton, Claire Fenouillet-Beranger, L. Hortemel, G. Cibrario, Pascal Besson, A. Seignard, B. Mathieu, F. Fournel, C. Bout, C. Agraffeil, S. Sollier, Michel Haond, O. Billoint, P. Leduc, O. Rozeau, Benoit Sklenard, Sebastien Thuries, Bernard Previtali, O. Faynot, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics, ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), European Project: 619325,EC:FP7:ICT,FP7-ICT-2013-11,COMPOSE3(2013), Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), and ANR-10-EQPX-0030/10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, Very-large-scale integration, Materials science, business.industry, Transistor, Stacking, Electrical engineering, 02 engineering and technology, Direct bonding, Dopant Activation, 01 natural sciences, 7. Clean energy, 020202 computer hardware & architecture, law.invention, law, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Process optimization, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Scaling
Abstract

session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

Published
2015
Full Text
View/download PDF

18. High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator

Author

M. Vinet, Michel Haond, Claire Fenouillet-Beranger, O. Rozeau, F. Allain, Louis Hutin, Sebastien Kerdiles, B. Mathieu, F. Piegas Luce, Pascal Besson, Shay Reboh, Laurent Brunet, Gerard Ghibaudo, Benoit Sklenard, L. Pasini, M. Casse, N. Rambal, Claude Tabone, D. Lafond, F. Aussenac, Perrine Batude, G. Audoit, S. Martini, Nicolas Bernier, J.M. Hartmann, G. Romano, S. Barraud, V. Barral, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
Very-large-scale integration, Fabrication, Materials science, 010308 nuclear & particles physics, 0211 other engineering and technologies, Insulator (electricity), 02 engineering and technology, 01 natural sciences, CMOS, 021105 building & construction, 0103 physical sciences, Scalability, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Performance improvement, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

session 5: 3D Systems and Packaging; International audience; 3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performance is demonstrated for LT TriGate and FDSOI devices using Solid Phase Epitaxy (SPE). Optimization guidelines for further performance improvement are given for FD, TriGate and FinFET on insulator with the constraint of 14nm node channel strain preservation. This work concludes that extension first process scheme (implantation before the raised source and drain epitaxy) is required for FDSOI and TriGate architectures.

Published
2015
Full Text
View/download PDF

19. InGaAs surface pretreatment prior to metal solid-state reactions for low resistance contacts

Author

Névine Rochat, Laura Toselli, Fabrice Nemouchi, Nicolas Chevalier, Eugénie Martinez, E. Ghegin, Ph. Rodriguez, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), ANR-13-NANO-0001,MOSINAS,MOSFET à hétérostructure et film ultra mince d'InAs sur substrat silicium(2013), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), ANR-10-AIRT-0005,NANOELEC,NANOELEC(2010), and ANR: ANR-10-AIRT-05,Programme Investissements d’Avenir

Subjects
010302 applied physics, Materials science, Argon, Silicon, Hydrogen, Analytical chemistry, chemistry.chemical_element, 02 engineering and technology, Plasma, 021001 nanoscience & nanotechnology, 01 natural sciences, Metal, chemistry.chemical_compound, Chemical engineering, chemistry, 13. Climate action, visual_art, 0103 physical sciences, visual_art.visual_art_medium, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, ComputingMilieux_MISCELLANEOUS, Indium, Arsenic, Indium gallium arsenide
Abstract

We have investigated the impact of various plasma treatments on InGaAs layers. Argon- and helium-based direct plasmas are more efficient than remote plasmas for the removal of InGaAs native oxides. We have demonstrated that the nature of direct plasma influences the InGaAs oxides removal efficiency. Indeed, both types of plasma seem to be efficient for removing arsenic oxides whereas the elimination of In oxides is more effective with Ar plasma. Hydrogen addition in He plasma impacts the removal of InGaAs oxides and appears to have a reducing effect on indium atoms. Whatever the nature of the pretreatment, the surface morphology and roughness of InGaAs layers were not significantly impacted.

Published
2015
Full Text
View/download PDF

20. In situ cleaning/passivation of surfaces for contact technology on III-V materials

Author

Fabrice Nemouchi, Philippe Rodriguez, Névine Rochat, Laura Toselli, Eugénie Martinez, E. Ghegin, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), ANR-13-NANO-0001,MOSINAS,MOSFET à hétérostructure et film ultra mince d'InAs sur substrat silicium(2013), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, In situ, Materials science, Passivation, Silicon, business.industry, Analytical chemistry, chemistry.chemical_element, 02 engineering and technology, Plasma, 021001 nanoscience & nanotechnology, 01 natural sciences, chemistry.chemical_compound, chemistry, X-ray photoelectron spectroscopy, Attenuated total reflection, 0103 physical sciences, Optoelectronics, Fourier transform infrared spectroscopy, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Indium gallium arsenide
Abstract

International audience; In this work we introduce the use of physical plasmas (e.g. Ar-and He-based plasmas) in order to study the in situ cleaning (prior to metal deposition) of InGaAs layers dedicated to the realisation of self-aligned contacts. For the characterisation of cleaning efficiency, we performed surface analyses like X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy in attenuated total reflection mode. The first results described in this work are encouraging. We have found efficient processes for removing totally or partially III-V native oxides.

Published
2015
Full Text
View/download PDF

21. Influence of the substrate on the solid-state reaction of ultra-thin Ni film with a In$_{0.53}$Ga$_{0.47}$As under-layer by means of full 3D reciprocal space mapping

Author

Zhiou, S., Rodriguez, Philippe, Gergaud, Patrice, Nemouchi, Fabrice, Nguyen, Thanh Tra, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), CRG et Grands Instruments (CRG), Institut Néel (NEEL), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF), ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), ANR-11-EQPX-0010,CRGF,Lignes synchrotron françaises à l'ESRF(2011), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), CRG & Grands instruments (NEEL - CRG), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)

Subjects
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; We studied the solid-state reaction of Ni thin films with InGaAs layers grown on InP or Si substrates. The inter-metallics obtained carried an hexagonal structure, but yielded a difference in orientation regarding either the substrates or the annealing temperature.

Published
2015
Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results