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Robotic exploration in dynamic and complex environments requires advanced adaptive mapping strategies to ensure accurate representation of the environments. This paper introduces an innovative grid flex-graph exploration (GFGE) algorithm designed for single-robot mapping. This hardware-scheme-based algorithm leverages a combination of quad-grid and graph structures to enhance the efficiency of both local and global mapping implemented on a field-programmable gate array (FPGA). This novel research work involved using sensor fusion to analyze a robot's behavior and flexibility in the presence of static and dynamic objects. A behavior-based grid construction algorithm was proposed for the construction of a quad-grid that represents the occupancy of frontier cells. The selection of the next exploration target in a graph-like structure was proposed using partial reconfiguration-based frontier-graph exploration approaches. The complete exploration method handles the data when updating the local map to optimize the redundant exploration of previously explored nodes. Together, the exploration handles the quadtree-like structure efficiently under dynamic and uncertain conditions with a parallel processing architecture. Integrating several algorithms into indoor robotics was a complex process, and a Xilinx-based partial reconfiguration approach was used to prevent computing difficulties when running many algorithms simultaneously. These algorithms were developed, simulated, and synthesized using the Verilog hardware description language on Zynq SoC. Experiments were carried out utilizing a robot based on a field-programmable gate array (FPGA), and the resource utilization and power consumption of the device were analyzed. [ABSTRACT FROM AUTHOR]

To improve performance in terms of overshoot and motor response speed when a permanent-magnet synchronous motor (PMSM) with a proportional–integral (PI) controller is subjected to external disturbances, this paper proposes a speed control strategy based on an enhanced Beetle Antennae Search algorithm, which allows for adjustable parameters of the PI controller within a certain range. Firstly, to enhance the global and local search capabilities of each individual beetle, the step size was improved by linearly decreasing it. Secondly, a simulation model of a PMSM closed-loop control system was built to verify the effectiveness of the improved Beetle Antennae Search (BAS) algorithm. Finally, a linear feedback shift register model that generates four random numbers was developed on a field-programmable gate array (FPGA). The improved BAS algorithm for the PMSM control system was implemented on an FPGA using the Verilog hardware description language, and the feasibility of the system was verified through hardware simulation. Additionally, the hardware resource consumption on different FPGA platforms was analyzed. The simulation results demonstrate that the proposed new speed control strategy can reduce the overshoot and improve the motor response speed. [ABSTRACT FROM AUTHOR]

In Healthcare 4.0, Wireless Body Area Networks (WBAN) takes place a major role in gathering real-time data of patients. The gathered real-time medical data is transferred through an insecure channel which may lead to several security attacks. To secure from these attacks, the methodology adopted in this work involves the use of a lightweight secure anonymous authentication scheme with location privacy and the implementation of a WBAN system using a cadence tool. Moreover, the methodology encompasses several stages, including initialization, registration, authentication, and location privacy. Further, the study adopts a systematic approach to address key challenges, such as integrity, privacy, security, and non-repudiation. The hypothesis underlying this research is that WBANs can provide accurate and real-time healthcare monitoring using an anonymous authentication scheme and validated by using cadence software. In this work, a digital signature-based cryptographic technique is used to verify the authenticity and integrity of the messages. The security analysis section proves that the system is efficient in resisting different security attacks. Though there are several existing works related to authentication, the proposed protocol is very efficient in terms of performance analysis parameters which are validated using Cygwin software. Computational cost is diminished by 13% and communication overhead is reduced by 32% when compared to the relevant recent works. Additionally, a practical hardware approach is designed using a Verilog Hardware description language and implemented in hardware on an Arty A7-100 SoC FPGA (Silicon on Chip Field Programmable Gate Array) Development board where the number of bonded IOBs utilization is only 10% and lastly synthesized using a Cadence tool with CMOS GPDK 90 nm technology. [ABSTRACT FROM AUTHOR]

Due to reset process of phase frequency detector (PFD), the induced blind zone degrades the acquisition performance of phase-locked loop. Most of reported blind-zone free solutions are based on transistors, which cannot be implemented with field programmable gate array (FPGA). Therefore, a blind zone-suppressed PFD suit for FPGA is proposed in this paper. If any trigger condition of blind zone is met, the proposed reset mask or edge recovery operation is active. Thereafter, the corresponding edge of detected clock is kept or recovered to alleviate the effect of blind zone. At last, the proposed PFD is written by Verilog hardware description language, and implemented with Xilinx Virtex-7 XC7VX330TFFV1157-3. The occupied resources are 9 LUTs and 15 FFs, and the logic delay of critical path is only 0.264ns. The correctness of blind zone-suppressed PFD is also verified by simulation results. [ABSTRACT FROM AUTHOR]

Motion Estimation is one of the main tasks behind any video encoder. It is a computationally costly task; therefore, it is usually delegated to specific or reconfigurable hardware, such as FPGAs. Over the years, multiple FPGA implementations have been developed, mainly using hardware description languages such as Verilog or VHDL. Since programming using hardware description languages is a complex task, it is desirable to use higher-level languages to develop FPGA applications.The aim of this work is to evaluate OpenCL, in terms of expressiveness, as a tool for developing this kind of FPGA applications. To do so, we present and evaluate a parallel implementation of the Block Matching Motion Estimation process using OpenCL for Intel FPGAs, usable and tested on an Intel Stratix 10 FPGA. The implementation efficiently processes Full HD frames completely inside the FPGA. In this work, we show the resource utilization when synthesizing the code on an Intel Stratix 10 FPGA, as well as a performance comparison with multiple CPU implementations with varying levels of optimization and vectorization capabilities. We also compare the proposed OpenCL implementation, in terms of resource utilization and performance, with estimations obtained from an equivalent VHDL implementation. [ABSTRACT FROM AUTHOR]

To address the defects of high complexity, large power consumption and poor practicability of current WBAN security schemes, this paper proposed a combined chaotic flow encryption scheme to meet the requirements of high security and low power consumption in WBAN. The algorithm consisted of three quantization accuracy, it firstly used tent map to interfere with the orbit of logistic map and generate chaotic sequences, then generated the key stream by combining the m sequences with good equilibrium and autocorrelation, and finally got the ciphertext after the XOR operation with the plaintext. This paper used Verilog hardware description language to describe the algorithm and implemented board level verification on FPGA. Through the security test of standard gray image, the information entropy of encrypted image reached 7. 999 4, and the correlation coefficient of adjacent pixels was close to 0. The results show that the algorithm has better correlation and higher information entropy compared with the existing algorithms. [ABSTRACT FROM AUTHOR]

Dual three-phase permanent magnet synchronous motor has been widely used for its reliable performance, high control precision, small output torque ripple and other advantages. In view of the control requirements of high reliability, high precision and small volume of servo motor in aerospace field, this study proposes a servo control algorithm and a specific implementation scheme of dual three-phase permanent magnet synchronous motor based on monolithic FPGA. Based on the hardware platform of Xilinx Kintex7 series XC7 K325 TFFG900 FPGA chip, the vector control algorithm of dual three-phase three-ring permanent magnet synchronous motor based on double DQ coordinate transformation is realized by Verilog hardware description language. In the verification of the experimental platform, the core control indicators of the current loop bandwidth of 600 Hz and the servo position loop bandwidth of 12 Hz have been achieved. [ABSTRACT FROM AUTHOR]

In the recent years, the infrared technology has significantly improved the development of science and technology, the military, industry and medical care. It also overcomes many failures in traditional visible light images. However, the output response error of the sensor is caused by the defective hardware of the infrared sensor and the lack of manufacturing technology, which affects the image quality. In this paper, the common infrared image problem is aimed to solve with a correction on the gray-scale dynamic range. This study also proposes a new high-performance compensation algorithm. It uses a redesigned linear conversion architecture to enhance image details through a segmented method, and improve compensation. In addition, the hardware design and bit size of the multiplier is improved. Compared to traditional histogram equalization, the use of hardware resources is significantly reduced. Especially, the compensation part is integrated into the combined logic circuit for implementation and the pipeline technology should be included to reduce time-consuming. The hardware architecture is described in Verilog hardware description language (HDL) via field-programmable gate array (FPGA). The chip, used to perform and verify functions, is Xilinx Kintex-7, while its operating frequency and the hardware resource size used is 105 MHz and 458 LUTS, respectively. [ABSTRACT FROM AUTHOR]

As CNNs are widely used in fields such as image classification and target detection, the total number of parameters and computation of the models is gradually increasing. In addition, the requirements on hardware resources and power consumption for deploying CNNs are becoming higher and higher, leading to CNN models being restricted to certain specific platforms for miniaturization and practicality. Therefore, this paper proposes a convolutional-neural-network-processor design with an FPGA-based resource-multiplexing architecture, aiming to reduce the consumption of hardware resources and power consumption of CNNs. First, this paper takes a handwritten-digit-recognition CNN as an example of a CNN design based on a resource-multiplexing architecture, and the prediction accuracy of the CNN can reach 97.3 percent by training and testing with Mnist dataset. Then, the CNN is deployed on FPGA using the hardware description language Verilog, and the design is optimized by resource multiplexing and parallel processing. Finally, the total power consumption of the system is 1.03 W and the power consumption of the CNN module is 0.03 W under the premise of guaranteeing the prediction accuracy, and the prediction of a picture is about 68,139 clock cycles, which is 340.7 us under a 200 MHz clock. The experimental results have obvious advantages in terms of resources and power consumption compared with those reported in related articles in recent years, and the design proposed in this paper. [ABSTRACT FROM AUTHOR]

A testbench is built to verify a functionality of a shift register IC (Integrated Circuit) from stuck-at-faults, stuck-at-1 as well as stuck-at-0. The testbench is supported by components, i.e., generator, interface, driver, monitor, scoreboard, environment, test, and testbench top. The IC consists of sequential logic circuits of D-type flip-flops. The faults may occur at interconnects between the circuits inside the IC. In order to examine the functionality from the faults, both the testbench and the IC are designed using SystemVerilog and simulated using Questasim simulator. Simulation results show the faults may be detected by the testbench. Moreover, the detected faults may be indicated by error statements in transcript results of the simulator. [ABSTRACT FROM AUTHOR]

The Space Plasma Environment Research Facility uses a coil system with the corresponding pulsed power supply (PPS) system to generate a very flexible magnetosphere-like magnetic configuration. Its purpose is to investigate the 3D asymmetric reconnection and the processes of trapping, acceleration, and transport of energetic charged particles restrained in a dipole magnetic field configuration, as well as the physical mechanism of the dipolarization front in the magnetotail. The control and monitoring function of the PPS system is realized by the integrated control subsystem, which adopts a two-layer network structure of the control layer and device layer and is developed based on the Experimental Physics and Industrial Control System framework. The control layer includes a remote control system that consists of an engineer station and an operator station and the data storage system. Both the engineer station and operator station are developed by Control System Studio. The data storage system is based on the combination of the Hierarchical Data Format 5 database and MySQL database, and the data management software of the data storage system is developed based on LabVIEW. The synchronous trigger device, the safety interlocking device, the local controller of each set of PPS, and the module controller of each discharge module are the device layer. Their hardware is designed and developed based on the Field Programmable Gate Array, and their software is based on the Quartus II platform and programmed with the Verilog Hardware Description Language language. The function of the integrated control subsystem is verified by the discharge test of the PPS system. [ABSTRACT FROM AUTHOR]

Background: The Number of transistors in recent computer chip has crossed billion mark. The VLSI design is becoming complex day by day. The Verification of such designs is a tedious process as majority of time of development is consumed in verification. Most the blocks in these chips are duplicated or replicated with some change in configuration. Verilog and System Verilog Verification Methodology doesn't have seamless support for reusability of the verification components. Objectives:The verification of Watchdog Timer with APB interface using UVM. Methods: UVM Verification Methodology uses System Verilog framework to build the testbench.UVM methodology defines various verification components. The tests of sequences are kept apart from the original testbench hierarchy which helps in reusability. Results: Watchdog timer with APB interface is designed and verification is done using UVM verification methodology. APB Write / Read and Watchdog Timer functionalities verified. Random stimulus is generated. Conclusions: Successfully designed the Watchdog Timer with APB interface by using Verilog and simulated with the UVM based Testbench. The main advantages of this method of verification are using the virtual random coverage driven, for which the verification engineer takes minimal time for verification in the complex design system. The tests and Verification components can be reused in a different design which uses APB Interface. [ABSTRACT FROM AUTHOR]

Cryptography is very important now-a-days for data security and integrity as the ecommerce and internet applications has increased. But, it has least importance in many cases because of extra memory and other requirements needed for the implementation. The main aim of this work is to implement Advanced Encryption Standard (AES) Encryption using Verilog. To protect data like electronics, cryptographic algorithms are used. The digital information can be encrypted and decrypted by the block cipher of AES algorithm. It can be implemented with the key length 128, 192, 256 bits. Each round of encryption associated with delay can be reduced by AES parallel design. For storing plain text, keys, and intermediate data, we construct two specific register banks, Key-Register and State-Register. Shift-Rows are inserted into the State-Register to save space. We build an efficient 8-bit block for Mix-Columns with four internal registers that take 8-bit and send out 8-bit to adapt the Mix-Column to an 8-bit data stream. For the key expansion and encryption phases, shared optimized Sub-Bytes are also used. We consolidate and simplify various Sub-Bytes to make them more efficient. The clock gating method is used in the design to decrease power consumption. This study provides a 256-bit AES architecture based on Image Cryptography. This design is built-in Verilog HDL on an FPGA XC3S 200 TQ-144, simulated using Modalism 6.4 c, and synthesized with the Xilinx tool. [ABSTRACT FROM AUTHOR]

A finite impulse response (FIR) filter is an essential component of any DSP and communication system. The adder and multiplier are two important components of filter architecture. Different adders and multipliers are available in digital circuits, but designing efficient filters requires an efficient adder and multiplier design. To achieve effective computation, the various existing functions of adders are classified, such as the carry select, ripple carry adder, which consumes more area, delay, and power. A novel carry save adder is combined with a structured Wallace tree multiplier and implemented into the digital filter to improve the efficiency of digital design. This novel carry save adder is built with majority logic and implemented in a digital FIR filter. This modified adder and multiplier overcomes the existing drawbacks. It is implemented using Verilog HDL. Compared to other adder techniques, the proposed majority logic produces optimal solutions. This new technique uses less power, has a delay-free carry circuit, and has fewer gate counts. [ABSTRACT FROM AUTHOR]

This article presents a fast direct pulsewidth modulation (PWM) algorithm for the conventional matrix converters developed in Verilog hardware description language. All PWM duty cycle calculations are performed in one cycle by an atomic operation designed as a digital module using field-programmable gate array basic blocks. The algorithm can be extended to any number of output phases. The improved version of the discontinuous direct analytic voltage PWM (DAV-PWM) method is proposed, in which the use of trigonometry, angles, and program loops has been eliminated. The proposed DAV-PWM is equivalent to the space vector modulation; it can be applied during input asymmetry and also allows for the control of the displacement input angle. The proposal has been verified using the circuit simulation in PSIM, digital structure modeling in ModelSim, and finally through an experiment. [ABSTRACT FROM AUTHOR]

The present work deals with the use of biphasic codes for their application as an exciting signal in pulse compression radars. Its main characteristics are exposed and the digital design of sections for modulation, reception and compression is described. Very High-Speed Integrated Circuit Hardware Description Language (VHDL) was used for its implementation and MATLAB® for simulation, modelling and synthesis in VHDL of functional blocks. A 32-bits code is used with witch a 20.56 dB Peak to Sidelobe Level Ratio (PSR) is guaranteed. The contribution of the proposal lies in the demonstration of two convolution synthesis methods for the BPSK signal. Is presented and described its finite difference equation that define both of the convolution methods and also presented main resources used for their synthesis on DE10-Standard Development Kit. [ABSTRACT FROM AUTHOR]

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models. [ABSTRACT FROM AUTHOR]

This paper presents the design of improved redundant binary adder (IRBA) by utilizing positive–negative encoding rules in FPGA platform. The proposed design deals with inverted encoding of negative binary (IEN) and positive binary number to get addition result using readily available standard hardware module. The Verilog hardware description language is used as design entry for synthesis of the proposed architecture in Xilinx ISE Desisn Suite 14.4 software. This structure is realized on Vertex-4 xc4vfx12-12sf363 FPGA device. The proposed IRBA is found to be time efficient in comparison with the performance parameters such as propagation delay and area over previous reported architecture. [ABSTRACT FROM AUTHOR]

This paper proposes field-programmable gate array (FPGA) acceleration on a scalable multi-layer perceptron (MLP) neural network for classifying handwritten digits. First, an investigation to the network architectures is conducted to find the optimal FPGA design corresponding to different classification rates. As a case study, then a specific single-hidden-layer MLP network is implemented with an eight-stage pipelined structure on Xilinx Ultrascale FPGA. It mainly contains a timing controller designed by Verilog Hardware Description Language (HDL) and sigmoid neurons integrated by Xilinx IPs. Finally, experimental results show a greater than × 10 speedup compared with prior implementations. The proposed FPGA architecture is expandable to other specifications on different accuracy (up to 95.82%) and hardware cost. [ABSTRACT FROM AUTHOR]

Purpose: In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters. Design/methodology/approach: The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer. Findings: Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively. Originality/value: The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively. [ABSTRACT FROM AUTHOR]

Elliptic curve cryptography provides a widely recognized secure environment for information exchange in resource-constrained embedded system applications, such as Internet-of-Things, wireless sensor networks, and radio frequency identification. As the elliptic-curve cryptography (ECC) arithmetic is computationally very complex, there is a need for dedicated hardware for efficient computation of the ECC algorithm in which scalar point multiplication is the performance bottleneck. In this work, we present an ECC accelerator that computes the scalar point multiplication for the NIST recommended elliptic curves over Galois binary fields by using a polynomial basis. We used the Montgomery algorithm with projective coordinates for the scalar point multiplication. We designed a hybrid finite field multiplier based on the standard Karatsuba and shift-and-add multiplication algorithms that achieve one finite field multiplication in m/2 clock cycles for a key-length of m. The proposed design has been modeled in Verilog hardware description language (HDL), functionally verified with simulations, and implemented for field-programmable gate array (FPGA) devices using vendor tools to demonstrate hardware efficiency. Finally, we have integrated the ECC accelerator as an AXI4 peripheral with a synthesizable microprocessor on an FPGA device to create an elliptic curve crypto-processor. [ABSTRACT FROM AUTHOR]

Purpose: A high-precision gyroscope is an important tool for accurate positioning, and the amplitude stability and frequency tracking ability of the drive control system are important and necessary conditions to ensure the precision of micro-electro-mechanical systems (MEMS) gyroscopes. To improve the precision of MEMS gyroscopes, this paper proposes a method to improve the amplitude stability and frequency tracking ability of a drive control system. Design/methodology/approach: A frequency tracking loop and an amplitude control loop are proposed to improve the frequency tracking ability and amplitude stability of the drive control system for a MEMS gyroscopes. The frequency tracking loop mainly includes a phase detector, a frequency detector and a loop filter. And, the amplitude control loop mainly includes an amplitude detector, a low-pass filter and an amplitude control module. The simulation studies on the frequency tracking loop, amplitude control loop and drive control system composed of these two loops are implemented. The corresponding digital drive control algorithm is realized by the Verilog hardware description language, which is downloaded to the application-specific integrated circuits (ASIC) platform to verify the performances of the proposed method. Findings: The simulation experiments in Matlab/Simulink and tests on the ASIC platform verify that the designed drive control system can keep the amplitude stable and track the driving frequency in real time with high precision. Originality/value: This study shows a way to design and realize a drive control system for MEMS gyroscopes to improve their tracking ability. It is helpful for improving the precision of MEMS gyroscopes. [ABSTRACT FROM AUTHOR]

The validation of the measurements quality after on-site diagnostic system installation is necessary in order to provide reliable data and output results. This topic is often neglected or not discussed in detail regarding measurement systems. In the paper recently installed system for soft X-ray measurements is described in introduction. The system is based on multichannel GEM detector and the data is collected and sent in special format to PC unit for further postprocessing. The unique feature of the system is the ability to compute final data based on raw data only. The raw data is selected upon algorithms by FPGA units. The FPGAs are connected to the analog frontend of the system and able to register all of the signals and collect the useful data. The interface used for data streaming is PCIe Gen2 x4 for each FPGA, therefore high throughput of the system is ensured. The paper then discusses the properties of the installation environment of the system and basic functionality mode. New features are described, both in theoretical and practical approach. New modes correspond to the data quality monitoring features implemented for the system, that provide extra information to the postprocessing stage and final algorithms. In the article is described also additional mode to perform hardware simulation of signals in a tokamak-like environment using FPGAs. The summary describes the implemented features of the data quality monitoring features and additional modes of the system. [ABSTRACT FROM AUTHOR]

The scale of integration of processors has increased in recent decades, new challenges have emerged and chip area has become an important issue. Designers have been motivated to seek new techniques and technologies, among them, the multi-value logic (MVL). The quaternary representation, domain D: {0, 1, 2, 3} reduces the number of connections due to the fact that, approximately, 70% of the circuit area is being used for interconnections and pads. This work proposes the design of a four stages pipelined quaternary processor (eCPU) with sixteen instructions and the handling of hazards utilizing hybrid (static and dynamic) techniques with the scope to demonstrate the correct functionality with respect to the design specification, based on a universal set of quaternary logic gates already proposed in the literature. The eCPU has been designed via hardware description in Quartus-environment written in VHSIC Hardware Description Language (VHDL) and simulations performed in ModelSim-, demonstrating the correct behavior with respect to the specifications. The simulations are performed by executing several programs written in the chosen quaternary assembly language with the support of a two phase's compiler written in Java to generate quaternary machine code. [ABSTRACT FROM AUTHOR]

Satellite broadcasting systems are an economical alternative for the deployment of television and other services in sparsely populated and difficult to access areas. This paper presents the modeling and hardware implementation of a DVB-S receiver according to the specifications contained in the EN 300 421 standard. The receiver is modeled and validated within the Simulink environment. From the validated model, an equivalent VHDL code is generated using the HDL Coder and HDL Verifier tools. Both Simulink synthesizable HDL modules and Xilinx Core Generator IP modules are used in the design for implementation and validation in a hardware environment, using the FPGA in the Loop tool. A comparison is made between implementation with native HDL blocks from the Simulink environment and the use of modules from the Xilinx platform. [ABSTRACT FROM AUTHOR]

Summary: Approximate computing‐based arithmetic units are oriented towards reduction in power, delay, and area. Intrinsic error tolerance capability of emerging application domains, like multimedia, Internet of Things (IoT), and image processing provides better opportunities for optimization of approximate arithmetic units. In this paper, a novel 1‐bit imprecise full adder (IFA) is proposed with less gate count. Also, two versions of 16‐bit error tolerant adders (ETAs), namely a low power and area efficient error tolerant adder (LETA) and improved low power and area efficient error tolerant adder (ILETA), are proposed. In these proposed ETAs, the most significant bit (MSB) segments are realized in same approach, whereas the least significant bit (LSB) segment of LETA and ILETA are realized using an existing modified full adder (MFA) and proposed IFAs, respectively. The proposed and existing ETA adders are implemented using a Verilog hardware description language (HDL) and synthesized in a Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65nm technology. The proposed (ILETA, LETA) adders exhibit (55%, 50%) reduction in power consumption and achieve significant reduction in area (68%, 61%). Further, in this work, a new performance metric namely power and error product (PEP) is proposed in order to evaluate the approximate adders in terms of power and error metrics. It is found that the proposed ILETA achieves a low PEP of 1.05 ×10−5 compared with other ETAs. To study the efficacy of the proposed ETA adders in image processing application, an image blending algorithm is implemented and simulated using MATLAB. From simulation results, it is observed that the proposed ETA adders exhibit a high peak signal‐to‐noise ratio (PSNR). [ABSTRACT FROM AUTHOR]

Field-programmable gate-array (FPGA)-based intelligent hardware modules are increasingly being used in safety systems of nuclear power plants. Qualification of these modules as per safety standards such as IEC 62566/60880 and IEEE-7.4.3.2-2010 needs considerable effort. Many of the safety standards demand high rigor in verifying that the designs of these modules meet the design intent. Use of hardware description languages such as VHDL or Verilog makes the process of code review and verification difficult due to the complex nonsequential semantics of these languages. It is now recognized that formal verification offers a complementary approach to conventional verification. Formal verification tools perform analysis of designs based on language semantics to prove/refute their functional correctness. In this article, we present the architecture of a formal verification tool for VHDL designs and our experience of using this tool on VHDL designs in nuclear applications. [ABSTRACT FROM AUTHOR]

Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system. [ABSTRACT FROM AUTHOR]

Cognitive radio allows opportunistic spectrum access by finding and using temporally and spatially unused radio channels to enhance the utilization of scarce radio spectrum. Various spectrum sensing techniques have been proposed to detect the availability of unoccupied radio channels. In this article, we first briefly discuss the merits of various spectrum sensing techniques. We then present an efficient hardware architecture for energy detection-based spectrum sensing. We discuss various design parameters and features, such as transform length, window selection, window overlap, ensemble averaging, and dynamic thresholding for efficient realization of the designed spectrum sensing module. Then, an efficient hardware architecture for an optimal energy detection-based spectral estimator is presented. To reduce the computational complexity, we utilize a polyphase filter structure. For the high-performance implementation of the proposed spectrum sensing architecture, we use cutset retiming, and for the compact realization, we use the time-multiplexing technique to reuse hardware resources. We model our spectrum sensing module in both floating-point and fixed-point representations using our custom-developed library of numerical operations. The synthesizable parameteric model of the energy detection-based spectrum sensing module is developed in Verilog hardware description language. The architecture of the designed spectrum sensing module is implemented on a Xilinx Virtex-7 field-programmable gate array and operates at 327 MHz. The cycle-accurate bit-true hardware simulation results are verified against its fixed-point software simulation results. An ASIC architecture of the designed spectrum sensing module is estimated to occupy 5.65 mm 2 and dissipate 9.10 mW from a 1.05-V supply while operating at 200 MHz in a standard 32-nm CMOS technology for a 200 MHz bandwidth. [ABSTRACT FROM AUTHOR]

In the conventional distribution network mostly overcurrent (OCR) relays are in use, however, in case of microgrid the direction of power changes with operating conditions, the need of directional feature of the relay has become a must. Therefore, in this article, the design and hardware prototype of a soft-core directional-OCR (DOCR) on Field Programable Gate Array (FPGA) using a modular design approach is presented. A digital phase detection module has been developed for the estimation of the direction of current flowing through the power system network. A parallel architecture for phase and tripping time computation is used in the proposed design that makes the developed relay faster by reducing the computation time of the algorithm. The Integer arithmetic Verilog hardware description language platform is used to optimize the computational burden and hardware resources. Also, in the developed relay, inverse characteristics viz. extreme inverse and very inverse characteristics of OCR are emulated. The design is implemented on the Virtex ML-505 FPGA development board. The performance of the DOCR is tested by creating the faults at different locations with different values of time dial settings and plug-point-multiplier. Hardware-in-loop verification of the relay is carried out with the real-time-digital simulator and FPGA. The results are compared with the standard DOCR of the RTDS to successfully verify the operation of the designed relay under different fault conditions. [ABSTRACT FROM AUTHOR]

Recent advances in fabrication complexity and density—especially for the Institute of Advanced Industrial Science and Technology (AIST) advanced process 2 (ADP2) process and the MIT Lincoln Lab (MITLL) SFQ5ee process and beyond—allow the implementation of a superconducting field-programmable gate array (SFPGA) with sufficient complexity to host a number of different programmed functions. We discuss design choices for an all single flux quantum SFPGA targeting these modern processes, making heavy use of passive transmission line (PTL) layers they provide. Various configurations for lookup tables, basic logic elements and timing schemes are shown, and a viable switch block implementation is discussed. Academic FPGA electronic design automation (EDA) tools are repurposed for mapping Verilog hardware description language (HDL) functions to the chosen SFPGA design, whilst HDL and electrical simulations are used to show its correct operation. We show simulations for programming and the operation of an SFPGA, and discuss die size requirements for practical implementation. [ABSTRACT FROM AUTHOR]

Principal component analysis (PCA) is one of the widely used techniques for dimensionality reduction in multivariate statistical analysis. This article presents an efficient architecture design and implementation of the PCA algorithm on a field-programmable gate array (FPGA). The designed reconfigurable architecture is modeled in both floating-point and fixed-point representations using our custom-developed library of numerical operations. The PCA architecture supports input dataset matrices with parameterizable dimensions. The synthesizable model of the PCA architecture is modeled in Verilog hardware description language, and its cycle-accurate and bit-true simulation results are verified against its software simulation models. The characteristics and implementation results of the PCA architecture on a Xilinx Virtex-7 FPGA and in a standard 45-nm CMOS technology are presented. The execution times of the implemented PCA system on the FPGA for different data sizes are compared with those of the graphics processing unit and general-purpose processor implementations. To the best of our knowledge, this work is the first high-throughput design and implementation of the reconfigurable PCA architecture, including both the learning and mapping phases, on a single FPGA. [ABSTRACT FROM AUTHOR]

High efficient video coding (HEVC) succeeds dual coding efficiency development contrasted to its predecessor H.264/MPEG-4 AVC. Though, it experiences high computational complexity caused by its quad-tree structure in motion estimation (ME). The full search ME (FSME) procedure can fundamentally raise the video encoder compression ratio (CR) while maintaining high video quality, but it is also fundamentally expensive and can comprise of more than 45% of the entire motion estimation method. The consecutive rate-constrained elimination technique (CRCE) safely removes contender motion vectors while saving the best aspirant chosen by the full search block motion estimation (FSBME) method. However, these methods have been failed to consume less power. This paper proposes low power oriented full search block based motion estimation (LP-FSBME) algorithm. The proposed algorithm decomposes every block into subsequent sub-pixel blocks by computing the sum of absolute difference (SAD) values of sub-pixel search locations utilizing the SAD benefits of neighboring integer pixel search areas for best motion vector (MV) and it diminishes the computational complexity. The proposed method hardware design is implemented with Verilog Hardware Description Language (Verilog-HDL) and synthesized by Xilinx Virtex 7 FPGA XC7VX1140T device with speed grade 1 in Xilinx software version 14.5. The proposed method is checked videos occupied 754 K gate counts, 4410 Look Up Tables (LUTs), 3312 Registers, maximum occupied frequency is 204 MHz, maximum power consumption is 40.14 mW in 1080 pixels @ 30 frames per second. [ABSTRACT FROM AUTHOR]

Highlights • A single set of Memristor crossbar array is extended for bidirectional synaptic weighting operation, which is convenient and cost-effective in hardware implementation of artificial neural networks. • The on-chip learning circuits and related learning algorithm for memristive BAM are considered to train the system to memorize pattern pairs, together with a novel programming strategy to ease the process of tuning memristance. • We have implemented and demonstrated meaningful pattern can be trained and recalled by the proposed memristive BAM system. • BAM neuron activation function is realized by digital circuit element JK flip-flop. • The Verilog-AMS design methodolgy adopted in this study can be a good candidate for system level design of memristor-based large scale ANN circuit when both digital circuit element and analog memristors are employed. Abstract Recently, memristor as an emerging device has been used as the basic synapse realization component for the circuit implementation of artificial neural networks. Following this trend, this paper studies the circuit realization of a memristor-based bidirectional associative memory (BAM) system that extends the memristor crossbar array structure for bidirectional synaptic weighting operation. The neuron cell in BAM is represented by digital circuit element JK flip-flop for hardware cost-saving. Meanwhile a novel memristor programming strategy is also considered and examined to ease the on-chip learning. The design of such memristive BAM circuit system is conducted by hardware description language Verilog-AMS and has been validated in a commercial circuit simulation environment via a case study. Test results show that a set of binary character patterns can be memorized and recalled successfully by the trained memristive BAM system. [ABSTRACT FROM AUTHOR]

Binary Neural Networks (BNNs) have reached recognition performances close to those achieved by classic non-binary variants, enabling machine learning to be processed near-sensor or on the edge. The paper researches massively parallel combinational BNN logic and how it is to be used in real-world deployment situations which include training and constructing networks for imaging, cybersecurity and high-energy physics applications. For each field, a hardwired Verilog Hardware Description Language (HDL) code is built. It is synthesized for an FPGA system to create designs for a set of concrete edge processing problems. Synthesis results show that BNNs use minimal resources and achieve less than 30 ns inference delays, which is crucial for high-speed applications, less than 2 W power consumption and less than 60 k FPGA slices. It is shown that parallel BNNs enable efficient hardware machine learning performance for a variety of edge processing problems. [ABSTRACT FROM AUTHOR]

Abstract The design of integrated circuits (ICs) is typically done using low level Hardware Description Languages (HDLs) like Verilog or VHDL (Register Transfer Level). These enable the full controllability of the generated hardware design as they allow to specify the detailed behaviour and structure of the architecture, at every single clock cycle. The main drawback of using these low level HDLs is that takes very long time to create and verify large ICs with them. Moreover, it is hard to re-use HDL code for future projects that require changes in the micro-architecture. Thus, the industry is moving the level of abstraction to C-based VLSI design where designers only have to specify the functionality of the program and High-Level Synthesis (HLS) tools generate the HDL automatically. One additional benefit of C-based VLSI design is that it enables to explore the search space of possible micro-architectures from a single behavioral description. The result of a Design Space Exploration (DSE) is a trade-off curve of Pareto-optimal designs with unique area vs. performance metrics. Most VLSI design companies have large amounts of legacy HDL code. Thus, it makes sense to have an automatic flow to convert HDL designs into behavioral descriptions (e.g. C, C++ or SystemC) optimized for HLS DSE. This implies that the generation of explorable constructs, e.g. loops and arrays, which upon exploration, lead to very different micro-architectures (e.g. loops can be unrolled or folded, arrays can be mapped to RAMs or registers). In this paper, we propose a robust RTL to C translation method called VeriIntel2C to abstract RTL descriptions (written in Verilog) into ANSI-C descriptions optimized for HLS DSE by generating a large number of loops and arrays. Our method is able to generate these explorable constructs with the use of extended Hardware Petri Nets to extract the behaviour of the Verilog designs and to generate a Control Data Flow Graph (CDFG) that allows the easy identification of these constructs. From the experimental results, we are able to demonstrate that VeriIntel2C expands the design space considerably and also improves the quality of design space by 55% on average compared to previous work, on a wide range of designs. Highlights • Corrected C code as average filter. • Moved example after related work. • Moved 'motivational example' section after related work. • Corrected graph in Figs. 8–10. [ABSTRACT FROM AUTHOR]

This paper presents a frequency domain analysis of spurious tones in frequency dividers. The results of the analysis are used to develop an event-driven model for system simulations which work entirely in the frequency domain. The proposed approach is able to provide a fast and accurate model in a SystemVerilog/C++ environment which takes the frequency conversion effects of the spurious tones into account. A virtual prototype which includes the model was simulated and due to the fast simulation speed it was possible to determine the influence of spurious tones on the bit error rate in a complex receive scenario. [ABSTRACT FROM AUTHOR]

Highlights • A tunnel FET compact model is developed including crucial non-idealities such as the trap assisted tunneling. • The compact model is tested against experimental data achieving excellent fit. • Compact expressions describing details of TFET device physics are developed. • A Verilog-A model is developed on the basis of the compact model and simple TFET circuits are simulated. • The compact model can be used to benchmark TFET technology for varying degrees of non-idealities and other device parameters. Abstract We present a compact model for Tunnel Field Effect Transistors (TFET), that captures several non-idealities such as the Trap Assisted Tunneling (TAT) originating from interface traps ( D it ), along with Verilog-A implementation. We show that the TAT, together with band edge non-abruptness known as the Urbach tail, sets the lower limit of the sub-threshold swing and the leakage current at a given temperature. Presence of charged trap states also contributes to reduced gate efficiency. We show that we can decouple the contribution of each of these processes and extract the intrinsic sub-threshold swing from a given experimental data. We derive closed form expressions of channel potential, electric field and effective tunnel energy window to accurately capture the essential device physics of TFETs. We test the model against recently published experimental data, and simulate simple TFET circuits using the Verilog-A model. The compact model provides a framework for TFET technology projections with improved device metrics such as better electrostatic design, reduced TAT, material with better transport properties etc. [ABSTRACT FROM AUTHOR]

Runtime monitors detect vulnerabilities in embedded systems by running alongside untrusted software in order to detect violations of security policies as they occur, ideally with minimal overhead. Prior work has demonstrated language support for largely static security policies implemented using lattices and tag-based monitors. However, compiling high-level policies to modular hardware monitors that can implement a wide variety of security policies with minimal power has not been previously proposed. In this paper, we present a high-level security policy language, GARUDA, together with a compiler from GARUDA to Verilog, that enables the modular construction and composition of security hardware runtime monitors for a variety of security policies, including software fault isolation, secure control flow, and dynamic information flow via taint tracking. Unlike prior approaches in which the hardware monitors check all instructions, our hardware monitors are activated on-demand by the security policies which reduces the energy consumption. We perform experiments on Sniper, a full system multicore simulator, to evaluate the energy and performance tradeoffs of the security policies we have implemented so far. The policies are tested across a range of Splash-2 benchmarks. [ABSTRACT FROM AUTHOR]

The increase in complexity of superconducting single flux quantum circuits enabled by the IARPA Cryogenic Computing Complexity project has highlighted the need for hardware description language (HDL) models that allow fast and reliable simulation and verification of such circuits. The design of new cell libraries for successive nodes of fabrication processes also exposed the cost of building new HDL models for each cell library. We expand an automatic HDL extraction method presented earlier to provide a fully automated tool for timing model extraction from an arbitrary cell the functionality of which does not need to be known. We describe in detail how models for the Verilog HDLs are constructed to allow timing verification and to implement delays as functions of bias, process tolerances, thermal noise, and load. Modeling of wire length delays is discussed, and results presented for complex circuits synthesized with new place-and-route algorithms. [ABSTRACT FROM AUTHOR]

Abstract Analog/Mixed-Signal (AMS) design and verification strongly relies on more or less abstract models to make extensive simulations feasible. Maintaining consistent behavior between system model and implementation is crucial for a correct verification. Besides the functionality, this also involves the operating conditions: A faulty model might introduce false-positive verification results despite of e.g. an incorrect supply voltage. We propose a novel method to compare a model to its implementation and automatically generate a model safe-guard unit from transistor-level simulation data. By using the concept of system acceptance region, we transfer the information about valid operating conditions to a higher level of abstraction. We introduce this unit into a purely functional VerilogAMS model to check the validity in the simulated environment. This method can be used to significantly reduce the risk of erroneous verification results on system level. We demonstrate our approach using a demodulator circuit of a passive RFID tag. The model is automatically augmented with additional checks derived from an exploration of the underlying circuits' parameter space. By comparing the risk of false-positive simulation results, we prove that the design risk can be significantly reduced. It is eliminated completely by introducing an additional safety-margin, which drives the coverage up to 100%. Highlights • A novel method for automatic extraction an d synthesis of mixed-signal operating condition checks is proposed. • The method is evaluated using a novel model-coverage measure. • As an application example, a model augmentation for an RFID demodulator circuit is presented. [ABSTRACT FROM AUTHOR]

Optical feedback interferometer (OFI) lasers, also called self-mixing (SM) lasers, have been widely explored over the last couple of decades due to their low cost, compactness, and self-aligned nature and they provide a very good solution for measurements of displacement, vibration, distance, velocity, etc. The SM effect takes place when a part of the laser beam is fed back to the active laser cavity after reflecting from the target. The reflected beam interferes with the emitted beam and hence the optical and spectral characteristics of the laser get changed. To retrieve the vibration or displacement signal of the target from the SM signal, different postprocessing algorithms have been proposed, such as the phase unwrapping method (PUM). The first step of the PUM leads to the coarse estimation of the laser phase and the final step is an iterative joint estimation of 2 parameters, namely laser coupling coefficient C and linewidth enhancement factor α. To make this algorithm applicable for real-time measurements, parallel joint estimation for a wide range of C and α values needs to be done. In this research, 3 algorithms, namely PUM, direct fringe unwrapping (DFU), and improved DFU (IDFU) were tested for FPGA implementation by using Verilog HDL (hardware description language) so that more precise and real-time vibration and displacement signals of targets could be extracted from the SM sensor in an embedded systems environment. These algorithms were developed using Verilog HDL for implementation on the Xilinx Spartan-3 Xcs400-FG320 development board. Our designed IDFU algorithm performed 0.492 times better than the parallel PUM algorithm in maximum clock frequency and 1.53 and 1.21 times better than the PUM in slice registers and LUT utilization of hardware resources, respectively. The designed DFU algorithm can operate 1.355 times better than IDFU in maximum clock frequency and 25.34 and 14.25 times better than IDFU in slice registers and LUT utilization of hardware resources, respectively. [ABSTRACT FROM AUTHOR]