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Using a novel gate-last process scheme that affords precise channel thickness control, we have fabricated self-aligned InGaAs quantum-well (QW) MOSFETs. Devices with a channel thickness between 3 and 12 nm, and a gate length between 40 nm and 5 \mu \textm are fabricated on a heterostructure that includes a composite InGaAs/InAs QW and an InP barrier. It is observed that channel thickness has a strong impact on the device characteristics. In general, a thick channel is beneficial to ON-state figures of merit, including transconductance and effective carrier mobility. However, a thin channel is beneficial to OFF-state metrics, such as subthreshold swing and drain-induced barrier lowering (DIBL). The InAs composition and effective mass that electrons experience in the channel emerges as a factor that significantly affects channel mobility and presumably the transport characteristics of these devices. The subthreshold swing and DIBL are found to follow a classic scaling behavior. This suggests that the InGaAs QW MOSFETs are at the limit of scaling around Lg=50 nm. [ABSTRACT FROM AUTHOR]

A number of recent reports have noted excess OFF-state leakage current ( I\mathrm{{\scriptscriptstyle OFF}}) in scaled InGaAs quantum-well nMOSFETs. There is growing evidence that a combination of band-to-band tunneling (BTBT) and a floating-body bipolar gain effect is responsible for this. Unless this issue is effectively addressed, the scaling potential of this transistor structure will be compromised. This paper presents a detailed study of the physics of I\mathrm{{\scriptscriptstyle OFF}} and explores I\mathrm{{\scriptscriptstyle OFF}} reduction strategies through 2-D device simulations that have been calibrated with experiments. In essence, under OFF conditions at even moderate values of V\textrm {ds} , a BTBT process at the drain-end generates holes in the channel and thereby reduces the source–channel potential barrier. This results in injection of electrons into the channel that contribute to enhanced I\mathrm{{\scriptscriptstyle OFF}} while the holes are injected into the source where they recombine. In a nanoscale device, the bipolar effect that is at play here can have a very large current gain and amplify many fold even a small BTBT current. A study of approaches to mitigating this effect is analyzed here. It is concluded that the most effective strategy is to minimize the bipolar current gain rather than BTBT in scaled transistors. [ABSTRACT FROM AUTHOR]

The Microelectronics WebLab at MIT allows students to do actual (not simulated) laboratory research on state-of-the art equipment through the Internet. This study assesses the use of WebLab in a junior-level course on microelectronic devices and circuits in 2004–05 and 2005–06. In quantitative surveys and qualitative interviews, students and faculty reported that WebLab was effective as an instrument of learning, and grew more so with refinements of the program. WebLab allowed undergraduates to learn at their own pace and on their own schedules. It enabled them to use different processes of learning (intuitive, visual, abstract), and it gave them an opportunity to link individual and collaborative effort in creative combinations. Online laboratories on this model have broad applications in the experimental sciences and in other research-oriented disciplines. [ABSTRACT FROM AUTHOR]

In the presence of prominent gate oxide trapping, the conventional technique for channel mobility extraction in MOSFETs based on I – V/C – V measurements becomes inadequate. This is the consequence of two different effects associated with oxide traps: gate voltage stretch-out and electron trapping and detrapping in the oxide at the megahertz (MHz)-range frequencies that are commonly utilized. In thin-channel planar InGaAs MOSFETs, both effects are observed and found to result in a severe overestimation of mobile charge and subsequently an underestimation of mobility using I – V/C – V. To address this issue, we demonstrate a new mobility extraction technique (RF- ID) based on concurrent I – V and S-parameter measurement in the gigahertz (GHz) regime that is largely immune to oxide trapping. Excellent agreement with Hall measurements as well as with theoretical predictions from Poisson–Schrodinger simulations gives confidence to the new technique. Importantly, the new technique is not limited to InGaAs planar MOSFETs, but applies to any device geometry and any material system. Promising mobility ~1100 cm2/V⋅s is found in quantum-well planar InGaAs MOSFETs with a 4-nm-thick channel. [ABSTRACT FROM AUTHOR]

In this article, a detailed simulation study of high-performance InGaAs quantum-well (QW) MOSFETs is presented. We demonstrate that the limited free carrier density in the access region leads to a significant source starvation effect in the saturation regime, which limits the maximum transconductance (${g}_{m}$). By coupling ballistic 2-D quantum mechanical simulations with an original semiclassical model for source starvation, we are able to reproduce quantitatively the ${V}_{\text {GS}}$ – ${g}_{m}$ characteristics of three successive device generations differing only in the design of their access region. Source starvation is approximated as a quasi-equilibrium phenomenon characterized by a nonlinear, current-dependent voltage drop in the access region that reduces injection into the channel at high currents. Even in the most recent record device with a ${g}_{m}$ peak of 3.45 mS/ $\mu \text{m}$ , source starvation is found to have a negative impact. An extrapolation of our model furthermore suggests that source starvation will become a major performance bottleneck in future device realizations with lower trap densities. [ABSTRACT FROM AUTHOR]

Recently, sub-10-nm-diameter InGaAs vertical nanowire (VNW) MOSFETs have been demonstrated. The key to this achievement was the use of Ni for the top ohmic contact. In this paper, we present a detailed study of the impact of Ni and Mo contacts on the electrical characteristics of highly scaled InGaAs VNW MOSFETs. Sequential annealing experiments are presented that reveal the optimum temperature for each type of contact. A negative temperature dependence of the ON-resistance of 7-nm-diameter Ni-contacted devices suggests the existence of an energy barrier. We also observe an unexpected transconductance and drain-induced barrier loweirng (DIBL) dependence on transistor diameter in Ni-contacted devices as well as abnormal DIBL asymmetry to swapping source and drain. All these results can be explained by Ni diffusing down the nanowire during the contact annealing process, reducing the effective channel length, and creating a Schottky-barrier drain. [ABSTRACT FROM AUTHOR]

The single-event-transient response of InGaAs FinFETs with different fin widths is examined using pulsed-laser and heavy-ion irradiation. Devices with wider fins collect more charge in both environments. Quantum-well structures confine charge collection in the channel, and determine the sensitive volume. Simulations show that the charge density produced by irradiation is similar for devices with different fin widths, but more charge is collected by wider fin devices due to the larger channel volume. Charge accumulated in the buffer and substrate layers modulates the body potential, altering the degree of back-gate control, leading to additional effects associated with charge accumulation in wider fin devices. Optical simulations for a model system suggest that optical phenomena in the fins should be considered for laser testing. These include optical interference, plasmonic enhancement at the metal–dielectric interfaces, and enhanced electron–hole pair recombination due to multiple reflections in multigate devices with nanoscale dimensions. [ABSTRACT FROM PUBLISHER]

We have investigated time-dependent dielectric breakdown in high-voltage AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistors, with a focus specifically on the role of temperature under positive gate stress conditions. We aim toward understanding the temperature dependence of progressive breakdown (PBD) as well as hard breakdown. We find that the temperature dependence of time-to-first breakdown, hard breakdown, and the gate current evolution during PBD all share similar, shallow activation energies that suggest a common underlying mechanism. However, the gate current noise during PBD seems to be independent of temperature and is likely due to a tunneling process. Understanding of temperature-dependent breakdown is essential to developing accurate device lifetime estimates. [ABSTRACT FROM PUBLISHER]

A tunable wavelength laser system and high-resolution transient capture system are introduced to characterize transients in high-mobility MOSFETs. The experimental configuration enables resolution of fast transient signals and new understanding of charge collection mechanisms. The channel layer is critical in the charge collection process for the InGaAs FinFETs examined here. The transient current mainly comes from the channel current, due to shunt effects and parasitic bipolar effects, instead of the junction collection. The charge amplification factor is found to be as high as 14, which makes this technology relatively sensitive to transient radiation. The peak current is inversely proportional to the device gate length. Simulations show that the parasitic bipolar effect is due to source-to-channel barrier lowering caused by hole accumulation in the source and channel. Charge deposited in the channel causes prompt current, while charge deposited below the channel causes delayed and slow current. [ABSTRACT FROM PUBLISHER]

This paper demonstrates InGaAs vertical nanowire (VNW) MOSFETs fabricated via an improved top–down approach, the performance of which is comparable to that of the best bottom–up devices in terms of the balance between transport and electrostatics. These devices, when contrasted with an earlier generation fabricated by a similar technology, have enabled the first experimental study of source/drainasymmetry in InGaAs VNWMOSFETs. The transconductance differs significantly when swapping source and drain due to inherently different top and bottom contact electrical resistance. This also results in distinct asymmetry in the saturation behavior of the output characteristics. On the other hand, diameter nonuniformity along the nanowire (NW) length is responsible for asymmetry in the subthreshold characteristics. A uniform NW cross section, enabled by our improved InGaAs dry etch technology in the present devices, eliminates the asymmetry of the electrostatics, which was observed in our previous work. [ABSTRACT FROM PUBLISHER]

The effects of total-ionizing-dose irradiation are investigated in HfO2/InGaAs quantum-well MOSFETs. Radiation-induced hole trapping is higher for irradiation under positive gate bias than under negative gate bias. Electrical stress-induced electron trapping compensates radiation-induced hole trapping during positive gate-bias irradiation. Stress-induced hole trapping adds to the effects of radiation-induced hole trapping under negative gate bias. Radiation-induced charge trapping increases with the channel length. [ABSTRACT FROM PUBLISHER]

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( V\mathrm{ bs} ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive V\mathrm{ bs} due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate. [ABSTRACT FROM PUBLISHER]

A 2D conductive hole gas in diamond is obtained by exposing diamond to a plasma formed in H 2 or D 2, which terminates the diamond surface with H or D. The diamond is still insulating until it is activated by exposing it to air or overcoating it by atomic layer deposition, ALD, with Al 2 O 3 /SiO 2 or evaporated WO 3. The carrier density of air activated diamond slowly decreases in time, days to weeks, and the carrier mobility increases. However, the carrier density deceases faster than the mobility increases and the diamond's surface resistance increases in time. The mobility is empirically related to the carrier density by a power law, mobility = Q (carrier density)-0.42, where Q is determined by fitting the equation to the data. The value of Q and the surface resistance of the 2D gas depends upon the removal of impurities such as C, K, and Na in the plasma, as well as the offcut angle from the (100) diamonds. These impurities originate from carbon on the chamber walls, the Mo structure that supports the diamond during plasma exposure, impurities on the diamond, such as H 2 SO 4 , after inefficient cleaning, and the carbon from the diamond itself as it is etched in the plasma. Once the impurities are reduced, then the offcut angle of (100) diamond to the [011]-axis generates crystal steps generally parallel to the 0 1 ¯ 1 axis on the diamond surface. Resistance along the steps is lower than perpendicular to the steps. With the impurities removed, six (100) diamonds offcut by ~6° to the [011] axis had resistance parallel to the steps, 0 1 ¯ 1 , vary from 1.32 to 1.95 kΩ sq.−1 with an average of 1.70 ± 0.25 kΩ sq.−1 and perpendicular to the steps, [011], from 1.93 to 3.20 kΩ sq.−1 with an average of 2.51 ± 0.4 kΩ sq.−1. [Display omitted] • H-terminated diamond has surface resistance anisotropy by offcutting (100) diamond 6° to the [011] axis. • Anisotropic resistance 1.32 parallel to [0 1 ¯ 1] and 1.93 K ohms sq.−1 parallel to [011] • Surface crystal steps effect surface resistance, resistance is lower parallel to steps. • Presence of carbon, potassium, and sodium during H termination compromise diamond's surface conduction [ABSTRACT FROM AUTHOR]