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Hardware Trojan Horses have emerged as great threats to modern electronic design and manufacturing practices. Because of their inherent surreptitious nature, test vector generation to detect hardware Trojan horses is a difficult problem. Efficient online detection techniques can be more effective in detection of hardware Trojan horses. In this paper, we propose a low-overhead detection technique which inserts malicious logic detection circuitry at netlist sites chosen by an algorithm that employs an intelligent and accurate analysis of fault propagation through logic gates. Proactive system-level countermeasures can be activated on detection of malicious logic, thereby avoiding disastrous system failure. Experimental results on benchmark circuits show close to 100 percent HTH detection coverage when our proposed technique is employed, as well as acceptable overheads.

The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non-adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd.

Look-up tables (LUT) form the basic logic elements in a large class of modern day field programmable gate arrays (FPGA). With FPGAs increasingly being used in low and medium volume productions, many vendors have improved the capacity and versatility of these devices. The enormous logic capacity inherent in state-of-art FPGAs has made it essential to develop automated computer aided design (CAD) support for logic synthesis using these platforms. Since design entry is the only manual phase in the FPGA CAD-flow, it essentially rules out any scope for technology-dependent optimization, which focusses on achieving optimal mapping of logical functionalities onto the target platforms. Evidently, majority of the work related to the implementation of different arithmetic circuits on FPGAs focuses only on the technology-independent optimizations, where the design process consists of modifying the architecture at the top level without giving any consideration to the mapping of the architecture onto the FPGA device. In this paper, we consider the technology-dependent optimization of the fixed-point bit-parallel multipliers on LUT based FPGAs. Our approach re-structures the initial Boolean network and transforms it into an optimized LUT netlist prior to the design entry phase. The design entry of the optimized netlist is then carried out using instantiation based coding styles. This ensures that the optimizations done prior to the design entry phase remain preserved throughout the synthesis process. We particularly focus on 6-input LUTs that are inherent basic logic elements in state-of-art FPGAs. Theoretical analysis and detailed experimentation using state-of-art Xilinx 7th generation FPGAs reveal a substantial speed-up in performance.

This paper presents a novel hardware Trojan detection technique in gate-level netlist based on the controllability and observability analyses. Using an unsupervised clustering analysis, the paper shows that the controllability and observability characteristics of Trojan gates present significant inter-cluster distance from those of genuine gates in a Trojan-inserted circuit, such that Trojan gates are easily distinguishable. The proposed technique does not require any golden model and can be easily integrated into the current integrated circuit design flow. Furthermore, it performs a static analysis and does not require any test pattern application for Trojan activation either partially or fully. In addition, the timing complexity of the proposed technique is an order of the number of signals in a circuit. Moreover, the proposed technique makes it possible to fully restore an inserted Trojan and to isolate its trigger and payload circuits. The technique has been applied on various types of Trojans, and all Trojans are successfully detected with 0 false positive and negative rates in less than 14 s in the worst case.

Hardware devices of recent technology nodes are intrinsically more susceptible to faults than previous devices. This demands further improvements of error detection methods. However, any attempt to cover all errors for all theoretically possible scenarios that a system might be used in can easily lead to excessive costs. Instead, an application-dependent approach should be taken, i.e., strategies for test and error resilience must target only those errors that can actually have an effect in the situations in which the hardware is being used. In this paper, we propose a method to inject faults into hardware (HW) and to formally analyze their effects on the software (SW) behavior. We describe how this analysis can be implemented based on a recently proposed HW-dependent software model called program netlist (PN). We show how program netlists can be extended to formally model the behavior of a program in the event of one or more hardware faults. Then, it is demonstrated how the results of the PN-based analysis can be exploited by a standard ATPG tool to determine hardware faults at the gate level that are "application-redundant". Our experimental results show the feasibility of the proposed approach.

A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a singleobjective and a multiobjective optimization of a low noise amplifier

This work intends to an integration of implementing an automated diagnostic systems for breast cancer detection us- ing Artificial Neural Network (ANN) in FPGA. In the world, breast cancer is the fifth most common cause of cancer death. So better classification system is needed for diagnosing breast cancer disease. In this work, the training and testing of the Multilayer Perceptron Neural Network (MLPNN) with Back Propagation Network (BPN) is done with the attributes of the record of the Wisconsin Breast Cancer Database (WBCD). The neural network lacks the flexibility during off line training. In order to over- come the flexibility, it is necessary to train and test the network on on-chip neural network using FPGA. The purpose is to deter- mine the cancer of patients either having benign or malignant through an FPGA based implementation of smart instrument. In order to implement the hardware, VERILOG coding is done for ANN and synthesized by Xilinx family XC5VLX50TFFT1136 FPGA Virtex 5 board using XILINX ISE tool to get the netlist of ANN. Finally the netlist is mapped to FPGA and the hardware functionality is verified. The correct classification rate of proposed system is 90.83%.

Summary In this paper, an efficient and highly accurate algorithm for yield-aware design of pipeline analog to digital converters (ADCs) based on a four-step approach is presented. First, a general netlist is generated for the data converter building blocks. Then, using an evolutionary method, its best performance sizing is estimated. Finally, the yield gets enhanced to reach a desired value. With the same accuracy, the presented algorithm can achieve yield optimization by approximately five times less computational cost compared with a state-of-the-art MC-based method. The framework is applied to demonstrate a reliable converter with optimum performance, power consumption, speed and area overhead during a single running process. A prototype 10-bit resolution, 10-MS/s pipeline analog to digital converter has been simulated in a 0.18-µm 1.8-V CMOS process. Presented results, applying the proposed method, show important advantages in terms of accuracy and efficiency. Copyright © 2016 John Wiley & Sons, Ltd.

Verilog is a hardware description language (HDL) that supports the specification of hardware circuitry and control logic for production, simulation and testing. The subset of the specification used for production is called synthesizable. Verilog-to-Routing (VTR) is a Computer-Aided Design (CAD) flow. It transforms synthesizable Verilog into a placed and routed configuration for a Field Programmable Gate Array (FPGA) architecture specified in XML. The front end of the VTR CAD flow is Odin II. Odin II parses Verilog files and uses them to create a netlist consisting of inputs, outputs, nodes, and connections. Odin II is an open-source research project, and full Verilog language coverage is a work in progress. This work extends Odin II's Verilog support to files containing the arithmetic right shift operator (>>>) and both the + : and - : part-select operators. It also adds support for simple for loops, while loops and loop-based module generation. Dynamic looping constructs are not synthesizable, so all looping constructs are processed before the netlist is generated. This paper will present the missing language features that were implemented, the scope of their implementation, the architecture of the solution, testing and finally the efficiency of the contributions.

Logic obfuscation emerged as an efficient solution to strengthen the security of integrated circuits (ICs) from multiple threats including reverse engineering and intellectual property (IP) theft. Emergence of Boolean Satisfiability (SAT) attacks and its variants have shown to circumvent the security mechanisms such as obfuscation and a plethora of its variants. Considering the size of ICs and the amount of time it takes to validate a defense i.e., obfuscation against SAT attack could range from few ms to days. In contrast, our current work focuses on devising an iterative, dynamic and intelligent SAT-hard clause generator for a given SAT-prone problem. The proposed Machine Learning (ML)-based SAT to unSAT clause translator is a SAT-hard clause generator that utilizes a bipartite propagation based neural network model. The utilized model comprises multiple layers of artificial neural networks to extract the dependencies of literals and variables, followed by long short term memory (LSTM) networks to validate the SAT hardness. The proposed ML-based SAT to unSAT clause translator is trained with conjunctive normal form (CNF) of the IC netlist that are both SAT solvable and SAT-hard. Further, the model is also trained to convert a CNF from satisfiable (SAT) to unsatisfiable (unSAT) form with minor perturbation (which translates to minor overheads) so that the SAT-attack cannot decrypt the keys. To the best of our knowledge, no previous work has been reported on neural network based SAT-hard clause or CNF translator for circuit obfuscation. We evaluate our proposed models's empirical performance against MiniSAT with 300 CNFs.

We present two novel sound and complete netlist transformations, which substantially improve verification scalability while enabling very efficient trace reconstruction. First, we present a 2QBF variant of input reparameterization, capable of eliminating inputs without introducing new logic and without complete range computation. While weaker in reduction potential, it yields up to 4 orders of magnitude speedup to trace reconstruction when used as a fast-and-lossy preprocess to traditional reparameterization. Second, we present a novel scalable approach to leverage sequential unateness to merge selective inputs, in cases greatly reducing netlist size and verification complexity. Extensive benchmarking demonstrates the utility of these techniques. Connectivity verification particularly benefits from these reductions, up to 99.8%.

The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate’s Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5% and 4.2% on average, respectively.

As feature size shrinks, routing constraints become a more significant limiting factor to the manufacturability of VLSI designs. Routing congestion significantly impacts quality metrics such as area and timing performance, but congestion is not known accurately until late in the design cycle, after placement and routing. This can lead to unpleasant surprises during the design process. Accordingly, early prediction of routing requirements would enable design engineers to iterate faster, with more confidence that their designs were routable and high quality. Additionally, routability estimates can inform placement itself, preemptively eliminating routing problems. In this work, we present a graph-based deep learning method for quickly predicting logic-induced routing congestion hotspots from a gate-level netlist before placement. This model can provide early feedback to designers and EDA tools, indicating logic that may be difficult to route. Compared to using previous congestion prediction metrics to predict congestion hotspots without placement information, our solution provides a 29% increase in the Kendall ranking correlation score. Because our focus is on predicting congestion due to local logic structure, which manifests itself on lower metal layers, we also report accuracy for predicting lower metal layer congestion. When predicting congestion for the lower metal layers, the benefit of our solution over previous metrics increases to 75%. Additionally, our approach is fast. On a circuit with 1.3 million cells, our approach takes 19 seconds to predict congestion, compared with 10–60 minutes for other methods.

The small number of logic functions in a traditional cell library limits the optimization of digital design regarding transistors, wires, and vias count. It affects traditional quality metrics, like area and total wire length. Our new library free approach enables such optimization by using tools for automatic layout synthesis of any transistor network. Using the traditional cell-based design flow to generate the initial netlist, we postprocess it considering to replace groups of cells by a single new cell of equivalent logic, which is not available in the cell library. Tests were performed over a standard benchmark, using a predictive 45nm cell library. Our approach reduces on average the number of transistors of a circuit by 21% when compared to a traditional solution. When to other logic minimization tools, it reduces transistor count by 2%, and by consequence, we obtain an average reduction of 9% on the number of wire segments, 5% in total wire length and 6% fewer pins. It also impacts the traditional performance metrics, demanding in 5% less area.

FNSim, a device-circuit-algorithm codesigned simulator is developed to evaluate and optimize the performance of flash based neural network. The accuracy, layout area, energy consumption and delay of different flash based neural networks can be evaluated by inputting the dataset, network topology, circuit netlist and device model parameters to the simulator. A convolutional neural network of Lenet-5 is designed to classify MNIST digits as a case study to show how to optimize the performance of flash based neural network with the developed simulator.

We present extensions to commercially available EDA tools to support Wafer-to-Wafer (W2W), Face-to-Face (F2F), hybrid bonding 3D integration with ~1μm pitch Cupad structures. Proposed flow is based on Innovus™ Place & Route (P&R) tool from Cadence Design Systems and allows functional 3D system partitioning with user specified partitioning information and automated netlist split. Due to fine 3D pitch, the partitioning can occur at lower levels of system hierarchy, resulting in significant number of 3D pins and with die-crossing critical paths. Proposed flow has been validated using memory-on-logic split of a single OpenSPARC-T2 core. L1 memory macros have been extracted from the post-synthesized gate-level netlist using a dedicated automated netlist partitioner. Per die netlists and top-level system have been fed into the P&R flow, memory die being implemented first. 3D structures have been assigned to 3D nets automatically, allowing their optimal placement with respect to the memory macros pins. 3D pin positions of the memory die have been propagated as a constraint for the implementation of the logic die, allowing optimized standard cell placement with respect to the 3D pins. Finally, we have enabled a cross-die timing analysis to assess the improvements of 3D in comparison to 2D. Our results show up to 40% of the total wirelength savings and 25 % on the maximum one, resulting in a 19% timing improvement on critical path.

Since underlying hardware components form the basis of trust in virtually any computing system, security failures in hardware pose a devastating threat to our daily lives. Hardware reverse engineering is commonly employed by security engineers in order to identify security vulnerabilities, to detect IP violations, or to conduct very-large-scale integration (VLSI) failure analysis. Even though industry and the scientific community demand experts with expertise in hardware reverse engineering, there is a lack of educational offerings, and existing training is almost entirely unstructured and on the job. To the best of our knowledge, we have developed the first course to systematically teach students hardware reverse engineering based on insights from the fields of educational research, cognitive science, and hardware security. The contribution of our work is threefold: (1) we propose underlying educational guidelines for practice-oriented courses which teach hardware reverse engineering; (2) we develop such a lab course with a special focus on gate-level netlist reverse engineering and provide the required tools to support it; (3) we conduct an educational evaluation of our pilot course. Based on our results, we provide valuable insights on the structure and content necessary to design and teach future courses on hardware reverse engineering.

Over the past 10 years, various Hardware Trojan (HT) detection techniques have been proposed by the research community. However, the development of HT benchmark suites for testing and evaluating HT detection techniques lags behind. The number of HT-infected circuits available in current public HT benchmarks is somewhat limited and the circuits lack diversity in structure. Therefore, this paper proposes a new method to generate HTs using a highly configurable generation platform based on transition probability. The generation platform is highly configurable in terms of the HT trigger condition, trigger type, payload type and in the number and variety of HT-infected circuits that can be generated. In this research the transition probability of netlists is employed to identify rarely activated internal nodes to target for HT insertion rather than functional simulation as utilised in previous research. The authors believe transition probability provides a more realistic reflection of the netlist activity for use in determining the appropriate position for HT insertion. Finally, the generated HT-infected circuits are tested by a machine learning (ML)-based HT detection technique, which is known as Controllability and Observability for HT Detection (COTD). The resulting false positive and false negative rates illustrate the feasibility of the benchmark suite.

This chapter presents cyclic logic locking and one-way function-based logic locking. The underlying idea of both schemes is to embed structures in a netlist that are hard to resolve for a SAT solver. Cyclic logic locking introduces cycles into a netlist with the expectation that it will render the SAT attack effort exponential in the number of cycles introduced. However, cyclic logic locking is vulnerable to the CycSAT attack, which can encode the presence of cycles in the CNF representation. One-way function-based logic locking integrates one-way functions into the locked netlist to render the SAT attack computationally infeasible.

This chapter presents point function-based logic locking techniques, namely SARLock, Anti-SAT, and AND-tree detection that thwart the SAT attack by controlling the distinguishing ability of the DIPs. All these techniques integrate with the original netlist a point function that sets a limit on the number of incorrect key values that a DIP can eliminate. While these techniques cost-effectively thwart the SAT attack, their main limitation is the susceptibility to removal attacks. Moreover, these techniques fail to achieve a high output error rate.

Apart from the previously mentioned attacks that exploit the algorithmic weaknesses of logic locking techniques, logic locking is also vulnerable to the emerging class of side-channel attacks, which are the focus of this chapter. The chapter introduces four attacks on logic locking that exploit various side-channels to extract secret key. The differential power analysis attack utilizes the power consumption of a chip to determine the secret logic locking key. The test-data mining attack and the hill climbing attack determine the secret key from the test data. The de-synthesis attack extracts the key by leveraging the traces left in a netlist during logic synthesis.

Floating, i.e. not locally grounded, printed circuit boards (PCBs) at the end of a long harness and above a large ground plane are common in automotive applications. A problem in modeling such setups is the missing ground reference at the PCB side. In this work, two equivalent circuit models are extracted from PCB design data, one based on a broadband SPICE (BBSPICE) netlist generated from S-parameter simulation and the other obtained by partial element equivalent circuit (PEEC) method. They are compared against measurements results of a demonstrator PCB in above described setup. Investigations include the verification of both modeling approaches with respect to low frequency behavior, broadbandness, sensitivity to PCB circuitry modifications and grounding scheme, as well as model generation effort and simulation times.

In this paper, we present an automated strategy for extracting behavioral small-signal macromodels of biased nonlinear circuit blocks. We discuss in detail the case study of a Low DropOut (LDO) voltage regulator, which is an essential part of the power distribution network in electronic systems. We derive a compact yet accurate surrogate model of the LDO, which enables fast transient power integrity simulations, including all parasitics due to the specific layout of the LDO realization. The model is parameterized through its DC input voltage and its output current and is thus available as a SPICE netlist. Numerical experiments show that a speedup up to 700X is achieved when replacing the extracted post-layout netlist with the surrogate model, with practically no loss in accuracy.

The routing stage is one of the most time-consuming steps in System on Chip (SoC) physical design. For large designs, it can take days of effort to find a complete routing solution, and the result directly affects the circuit performance. In this paper, we present a routing strategy that decomposes global routing into three stages, with different objectives associated with each stage. This is in contrast to conventional approaches, which usually use a single global optimization objective for driving the entire process. Furthermore, we propose to use generative adversarial networks (GAN) to predict the congestion heatmap. This deep learning method has been used to successfully improve image recognition results. We adapt its use to global routing by converting data between the router and the image-based model. This model needs only placement and netlist information as input to make the forecast. Our GAN-based congestion estimator produces congestion heatmaps that show good fidelity with actual heatmaps produced by state-of-the-art global routers. Using this heatmap along with our modified routing flow, we achieve comparable global routing quality in terms of the total overflow and wirelength, but the runtime speedup on hard-to-route designs is significant.

Logic obfuscation techniques are used to deter intellectual property piracy, reverse engineering, and counterfeiting threats in the design and manufacturing of integrated circuits. However, obfuscation can be reverse-engineered in a variety of ways, there has been little effort in measuring the effectiveness of different obfuscation techniques using uniform security and overhead metrics, and only limited investigations on the effect of combining multiple methods on the same die. This paper presents MIRAGE, a system-level end-to-end framework for integrated circuit obfuscation. MIRAGE includes a front-end design space exploration tool that selects an appropriate combination of obfuscation techniques for a given circuit, a netlist manipulation application programming interface to apply the obfuscation, and a back-end analysis tool that evaluates the obfuscation strength in terms of attack resiliency time as well as area, power, and timing overhead. The effectiveness of the proposed framework is illustrated on benchmarks from ISCAS and cores from an open-source system-on-chip test platform, thus extending the analysis to practical circuits with more than 100k gates. MIRAGE utilizes 1,242 circuit configurations to evaluate 6 obfuscation methods in terms of the attack resiliency time and the obfuscation overheads such as area, power, and timing.

In this paper we investigate using low-level loop analysis to identify common loop patterns in the netlist generated by the synthesis flow and use loop optimization techniques to increase Fmax of applications implemented on Xilinx FPGAs. Ordinarily, feed-forward paths in the netlist can be easily pipelined. The focus of this study is only sequential loops (with feedback cycles) that are more challenging to optimize. We show using low-level loop analysis, we can improve Fmax on average by 57% and achieve an average Fmax of 714MHz across seven industrial designs. Using aggressive loop combining, we also show that we can save 18% area on average while still improving the Fmax by 15% to 41% on four of the seven designs.

Neural networks are achieving state-of-the-art performance in many applications, from speech recognition to computer vision. A neuron in a multi-layer network needs to multiply each input by its weight, sum the results and perform an activation function. This paper presents a variation of the implementation of an amplifier-based MOS analog neuron capable of performing these tasks and also the optimization of the synaptic weights using in-loop circuit simulations. MOS transistors operating in the triode region are used as variable resistors to convert the input and weight voltage to a proportional input current. To test the analog neuron in full networks, an automatic generator is developed to produce a netlist based on the number of neurons on each layer, inputs and weights. Simulation results using a CMOS 180 nm technology demonstrate the neuron proper transfer function and its functionality while trained in test datasets.

This paper presents a software platform based on open source tools to simulate and fit parameter values of sensor device models based on MOSFET like the ISFET. In electronic simulation, electrical and mathematical models allow to describe the behavior of electronic devices. Although manufacturers provide device models, in some cases, this information is not enough to simulate their characteristics. In order to improve the parameter values of mathematical model, the fitting procedure compares the measured and simulated data. This platform allows testing different models such as ISFET or MOSFET using freely available SPICE simulator engines. It constructs the netlist based on the classical ISFET behavioral macromodel considering the values entered by the user, then via a set of methods simulate this customized model for both characteristics curves i DS vs v GS and i DS vs v DS and compare them with experimental results obtained from a characterization process.

Existing logic obfuscation approaches aim to protect hardware design IPs from SAT attack by increasing query count and output corruptibility of a locked netlist. In this paper, we demonstrate the ineffectiveness of such techniques to obfuscate hardware accelerator platforms. Subsequently, we propose a Hardware/software co-design based Accelerator Obfuscation (HSCAO) scheme to provably safeguard the IP of such designs against SAT as well as removal/bypass type of attacks while still maintaining high output corruptability for applications. The attack resiliency of HSCAO scheme is manifested by using a sequence of keys to obfuscate instruction encoding for an application. Experimental evaluations utilizing an accelerator simulator demonstrate the effectiveness of our proposed countermeasure.

The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.

Crosstalk computing, involving engineered interference between nanoscale metal lines, offers a fresh perspective to scaling through co-existence with CMOS. Through capacitive manipulations and innovative circuit style, not only primitive gates can be implemented, but custom logic cells such as an Adder, Subtractor can be implemented with huge gains. Our simulations show over 5x density and 2x power benefits over CMOS custom designs at 16nm [1]. This paper introduces the Crosstalk circuit style and a key method for large-scale circuit synthesis utilizing existing EDA tool flow. We propose to manipulate the CMOS synthesis flow by adding two extra steps: conversion of the gate-level netlist to Crosstalk implementation friendly netlist through logic simplification and Crosstalk gate mapping, and the inclusion of custom cell libraries for automated placement and layout. Our logic simplification approach first converts Cadence generated structured netlist to Boolean expressions and then uses the majority synthesis tool to obtain majority functions, which is further used to simplify functions for Crosstalk friendly implementations. We compare our approach of logic simplification to that of CMOS and majority logic-based approaches. Crosstalk circuits share some similarities to majority synthesis that are typically applied to Quantum Cellular Automata technology. However, our investigation shows that by closely following Crosstalk's core circuit styles, most benefits can be achieved. In the best case, our approach shows 36% density improvements over majority synthesis for MCNC benchmark.

Approximate computing provides a paradigm shift to reduce the hardware cost or improve the speed of logic circuits by relaxing the quality of computation. This paper presents a novel approximate logic design methodology that integrates input data distribution to optimize the performance for specific applications. Furthermore, the proposed approach also provides sufficient scalability as only the circuit netlist and input data are needed in designing the approximate circuit. Our experimental results show that the data-driven designs generated by the proposed method achieve significantly better accuracy than the data-independent ones, while maintaining minimal hardware overheads. For example, in the design of an approximate finite impulse response (FIR) filter, our method reduces nearly 40% of the error metrics while still achieving a 29% area reduction, compared to the original exact circuit, which further validating the robustness of the proposed method beyond arithmetic elements.

In order to speed up analog design cycles, analog layout automation is a popular research in recent years. However, most previous works assume that the required design constraints are given by users manually. Designers still take a lot of time to fill-in the required design information. Template-based layout generation is another approach to consider the design constraints, but considerable development efforts are required for each new design and each new technology. In this paper, we propose a structure-based methodology for analog layout generation. This methodology starts from a structure analysis that divides the circuit netlist into several building blocks automatically. It can help to reduce the dependence on users' input and generate corresponding design constraints for the succeeding layout steps. With the help from structure analysis, the layouts of those analog structures are generated, placed, and routed automatically with proper constraints. As shown in the demo cases, the proposed flow is able to generate the required layout accurately without users' intervention and still keeps the post-layout performance within specifications.

Nowadays, the demand for a MEMS development/design kit (MDK) is even more in focus than ever before. In order to achieve a high quality and cost effectiveness in the development process for automotive and consumer applications, an advanced design flow for the MEMS (micro electro mechanical systems) element is urgently required. In this paper, such a development methodology and flow for parasitic extraction of active semiconductor devices is presented. The methodology considers geometrical extraction and links the electrically active pn-junctions to SPICE standard library models and subsequently extracts the netlist. An example for a typical pressure sensor is presented and discussed. Finally, the results of the parasitic extraction are compared with fabricated devices in terms of accuracy and capability.

Model abstraction of transistor-level circuits, while preserving an accurate behavior, is still an open problem. In this paper an approach is presented that automatically generates a hybrid automaton (HA) with linear states. The resulting HA is used for reachability analysis. Each of the locations of the HA is modeled with a system matrix described as a matrix zonotope or interval matrix. This leads to an acceptable over approximation, but guarantees that the system behavior is covered. The approach starts with a netlist at transistor level with full SPICE accuracy and ends at the system level description of the circuit. To illustrate our methodology, an example of a circuit containing complex poles and strong nonlinear limiting behavior is analyzed.

In this paper, a design methodology for carrying out all the steps involved in a typical analog design flow, using free or open source electronic design automation [EDA] tools is proposed. Implementation of a three stage CMOS operational amplifier is chosen for demonstration. gEDA-gschem tool is utilized for schematic capture and SPICE net list generation. Electric-VLSI is a state of the art EDA tool which is used for laying out the op-amp, design rule checking [DRC], verifying layout versus schematic [LVS] and generating parasitic extracted SPICE net list. The SPICE net list are simulated with the help of versatile, electronics and electric circuit simulator, Ngspice. The scripting language provided by Ngspice is used for performing corner analysis and Monte-Carlo simulations. Simulation results reveal that the designed operational amplifier meets the desired specifications. Corner and Monte-Carlo analysis show that the op-amp is robust against process variations and mismatch.

Logic encryption has been proposed as a potential solution to the hardware IP piracy problem. Naive logic encryption methods were shown to be susceptible to Boolean satisfiability (SAT) based attacks. In addition, the recently proposed Sequential SAT attack is able to decrypt many encrypted sequential logic circuits. This paper introduces a new logic encryption scheme that encrypts a sequential circuit on the occurrence of a chosen deep state. Two novel techniques to select a suitable deep state from the gate-level netlist of the design have been introduced. The attack resiliency of the proposed encryption technique against the sequential SAT attack is demonstrated using several standard benchmark circuits.

Arithmetic circuits like adders and multipliers are key workforces of many error resilient applications. Prior efforts on approximating these arithmetic circuits mainly focused on manual circuit level functional modifications. These manual approaches need high design time and effort. Due to this only a limited no. of approximate design points can be generated from the original circuit leading to a sparsely occupied pareto front. This work proposes an automated approximation methodology for arithmetic circuits. Proposed method approximates the gate level standard cell library and uses these approximate standard cells to modify the netlist of the original circuit. A heuristic design space exploration methodology is proposed to speed-up the design process. We integrate this methodology with traditional ASIC flow and validate our results using adders and multipliers of different bitwidths. We show that our methodology improves on existing state-of-the-art manual as well as automated design techniques by generating non-dominant pareto-fronts. An application case study (sobel edge detection) is shown using approximate arithmetic circuits generated by our methodology. In case of sobel edge detector, we show upto 50% energy improvements for hardly any quality degradation (PSNR ≥ 20dB).

The task of an engineering change order (ECO) is to update the current implementation of a design according to its revised specification with minimum modification. Prior studies show that the amount of design modification majorly depends on the selection of rectification points, i.e., the input pins of gates whose functionality should be rectified with some patch circuitry. In realistic ECOs, as the netlist of the current implementation has been heavily optimized to meet design objectives, it is usually structurally dissimilar to the netlist of a revised specification, which is synthesized only by lightweight optimization. This paper proposes an ECO solution for optimized designs, which is robust against structural dissimilarity caused by design optimization. It locates candidate rectification points in a sampling domain, which significantly improves the scalability of rectification search. To synthesize the circuitry of patches, a structurally independent rewiring formulation is proposed to reuse existing logic in the implementation. Based on the proposed method, a newly developed engine is evaluated on the engineering changes arising in the design of microprocessors. Its ability to derive patches of superior quality is demonstrated in comparison to industrial tools.

Applications of deep learning to electronic design automation (EDA) have recently begun to emerge, although they have mainly been limited to processing of regular structured data such as images. However, many EDA problems require processing irregular structures, and it can be non-trivial to manually extract important features in such cases. In this paper, a high performance graph convolutional network (GCN) model is proposed for the purpose of processing irregular graph representations of logic circuits. A GCN classifier is firstly trained to predict observation point candidates in a netlist. The GCN classifier is then used as part of an iterative process to propose observation point insertion based on the classification results. Experimental results show the proposed GCN model has superior accuracy to classical machine learning models on difficult-to-observation nodes prediction. Compared with commercial testability analysis tools, the proposed observation point insertion flow achieves similar fault coverage with an 11% reduction in observation points and a 6% reduction in test pattern count.

In recent years, formal methods based on Symbolic Computer Algebra (SCA) have shown very good results in verification of integer multipliers. The success is based on removing redundant terms (vanishing monomials) early which allows to avoid the explosion in the number of monomials during backward rewriting. However, the SCA approaches still suffer from two major problems: (1) high dependence on the detection of Half Adders (HAs) realized as AND-XOR gates in the multiplier netlist, and (2) extremely large search space for finding the source of the vanishing monomials. As a consequence, if the multiplier consists of dirty logic, i.e. for instance using non-standard libraries or logic optimization, the existing SCA methods are completely blind on the resulting polynomials, and their techniques for effective division fail. In this paper, we present RevSCA. RevSCA brings back light into backward rewriting by identifying the atomic blocks of the arithmetic circuits using dedicated reverse engineering techniques. Our approach takes advantage of these atomic blocks to detect all sources of vanishing monomials independent of the design architecture. Furthermore, it cuts the local vanishing removal time drastically due to limiting the search space to a small part of the design only. Experimental results confirm the efficiency of our approach in verification of a wide variety of integer multipliers with up to 1024 output bits.

This paper presents analog layout automation efforts under the ALIGN ("Analog Layout, Intelligently Generated from Netlists") project for fast layout generation using a modular approach based on a mix of algorithmic and machine learning-based tools. The road to rapid turnaround is based on an approach that detects structure and hierarchy in the input netlist and uses a grid based philosophy for layout. The paper provides a view of the current status of the project, challenges in developing open-source code with an academic/industry team, and nuts-and-bolts issues such as working with abstracted PDKs, navigating the "wall" between secured IP and open-source software, and securing access to example designs.

Click element is frequently used in asynchronous circuits. However, we have to use netlist to instantiate it and the output pulse width will change according to the placement and routing every time when we synthesis it. To address the problem, we design a standard cell library for Click element. However, it is difficult to characterize the Click element with commercial EDA tools for the indescribable function of its output pins in the feedback structure. In this paper, we propose a novel method to characterize Click element by cutting the feedback loops when building up the library and reconnecting the cut points when describing it with Verilog. As a result, the function of output pins could be described during characterization and the function of Click is maintained. The method has been verified by the simulation after placement and routing. The comparison between the Click instantiated by netlist and the full-custom standard cell of Click shows that the latter has 20.8% less area and 63.7% less power consumption than those of the former.

Asynchronous circuits have the potential advantages in low power consumption, high performance speed and no clock distribution problems. However, it is difficult to design asynchronous circuits because of the lack of EDA tools. In this paper, we proposed a desynchronization method to transform synchronous circuits to Click-based asynchronous circuits using commercial EDA tools, aiming to reduce the design complexity of asynchronous circuits and take advantages of asynchronous circuits. According to the different circuits structures between bundled-data asynchronous circuits and synchronous pipeline circuits, we transform the synchronous Verilog codes into asynchronous ones which can be synthesized by Synopsys Design Compiler (DC) by replacing the global clock in synchronous circuits with the local pulse signals generated by Click elements. With the netlist produced by DC, we use Cadence Encounter Digital Implementation system to implement the physical design. Finally, an asynchronous processing element in a Convolution Neural Network accelerator for Lenet-5 is implemented as a case study to prove the feasibility and efficiency of the proposed methodology.

Adiabatic Quantum-Flux-Parametron (AQFP) logic is an adiabatic superconductor logic that has been proposed as alternative to CMOS logic with extremely high energy efficiency. In AQFP technology, majority-based gates have the same area as two-input AND/OR gates while offering more complex logic. Therefore, majority-based logic (MAJ) is more preferred than and-or-inverter-based logic (AOI) to implement logic functions in AQFP for higher energy efficiency. In this paper, we propose a majority gates synthesis framework for AQFP circuits that is capable of converting any AOI netlist to its corresponding MAJ netlist by mapping all feasible three-input sub- netlists to corresponding MAJ based implementations. In addition, the proposed tool can insert the optimal amount of buffers and splitters for equivalent delay as required in the AQFP technology. Experimental results suggest that the proposed method can reduce delay and area by up to 60.00% and 60.98%, respectively.

In the past years, new hardware reverse engineering methods for sequential gate-level netlists have been developed to detect Hardware Trojans and counteract Design Piracy. A critical part of sequential gate-level netlist reverse engineering is the identification of state registers. A promising method to solve this problem, RELIC, proposed by T. Meade et al., is based on input structure similarities of registers to differentiate between state and non-state registers. We propose an improvement to this method, fastRELIC: it outperforms RELIC in terms of speed and computational complexity. A complexity analysis shows the upper bound of $\mathcal{O}(R^2)$ (R: # registers) for both methods, but a linear lower bound Ω(R) for fastRELIC. Empirical results with fastRELIC provide a speedup of up to 100x. This allowed us to analyze real-life designs with more than 4,000 registers and 50,000 gates.

Split Manufacturing (SM) was introduced as an effective countermeasure to reverse engineering of integrated circuits and as a potential deterrent to Trojan insertion and overproduction. In SM, some wires, assigned to the back-end-of-line (BEOL) layers and fabricated at a secure facility, are hidden from the attacker. However, proximity information based attacks use physical design hints such as wire-length, combinational cycles and routing directions obtained from the FEOL (front-end-of-line) netlist to recover some or all of the BEOL signals. In addition, a recently proposed satisfiability (SAT) based attack models the BEOL signal recovery problem as a problem of configuring a key-controlled interconnect network and solves for the key values using a SAT solver. While this method can recover 100% of the BEOL signals, it takes impractically long time for large circuits. In this paper, we propose an effective method to exploit proximity information extracted from the FEOL circuit to reduce the size of the interconnection network which models the missing BEOL layers which in turn significantly reduces the size of the resulting SAT problem. This leads to efficient recovery of 100% of the ‘hidden’ BEOL signals even for large circuits. Experimental results using circuits from ISCAS85, ISCAS89 and ITC99 benchmark suites show that the proposed method is up to 80x faster than the SAT-only attack (without proximity information) while maintaining the 100% attack correctness for all combinational and sequential benchmarks.

Logic locking, and Integrated Circuit (IC) Camouflaging, are techniques that try to hide the design of an IC from a malicious foundry or end-user by introducing ambiguity into the netlist of the circuit. While over the past decade an array of such techniques have been proposed, their security has been constantly challenged by algorithmic attacks. This may in part be due to a lack of formally defined notions of security in the first place, and hence a lack of security guarantees based on long-standing hardness assumptions.In this paper we take a formal approach. We define the problem of circuit locking (cℒ) as transforming an original circuit to a locked one which is “unintelligable” without a secret key (this can model camouflaging and split-manufacturing in addition to logic locking). We define several notions of security for cℒ under different adversary models. Using long standing results from computational learning theory we show the impossibility of exponentially approximation-resilient locking in the presence of an oracle for large classes of Boolean circuits. We then show how exact-recovery-resiliency and a more relaxed notion of security that we coin “best-possible” approximation-resiliency can be provably guaranteed with polynomial overhead. Our theoretical analysis directly results in stronger attacks and defenses which we demonstrate through experimental results on benchmark circuits.

A method to increase the resiliency of in-cone logic locking against the SAT attack is described in this paper. Current logic locking techniques provide protection through the addition of circuitry outside of the original logic cone. While the additional circuitry provides provable security against the SAT attack, other attacks, such as the removal attack, limit the efficacy of such techniques. Traditional in-cone logic locking is not prone to removal attacks, but is less secure against the SAT attack. The focus of this paper is, therefore, the analysis of in-cone logic locking to increase the security against the SAT attack, which provides a comparison between in-cone techniques and newly developed methodologies. A novel algorithm is developed that utilizes maximum fanout free cones (MFFC). The application of the algorithm limits the fanout of incorrect key information. The MFFC based algorithm resulted in an average increase of 61.8% in the minimum number of iterations required to complete the SAT attack across 1,000 different variable orderings of the circuit netlist while restricted to a 5% overhead in area.

This research presents the extension and application of a voltage and frequency scaling framework called Elongate to a high-performance and reconfigurable binarized neural network. The neural network is created in the FPGA reconfigurable fabric and coupled to a multiprocessor host that controls the operational point to obtain energy proportionality. Elongate instruments a design netlist by inserting timing detectors to enable the exploitation of the operating margins of a device reliably. The elongated neural network is re-targeted to devices with different nominal operating voltages and fabricated with 28 nm (i.e., Zynq) and 16nm (i.e., Zynq Ultrascale) feature sizes showing the portability of the framework to advanced process nodes. New hardware and software components are created to support the 16nm fabric microarchitecture and a comparison in terms of power, energy and performance with the older 28 nm process is performed. The results show that Elongate can obtain new performance and energy points that are up to 86 percent better than nominal at the same level of classification accuracy. Trade-offs between energy and performance are also possible with a large dynamic range of valid working points available. The results also indicate that the built-in neural network robustness allows operation beyond the first point of error while maintaining the classification accuracy largely unaffected.