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LUT based realization of fixed-point multipliers targeting state-of-art FPGAs
- Source :
- Design Automation for Embedded Systems. 21:89-115
- Publication Year :
- 2017
- Publisher :
- Springer Science and Business Media LLC, 2017.
-
Abstract
- Look-up tables (LUT) form the basic logic elements in a large class of modern day field programmable gate arrays (FPGA). With FPGAs increasingly being used in low and medium volume productions, many vendors have improved the capacity and versatility of these devices. The enormous logic capacity inherent in state-of-art FPGAs has made it essential to develop automated computer aided design (CAD) support for logic synthesis using these platforms. Since design entry is the only manual phase in the FPGA CAD-flow, it essentially rules out any scope for technology-dependent optimization, which focusses on achieving optimal mapping of logical functionalities onto the target platforms. Evidently, majority of the work related to the implementation of different arithmetic circuits on FPGAs focuses only on the technology-independent optimizations, where the design process consists of modifying the architecture at the top level without giving any consideration to the mapping of the architecture onto the FPGA device. In this paper, we consider the technology-dependent optimization of the fixed-point bit-parallel multipliers on LUT based FPGAs. Our approach re-structures the initial Boolean network and transforms it into an optimized LUT netlist prior to the design entry phase. The design entry of the optimized netlist is then carried out using instantiation based coding styles. This ensures that the optimizations done prior to the design entry phase remain preserved throughout the synthesis process. We particularly focus on 6-input LUTs that are inherent basic logic elements in state-of-art FPGAs. Theoretical analysis and detailed experimentation using state-of-art Xilinx 7th generation FPGAs reveal a substantial speed-up in performance.
- Subjects :
- Computer science
business.industry
020208 electrical & electronic engineering
02 engineering and technology
Work related
Reconfigurable computing
020202 computer hardware & architecture
Logic synthesis
Hardware and Architecture
Embedded system
Lookup table
0202 electrical engineering, electronic engineering, information engineering
Netlist
Hardware_ARITHMETICANDLOGICSTRUCTURES
Engineering design process
Field-programmable gate array
business
Fixed-point arithmetic
Software
Hardware_LOGICDESIGN
Subjects
Details
- ISSN :
- 15728080 and 09295585
- Volume :
- 21
- Database :
- OpenAIRE
- Journal :
- Design Automation for Embedded Systems
- Accession number :
- edsair.doi...........75dd2a37d272036f160e79e0052b127c