A method to transform synchronous pipeline circuits to bundled-data asynchronous circuits using commercial EDA tools

Asynchronous circuits have the potential advantages in low power consumption, high performance speed and no clock distribution problems. However, it is difficult to design asynchronous circuits because of the lack of EDA tools. In this paper, we proposed a desynchronization method to transform synchronous circuits to Click-based asynchronous circuits using commercial EDA tools, aiming to reduce the design complexity of asynchronous circuits and take advantages of asynchronous circuits. According to the different circuits structures between bundled-data asynchronous circuits and synchronous pipeline circuits, we transform the synchronous Verilog codes into asynchronous ones which can be synthesized by Synopsys Design Compiler (DC) by replacing the global clock in synchronous circuits with the local pulse signals generated by Click elements. With the netlist produced by DC, we use Cadence Encounter Digital Implementation system to implement the physical design. Finally, an asynchronous processing element in a Convolution Neural Network accelerator for Lenet-5 is implemented as a case study to prove the feasibility and efficiency of the proposed methodology.