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3D sequential integration is a promising candidate for the scaling sustainability for technological nodes beyond 14 nm. The main challenge is the development of a low temperature process for the top transistor level that enables to avoid the degradation of the bottom transistor level. The most critical process step for the top transistor level fabrication is the dopant activation that is usually performed at temperature higher than 1000 °C. In the frame of this Ph.D. work, different solutions for the dopant activation optimization at low temperature (below 600 °C) are proposed and integrated in FDSOI and TriGate devices. The technique chosen for the dopant activation at low temperature is the solid phase epitaxial regrowth. First, doping conditions have been optimized in terms of activation level and process time for low temperatures (down to 450 °C) anneals. The obtained conditions have been implemented in FDSOI and TriGate devices leading to degraded electrical results compared to the high temperature process of reference (above 1000 °C). By means of TCAD simulation and electrical measurements comparison, the critical region of the transistor in terms of activation appears to be below the offset spacer. The extension first integration scheme is then shown to be the best candidate to obtain high performance low temperature devices. Indeed, by performing the doping implantation before the raised source and drain epitaxial growth, the absence of diffusion at low temperature can be compensated. This conclusion can be extrapolated for TriGate and FinFET on insulator devices. Extension first integration scheme has been demonstrated for the first time on N and PFETs in 14 nm FDSOI technology showing promising results in terms of performance. This demonstration evidences that the two challenges of this integration i.e. the partial amorphization of very thin films and the epitaxy regrowth on implanted access are feasible. Finally, heated implantation has been investigated as a solution to dope thin access regions without full amorphization, which is particularly critical for FDSOI and FinFET devices. The as-implanted activation levels are shown to be too low to obtain high performance devices and the heated implantation appears a promising candidate for low temperature devices if used in combination with an alternative activation mechanism., L’intégration 3D séquentielle représente une alternative potentielle à la réduction des dimensions afin de gagner encore en densité d’une génération à la suivante. Le principal défi concerne la fabrication du transistor de l’étage supérieur avec un faible budget thermique; ceci afin d’éviter la dégradation du niveau inférieur. L’étape de fabrication la plus critique pour la réalisation du niveau supérieur est l’activation des dopants. Celle-ci est généralement effectuée par recuit à une température supérieure à 1000 °C. Dans ce contexte, cette thèse propose des solutions pour activer les dopants à des températures inférieures à 600 °C par la technique dite de recristallisation en phase solide. Les conditions de dopage ont été optimisées pour améliorer le niveau d’activation et le temps de recuit tout en réduisant la température d’activation jusqu’à 450°C. Les avancées obtenues ont été implémentées sur des dispositifs avancés FDSOI et TriGate générant des dispositifs avec des performances inférieures aux références fabriquées à hautes températures (supérieures à 1000 °C). En utilisant des simulations TCAD et en les comparant aux mesures électriques, nous avons montré que la région la plus critique en termes d’activation se trouve sous les espaceurs de la grille. Nous montrons alors qu’une intégration dite « extension first » est le meilleur compromis pour obtenir de bonnes performances sur des dispositifs fabriqués à faible température. En effet, l’implantation des dopants avant l’épitaxie qui vise à surélever les sources et drains compense l’absence de diffusion à basse température. Ces résultats ont par la suite été étendus pour des dispositifs TriGate et FinFETs sur isolants. Pour la première fois, l’intégration « extension first » a été démontrée pour des N et PFETs d’une technologie 14 nm FDSOI avec des résultats prometteurs en termes de performances. Les résultats obtenus montrent notamment qu’il est possible d’amorphiser partiellement un film très mince avant d’effectuer une recroissance épitaxiale sur une couche dopée. Finalement, une implantation ionique à relativement haute température (jusqu’à 500 °C) a été étudiée afin de doper les accès sans amorphiser totalement le film mince, ce qui est critique dans le cas des dispositifs FDSOI et FinFET. Nous montrons que les niveaux d’activation après implantation sont trop faibles pour obtenir des bonnes performances et que l’implantation ionique « chaude » est prometteuse à condition d’être utilisée avec un autre mécanisme d’activation comme le recuit laser.

As device dimension is scaling down, the source/drain parasitic resistance Rseries makes up a growing percentage of the on-resistance (Ron = Vdd/Ion), thus it presents a larger influence on device performance [1]. However, it is very difficult to reduce Rseries in sub-100 nm MOSFETs.

CMOS compatible self-aligned access regions for indium gallium arsenide (In 0.53 Ga 0.47 As) implant-free n-type metal oxide semiconductor “eld effect transistors (MOSFETs) are investigated. In situ doped n+source/drain regions are selectively grown by metal-organic vapor phase epitaxy and self-alignedNickel InGaAs alloyed metal contacts are obtained using a self-aligned silicide-like process, where differ-ent process conditions are studied. Soft pre-epitaxy cleaning is followed by X-ray photoelectron spectros-copy, while the Ni InGaAs/III V interface is characterized by back-side SIMS pro“ling. Relevant contactand sheet resistances are measured and integration issues are highlighted. Gate-“rst implant-free self-aligned n-MOSFETs are produced to quantify the impact of Ni InGaAs contacts on the deviceperformance. 2012 Elsevier Ltd. All rights reserved. 1. IntroductionDue to their higher injection velocity, III V compound semicon-ductors and in particular indium gallium arsenide (InGaAs) arebeing studied as possible candidates to replace Si as the channelmaterial in metal oxide semiconductor “eld-effect-transistors(MOSFETs) for digital logic applications. Several challenges haveto be tackled to bene“t from the III Vs superior transport proper-ties and achieve a high drain current performance. Achieving lowresistance self-aligned source/drain access regions suitable forhigh-performance logic at 10 nm node and beyond is one of themost critical challenges. These contacts have to be highly compat-ible with standard CMOS ”ows, scalable to the small-pitch require-ments and thermally stable to stand the back-end process.Several approaches have been tried such as ion implantationwhich has shown its limits due to the too high thermal budget re-quired to achieve a decent S/D dopant activation[1]. Selective epi-taxy of in situ doped InGaAs S/D regions has been done bymolecular beam epitaxy (MBE)[2] and metal-organic vapor phaseepitaxy (MOVPE) [3], achieving a high carrier density in a self-aligned gate-“rst scheme. These two approaches require a III Vcleaning recipe which includes a wet etch down to an etch-stoplayer before regrowth. Etching the channel material prior to S/Dformation is not an option in the case of fully-depleted types ofarchitectures like extremely-thin compound semiconductor oninsulator (ETCSOI).Low contact resistance and self-aligned molybdenum (Mo)metal contacts have been demonstrated using a height-selectiveetching process[4]. However, this process might be dif“cult tomanufacture over large wafer size on scaled devices. A salicide-like(self-aligned silicide) process on III V has been developed using aNickel InGaAs (Ni InGaAs) alloy integrated in a metallic S/D n-MOSFET[5,6] which suffers from a high off-state drain currentdue to the absence of a channel-to-S/D p n junction.In this work we report on a CMOS compatible process ”ow toachieve self-aligned implant-free access regions for In

Perchlorinated polysilanes were synthesized by polymerization of tetrachlorosilane under cold plasma conditions with hydrogen as a reducing agent. Subsequent selective cleavage of the resulting polymer yielded oligochlorosilanes SinCl2n+2 (n = 2, 3) from which the octachlorotrisilane (n = 3, Cl8Si3, OCTS) was used as a novel precursor for the synthesis of single-crystalline Si nanowires (NW) by the well-established vapor–liquid–solid (VLS) mechanism. By adding doping agents, specifically BBr3 and PCl3, we achieved highly p- and n-type doped Si-NWs by means of atmospheric-pressure chemical vapor deposition (APCVD). These as grown NWs were investigated by means of scanning electron microscopy (SEM) and transmission electron microscopy (TEM), as well as electrical measurements of the NWs integrated in four-terminal and back-gated MOSFET modules. The intrinsic NWs appeared to be highly crystalline, with a preferred growth direction of [111] and a specific resistivity of ρ = 6 kΩ·cm. The doped NWs appeared to be [112] oriented with a specific resistivity of ρ = 198 mΩ·cm for p-type Si-NWs and ρ = 2.7 mΩ·cm for n-doped Si-NWs, revealing excellent dopant activation.

高濃度As^+イオン注入したGe(100)でのAsの活性化に対する知見を得るために、加速電圧10keV,ドーズ量1x10^cm^でイオン注入後、熱処理に伴う化学構造変化やAs活性化状況を系統的に調べた。イオン注入により、p型Ge(100)基板の表層深さ約19nmが非晶質化すると共に、アクセプター型欠陥準位が生成されることが明らかになった。熱処理による基板側から再結晶化と伴って、Asの活性化が進行し、一部のAsは非晶質/結晶回復層の界面近傍に偏析することが分かった。硬X線光電子分光により、Ge中のAsの化学結合状態を評価した結果、500℃の熱処理後では、活性化した成分に相当するAs^と不活性な成分に相当するAs^の結合状態が存在し、As^の成分比から算出した活性化率は〜4%で、ホール効果測定結果とほぼ一致することが分かった。この結果は、Siの場合と同様に、クラスター形成による活性化率の低下を示している。, As^+ ions were implanted into p-type Ge(100) at a dose of 1x10^ cm^ and acceleration voltage of 10 keV, and an impact of activation annealing temperature on the chemical structure has been investigated systematically. After ion implantation, a formation of 19 nm-thick amorphous Ge including accepter-like defects was observed. During activation annealing in N_2 ambience, re-crystallization of amorphous Ge layer and activation of implanted As^+ ions were promoted from the substrate side. Hard x-ray photoemission spectroscopy (HAXPES) analyses of 500℃ annealed sample show the presence of two chemical states of As ions originating from activated As (As^) and inactivated As (As^). From the spectral deconvolution, activation ratio of implanted As ions was crudely estimated to be 〜4%, which was almost consistent with the electrical properties.

Microwave annealing of arsenic-doped silicon was employed to achieve nearly complete dopant activation and repair of damage caused by ion implantation. Analysis of Rutherford backscattering spectra suggested that volumetric heating from microwaves can repair ion-implantation damage. Secondary ion mass spectroscopy depth profiling revealed that even with high damage due to implanted arsenic, microwave annealing achieves repair of lattice damage, and electrical activation of dopants without allowing any significant dopant diffusion into the silicon substrate. Surface temperatures greater than 700 °C were achieved within ~ 100 s with assisted microwave heating, marking this as a quick annealing technique when compared to un-assisted annealing. This temperature was sufficient for solid phase epitaxial growth in Si. The temperature profile recorded by a thermocouple-calibarated IR pyrometer was explained based upon the type of losses the sample undergoes while heating. The mechanism for susceptor-assisted microwave heating was dominated by dipole polarization losses in the initial stages of anneal and by Ohmic conduction losses at higher temperatures. Cross-section transmission electron microscopy, along with ion channeling spectra indicated that the silicon lattice regained nearly all of its crystallinity during the microwave anneal. Hall measurement and sheet resistance characterization were used to assess the extent of dopant activation.

A distinctive approach for forming a lateral bipolar charge-plasma transistor (BCPT) is explored using 2-D simulations. Different metal work-function electrodes are used to induce n- and p-type charge-plasma layers on undoped silicon-on-insulator (SOI) to form the emitter, base, and collector regions of a lateral n-p-n transistor. Electrical characteristics of the proposed device are simulated and compared with that of a conventionally doped lateral bipolar junction transistor (BJT) with identical dimensions. Our simulation results demonstrate that the BCPT concept will help us realize a superior bipolar transistor in terms of a high current gain, as compared with a conventional BJT. This BCPT concept is suitable in overcoming doping issues such as dopant activation and high-thermal budgets, which are serious issues in ultrathin SOI structures.

The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs and high mobility substrates, including compound semiconductors (III-V). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under low thermal budget environments for III-V materials. Ion implantation into III-V materials presents a problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. This paper presents a potentially defect-free alternative, mono-layer doping (MLD), which utilizes wet processing techniques.

We propose a new strategy for in-situ observation of dopant activation process using scanning tunnelling microscopy (STM) technology. Two factor techniques are established within our original STM system combined with liquid-metal-ion-source ion-gun (LMIS-IG/STM): (1) in-situ real-time observation of Si(001)-2×1 surface modified with dopant ions, and (2) in-situ hydrogen passivation of Si(001)-2×1 surface. Sequential STM images of the surface morphological changes are successfully obtained with keeping the original observation area. The hydrogenated Si(001)-2×1 surface is stable enough even under the degraded vacuum conditions which are unavoidable in ion irradiation processes. (© 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Ca5Al2Sb6 is a relatively inexpensive Zintl compound exhibiting promising thermoelectric efficiency at temperatures suitable for waste heat recovery. Motivated by our previous studies of Ca5Al2Sb6 doped with Na and Zn, this study focuses on doping with Mn2+ at the Al3+ site. While Mn is a successful p-type dopant in Ca5Al2Sb6, we find that incomplete dopant activation yields lower hole concentrations than obtained with either previously investigated dopant. High-temperature Hall effect and Seebeck coefficient measurements show a transition from nondegenerate to degenerate semiconducting behavior in Ca5Al2−x Mn x Sb6 samples (x = 0.05, 0.1, 0.2, 0.3, 0.4) with increasing Mn content. Ultimately, no improvement in zT is achieved via Mn doping, due in part to the limited carrier concentration range achieved.

Ion-implantation characteristics and dopant activation behavior of P in Ge have been investigated. A Monte Carlo simulation indicates a smaller projected range and consequently a smaller critical dose of amorphization for Ge compared to Si. The solid-phase epitaxial (SPE) regrowth characteristics of damaged layers for Ge clearly depend on crystal orientation of the substrate in completely amorphized samples, while no orientation dependent regrowth is observed in the partially amorphized samples. These phenomena were explained on the basis of the damage cluster model. In addition, maximum carrier activation coincides with the complete regrowth at annealing temperatures of 300–400 °C in completely amorphized samples. However, higher temperature annealing (500–550 °C) is necessary for maximum carrier activation in partially amorphized samples, although SPE regrowth completes around 250–300 °C. Analysis of the temperature dependence of carrier activation ratio in partially amorphized samples suggests that carrier-activation should be mediated by vacancy-migration.

In this paper, we studied the influence of nitrogen implantation dose on both physical and electrical properties in 3C-SiC grown on Si (100) substrate. Scanning Transmission Electron Microscopy characterizations prove that high dose is responsible for amorphization of the implanted layer and the high defect density after annealing. A high V-shape defect density is still found in the implanted layer after an annealing at 1350°C. By lowering the dose, the layer is less damaged and no amorphization is observed. For the different doses, low Specific Contact Resistances are measured using Ti/Ni contacts. The Specific Contact Resistance value decreases from 8x10-6Ω.cm2for the high dose to 3.2x10­6Ω.cm2with decreasing the dose. Furthermore, the dopant activation ratio, evaluated by quantitative SSRM measurements, is improved at the same time from 17% (for the high dose) to 60% (for the low dose). This work demonstrates that high activation ratio can be achieved consecutively to a nitrogen implantation at reasonable implantation fluence.

We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge09Si01 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an Ion/Ioff ratio exceeding 108, the highest ever reported for Ge-based pFETs.

The effect of electrical quality of interfacial oxide on Ge MOSCAP and MOSFET characteristics is investigated. Different growth conditions are studied to optimize the interfacial layer. CV and D"i"t measurements are done for accurate comparison of different gate dielectric stacks. Optimized ozone oxidation process is integrated with Co-induced dopant activation to fabricate Ge N-MOSFETs. Forty percent improvement in inversion electron mobility is demonstrated with optimized GeO"2 passivation. The highest electron mobility is reported in bulk Ge N-MOSFETs with GeO"2/Al"2O"3 gate dielectric stack.

The electrical activation of B + implantation at 2 keV to doses of 5.0 × 10 13 –5.0 × 10 15 cm −2 in crystalline and pre-amorphized Ge following annealing at 400 °C for 1.0 h was studied using micro Hall effect measurements. Preamorphization improved activation for all samples with the samples implanted to a dose of 5.0 × 10 15 cm −2 displaying an estimated maximum active B concentration of 4.0 × 10 20 cm −3 as compared to 2.0 × 10 20 cm −3 for the crystalline sample. However, incomplete activation was observed for all samples across the investigated dose range. For the sample implanted to a dose of 5.0 × 10 13 cm −2 , activation values were 7% and 30%, for c-Ge and PA-Ge, respectively. The results suggest the presence of an anomalous clustering phenomenon of shallow B + implants in Ge.

In this paper, the contact resistivity of NiGe on n-doped Ge is extracted. Although phosphorus is the slowest n-type dopant in terms of diffusion in Ge, the corresponding contact resistivity data for this dopant are sparse. Contact resistivity dependence on implant dose will be determined, as well as a comparison of phosphorus- and arsenic-doped Ge layers. The impact of high contact resistance is evaluated for future technology n-type metal-oxide-semiconductor germanium devices.

We have investigated the electrical activation in boron doped poly-Si using Hall measurement, 4-point probe, and secondary ion mass spectroscopy. Through doping was conducted using a mass-separated ion implanter with acceleration energies from 20 to 35 keV at doses ranging from 1 × 10 15 /cm 2 to 4 × 10 15 /cm 2 , followed by isothermal rapid-thermal-annealing at temperatures ranging from 550 to 650 °C. The substrates used were poly-Si, produced by two-shot sequential lateral solidification. Reverse annealing, in which a continuous loss of charge carriers occurs, was observed in boron doped poly-Si. We found that implantation conditions play a critical role on dopant activation as well as annealing conditions. We observed that a certain implantation condition does exist where the sheet resistance is not changed upon activation annealing. Damage recovery encountered in activation annealing seems to be closely related to a reverse-annealing phenomenon. We assume that the defect-concentration profile would be more important to activation behavior of poly-Si than integrated defect-density accumulated in the silicon layer.

Good-quality ultrashallow n + p junctions are formed using 5-keV amorphizing As+ implantations followed by a single-shot excimer laser anneal for dopant activation. By using an implant that is self-aligned to the contact windows etched in an oxide isolation layer, straightforward processing of the diodes is achieved with postimplantation processing temperatures kept below 400°C. A possible source of junction leakage at the perimeter caused by dip-etch enlargement of the contact window, also confirmed by transmission electron microscopy (TEM) analysis, is identified, and diode performance is improved by increasing the junction/contact window overlap. The optimum performance in terms of low leakage, shallow junctions, and low resistivity is achieved for 30° tilted implants and by applying a thin laser-reflective aluminum layer. This work isolates the minimum requirements for achieving low-leakage diode characteristics.

Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels on Si substrates is one of the most critical factors in obtaining optimal pMOSFET performance from high hole mobility of strained SiGe. A millisecond Flash-assisted rapid thermal annealing (RTA) technique was applied to source/drain (S/D) dopant activation of high-Ge-concentration SiGe channel MOSFETs with a high-k/metal gate stack. Flash annealing of SiGe channel pMOSFETs is shown to be an effective way to preserve channel integrity while achieving a low S/D resistance. Excellent mobility and short-channel device performance are realized. In addition, as the concentration of Ge in the SiGe layer is increased, high B activation can be achieved with a lower peak temperature Flash anneal. As a result, the sheet resistance of the implanted p+ junction can be comparable with that of higher temperature Flash-annealed (or optimal spike-annealed) Si. Furthermore, minimizing Ge diffusion reduces performance variation (such as statistical threshold voltage variation), which may be caused by the introduction and/or growth of defects in the strained SiGe heterostructure channel. It is shown that high-performance SiGe channel pMOSFETs with high Ge concentrations and a scaled high- k/metal gate can be achieved by a millisecond Flash-assisted RTA technique while preventing undesirable effects in the SiGe channel, such as within-wafer statistical performance variation.

In this work, non-intentionally doped cubic silicon carbide (3C-SiC) epilayers grown on (1 0 0) silicon substrates were implanted using nitrogen (N), phosphorus (P) implantations or their co-implantation (N&P). After annealing from 1150 to 1400 °C, Secondary Ion Mass Spectroscopy (SIMS), Atomic Force Microscopy (AFM), Fourier Transformed InfraRed spectroscopy (FTIR), Scanning Spreading Resistance Microscopy (SSRM) and Scanning Transmission Electron Microscopy (STEM) analysis were performed. Specific contact resistances (ρc) of Ti/Ni ohmic contacts were determined using Circular Transfer Length Method (c-TLM) patterns. Our work shows that co-implantation, experimentally investigated for the first time in 3C-SiC, is not beneficial for the doping efficiency. According to the silicon substrate, the post-implantation annealing is limited to 1400 °C. Consecutively to this limit, the total recovering of the lattice does not seem to be possible, whatever are the implanted species. Moreover, as the crystal damages increase when increasing the atomic mass of the implanted species, a comparative study using SSRM measurements proved that, for the same post-implantation annealing treatment, the resistivity of implanted layers depend on the doping species. As a consequence, the lowest ρc value (2.8 × 10−6 Ω cm2) has been obtained (using Ti/Ni 25/100 nm pattern) for a 1400 °C–30 min annealing consecutively to the nitrogen implantation. This value is among the best values obtained on implanted 3C-SiC layers in the literature. Furthermore, for this annealing temperature, a doping activation close to 100% has been evaluated by quantitative SSRM technique which evidences that an efficient dopant activation could be done. The high activation rate obtained on n-type implanted 3C-SiC and the low specific contact resistance achieved with Ti/Ni are very promising for electronic device fabrication.

In this paper, we optimize and investigate Ge n+/p and p+/n junction diodes formed by Co metal-induced dopant activation technique at the activation temperature range between 300 °C and 420 °C in terms of on/ off-current ratio. Combining this low-temperature n+/p and p+/n junction formation technique with a low-temperature gate stack comprised of Al/Al2O3/GeO2 by ozone oxidation technique, we demonstrate n- and p-channel Ge metal-oxide-semiconductor field-effect transistors (MOSFETs), respectively, at sub-360 °C and 380 °C. This low-temperature Ge MOSFET process can be utilized to integrate Ge complementary metal-oxide-semiconductor devices above interconnect layers for monolithic 3-D integrated circuits.

A systematic study of the impact of As + ion implantation on strain relaxation and dopant activation of biaxially strained SSOI layers and uniaxially strained/unstrained NWs is presented. Three aspects are investigated: (i) the quality of the single crystalline layers and the NWs, (ii) strain relaxation of the implanted NWs and (iii) dopant activation of the layers and NWs. Optimization of the doping conditions resulted into very low contact resistivities of NiSi contacts on strained and unstrained 70 nm SOI layers and Si NWs. For NW contacts values as low as 1.2 × 10 −8 Ω cm 2 for an As + dose of 2 × 10 15 cm −2 were achieved, which is 20 times lower than for planar contacts made under the same implantation and annealing conditions.

Ga-doped ZnO films were deposited by pulsed laser deposition (PLD) at 200 °C and 10 mTorr in either pure argon (Ar films) or in oxygen (O 2 films). The bulk resistivity of the Ar films is −4 Ω cm at 300 K, two orders of magnitude lower than that of the O 2 films. In the Ar films, the donor concentration N D as determined by a detailed Hall-effect analysis is close to 100% of the total Ga concentration [Ga] measured by secondary ion mass spectrometry (SIMS), while in the O 2 films N D is less than 50% of [Ga]. Furthermore, the compensation ratio K = N A / N D is >90% for the O 2 films and 2 films have resistivities of about 5×10 −4 Ω cm, approaching those of the Ar films. These results suggest that oxygen-rich environments produce Ga/O complexes that reduce the dopant activation efficiency and thus decrease N D and increase K . Some of these complexes may also contribute to the increase in deep centers observed in photoluminescence.

pMOSFET performance of high Ge content (~50%) biaxial compressive strained SiGe heterostructure channel pMOSFETs is characterized, and performance between 〈110 〉 and 〈100 〉 channel orientations on a (001) substrate is compared for physical channel lengths down to ~80 nm. Temperature-dependent mobility and velocity are characterized for both channel directions. First, it is shown that high Ge content SiGe-based channels can deliver drive current enhancement over unstrained Si below sub-100-nm channel lengths. Second, it is found that, with a higher Ge content SiGe channel under biaxial compressive strain, there is a difference of drive current between 〈110 〉 and 〈100 〉 channel directions, and the difference increases when temperature is lowered and/or when channel length is scaled down. An external series resistance difference is detected between two channel directions, although it appears to be insufficient to explain all the direction-dependent drive current difference. Channel transport behavior in different channel orientations can be clearly observed with low external source/drain (S/D) series resistance achieved with a millisecond S/D dopant activation anneal process while controlling the thermal budget. Two possibilities have been investigated to understand channel-direction-dependent performance: possible differences in effects of device processing impact between two channel directions and anisotropic transport effects from an anisotropic hole band structure, particularly under biaxial compressive strain in a SiGe channel pseudomorphically grown on a Si substrate.

In this work we demonstrate the fabrication and characterization of high performance junction diodes using annealing temperatures within the temperature range of 300-350?C. The low temperature dopant activation was assisted by a 50nm platinum layer which transforms into platinum germanide during annealing. The fabricated diodes exhibited high forward currents, in excess of 400A/cm2 at ~|0.7|V for both p+/n and n+/p diodes, with forward to reverse ratio IF/IR greater than 104. Best results for the n+/p junctions were obtained at the lower annealing temperature of 300?C. These characteristics compare favorably with the results of either conventional or with Ni or Co assisted dopant activation annealing. The low-temperature annealing in combination with the high forward currents at low bias makes this method suitable for high performance/low operating power applications, utilizing thus high mobility germanium substrates.

The activation behavior of implanted atoms was investigated in P/B ion-shower-doped poly-Si upon thermal annealing. Phosphorous or boron was implanted by ion shower doping at acceleration voltages from 2 kV to 15 kV by using a source gas mixture of PH3/H2 or B2H6/H2. Isochronal annealing was conducted using a tube furnace at temperatures ranging from 400 ◦C to 600 ◦C for 30 min. With some exceptions the sheet resistance decreased as the acceleration voltage increased upon annealing. Reverse annealing, in which the loss of charge carriers continues, was observed to start at around 400 ◦C in the case of B-doping.

One important parameter for modelling emitter recombination is the surface recombination velocity (SRV), which strongly depends on the surface doping concentration and the applied surface passivation. However, for highly phosphorus-doped surfaces with concentrations in excess of 2×1020 cm-3, where not all of the dopant is electrically activated, data is hardly available in the literature. Moreover, the bulk carrier lifetime in such supersaturated near surface regions is unknown. We use an analytical model to describe silicon-nitride-passivated phosphorus-diffused emitters. The model shows excellent agreement with a recently presented numerical solver, deviating less than 1%. In both cases we apply a Fermi-Dirac statistics correction and account for band gap narrowing to calculate the intrinsic carrier density. Our results from measurements of the emitter dark saturation current density indicate that either the SRV or the local carrier lifetime in the supersaturated region are strongly affected by the doping concentration, even if it exceeds the dopant activation limit by far. Assuming only Auger recombination in the supersaturated region, we derive an upper limit for the SRV that depends on the chemical phosphorus surface concentration.

We report high performance Ge p(+)/n junctions using a single, cryogenic (-100 degrees C) boron ion implantation process. High activation >4 x 10(20) cm(-3) results in specific contact resistivity of 1.7 x 10(-8) Omega-cm(2) on p(+)-Ge, which is close to ITRS 15 nm specification (1 x 10(-8) Omega-cm(2)) and nearly 4.5x lower than the state of the art (8 x 10(-8) Omega-cm(2)). Cryogenic implantation is shown to enable solid-phase epitaxial regrowth and lower junction depth through amorphization of the surface Ge layer. These improvements in Ge p(+)/n junctions can pave the way for future high mobility Ge p-MOSFETs.

Solid-phase-epitaxial regrowth (SPER) of Si amorphized by ion implantation is considered as a potential solution for the fabrication of highly-activated ultra-shallow junctions for future technology nodes of Si CMOS devices. In the frame of 32 and 22 nm technologies node development, SPER occurs after amorphizing implantations used in source/drain regions. To get an accurate simulation of dopant activation and junction depth position, a suitable continuum SPER model, implemented into a commercial simulator, is now mandatory. This TCAD model must consider the different physical effects associated with SPER: silicon regrowth rate, dopants redistribution snow plough effect, and interaction with silicon point defects. In this work, using a previously established model, we have implemented an improved physically based model for SPER and, several formulations have been developed to enable a robust/accurate modeling of the recrystallization velocity. It takes into account the direct interaction between amorphous/crystalline interface kinetics and point defects, and a regrowth rate dependent on temperature. Simulation results of dopant concentration profiles are in good agreement with experimental data and can provide important insight for optimizing the bulk silicon process as well in one dimension as two dimensions.

The ongoing downscaling of microelectronic devices requires dopant activation with diffusion kept to a minimum. One method considered in device processing is microsecond annealing by pulsed lasers. This is a highly non-equilibrium process during which intrinsic point defects generated at the surface diffuse into the material and form a variety of defects during cooling-down. Since the defects lie close to the surface, they may well affect the effective concentration and the formation of leakage currents in pn-junctions of advanced technologies. These defects may be clusters of intrinsic point defects or contain residual impurities like oxygen or dopants. In this work, a bare n-type silicon substrate (phosphorus concentration 5 × 1014 cm–3) was annealed with a pulsed laser with maximum temperatures of about 800 K up to 1650 K. The defects remaining after annealing were characterized by deep level transient spectroscopy (DLTS) to obtain their activation energies and capture cross-sections for majority carriers in n-type silicon. Additionally, the depth profiles of these defects were measured via a variation of the pulse voltage. The dominating defects found have levels at EC – 0.41 eV, EC – 0.31 eV, EC – 0.3 eV, EC – 0.22 eV, and EC – 0.17 eV. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The purpose of this paper is to study the impact of the different post-epi process steps on the stress behavior of epitaxially grown Si1-x-Gex layers on Si substrates and the subsequent defectivity and device leakage. Stress measurements were performed by the in-line monitoring laser reflectance method to further investigate the intrinsic film stress dependence on the ion implantation conditions (atom size, depth of the implant, and dose) and the laser scan energy beam conditions during dopant activation (temperature, dwell time, and power). Moreover, the role of the millisecond laser anneal conditions on the area leakage current of embedded SiGe source/drain junctions is discussed. The analysis is complemented with structural characterization based on Nomarski microscopy.

We investigate the optimal encapsulation conditions for obtaining fully activated, double δ-layersδ-layers of phosphorus in silicon. Using scanning tunneling microscopy and low-temperature magnetotransport we have explored whether it is important to optimize the maximal dopant incorporation of each individual layer or the smoothness of the surface on which we form the second dopant layer to achieve maximum total bilayer carrier density. We find maintaining crystallinity of the interstitial spacer layer is of paramount importance. In doing so, we are able to achieve double δ-layersδ-layers with high dopant activation resulting in a maximum carrier density of 4.35×1014cm−2.

Problem statement: In this study, a systematic study based on Technology CAD (TCAD) was taken up for the design and Virtual Wafer Fabrication (VWF) of strain-engineered MOSFETs in Si CMOS technology. Approach: A simple manufacturable process recipe was developed to induce uniaxial stress in channel region to obtain enhanced performance in CMOS in 45 nm technology node. Results: Using Synopsys Sentaurus Process simulation tool, high dopant activation and low Transient Enhanced Diffusion (TED) during processing are fully captured. A physics-based mobility model had been developed and implemented in Synopsys Sentaurus Device tool. Sentaurus Device was used to simulate device DC and AC characteristics and also to extract Vth, Ion and Ioff. Conclusion: Optimum process conditions required to meet a set of device specifications had been achieved via the Design of Experiment (DoE) study. Process Compact Model (PCM) was used for performance and manufacturability optimization.

Ion doping effect on low temperature poly-Si films has been investigated to suggest CW laser dopant activation as an alternative to conventional thermal annealing. The poly-Si films were ion doped with various B2H6/H2 or PH3/H2 plasma ion doses at an acceleration voltage of 16 kV, a RF of 13.56 MHz, and a RF power of 20 W. Then, the dopant activation was carried out by laser scan or conventional thermal annealing. The properties of ion doped poly-Si were examined by sheet resistance measurement and Raman spectroscopy. The sheet resistance of the ion doped poly-Si after laser dopant activation is sufficiently low compared to the value measured after the thermal annealing. EBSD was also examined to clarify grain boundary condition.

This paper shows that germanium n+/p shallow junction formation often results in poor leakage current control. It is due to the counteraction between the fast diffusion of phosphorus and the high-temperature annealing requirement for dopant activation and defect annihilation. When the dopant concentration is above a threshold value, the concentration-dependent diffusion enhances phosphorus diffusion and results in a box profile, leading to an electrical concentration lower than its solid solubility limit. A refrained thermal budget may increase the active concentration, but it is not sufficient to repair the implantation-damaged lattice. Moreover, any plasma-involved fabrication processes after rapid thermal annealing may introduce additional field-assisted defects into the depletion region when the junction is near the surface. Thus, several tradeoffs must be considered between high P activation, low junction leakage, and a shallow junction in order to obtain functional negative-channel metal-insulator-semiconductor field-effect transistors.

Heavy n-type doping in polycrystalline Ge (poly-Ge) is still under development owing to the low solid solubility and the low activation ratio of group-V dopants in Ge. To solve this problem, we have investigated ultra-short (55 ns) laser pulse annealing in flowing water for Sb-doped amorphous Ge1−xSnx layers (x ≈ 0.02) on SiO2. It is found that fully melting a Ge1−xSnx layer down to the Ge1−xSnx/SiO2 interface leads to a large grained (∼0.8 μmϕ) growth, resulting in not only a high electrical activation ratio (∼60%) of Sb atoms in the polycrystals but also a high electron density around 1020 cm−3. As a result, the electron mobility in the Ge-rich poly-Ge1−xSnx layers exceeds that in single-crystalline Si even in the region of a high electron density around 1020 cm−3. The low thermal budget process opens up the possibility for developing Ge1−xSnx based devices fabricated on 3D integrated circuits as well as flexible substrates.

In this work we investigate CO2 laser annealing at millisecond time scale for the fabrication of Ultra Shallow Junctions, able to fulfill the requirements imposed for sub-45 nm CMOS nodes. Silicon samples doped with Boron using BF3 plasma implantation technique at low energy (0.4 and 0.6 keV) were used to ensure ultra shallow as implanted boron concentration profiles. Our aim is to achieve high electrical activation level of the dopant, while maintaining the Boron concentration profile as immobile as possible. Samples have been irradiated at a variety of annealing conditions regarding the duration of the irradiation and the power density; however, in every case the peak surface temperature was kept in the range of 1080–1320 °C. Sheet resistance measurements indicate significant enhancement in the activation levels, while chemical characterization by means of SIMS, shows very limited movement of the dopant concentration profile, especially for short pulse duration conditions.

Due to the continuous CMOS transistor scaling requirements, highly doped shallow junctions with improved activation have been widely investigated in recent CMOS technologies. In this scope, sub-melt millisecond laser annealing has been introduced in the integration flows to enhance dopant activation, without any additional detrimental diffusion. This MSA step impacts not only the transistor junction properties, but also the polysilicon gate depletion. This paper is devoted to the study of the MSA influence on boron and germanium co-implanted polysilicon films. A sensitive boron diffusion occurring during the laser anneal step, with or without an initial spike annealing step, has been observed. The activation energy of the boron diffusivity extracted from SIMS profiles in the laser only sequence has been found equal to 4.05 eV. In addition, it was shown that either a high temperature laser anneal sequence or a spike anneal followed by a laser anneal sequence can reach the same activation levels.

We use scanning tunneling microscopy and low temperature magnetotransport measurements to study the effect of encapsulation temperature on phosphorus δ -layers in silicon. In particular we examine the quality of the resultant surface after encapsulation for the fabrication of three dimensional devices. Dopants were overgrown with 25 nm of silicon at temperatures between 250 and 300 °C. Electrical measurements show that 100% activation of dopants was obtained for 250 ∘ C encapsulation. However, dopant activation reduced to 54% as the growth temperature was increased to 300 ∘ C . Moreover we find that encapsulating above 270 ∘ C leads to dopant segregation that deactivates and broadens the δ -layer , without any substantial improvement in the quality of the regrowth surface.

Development and optimization of electronic devices in industrial and academic environments would hardly be conceivable without the numerical simulation of their processing and electronic behavior. In the past, model development efforts aimed especially at predicting junction depths. With the paradigm shift towards ultra-thin body silicon-on-insulator devices and FinFET architectures, the main emphasis changed to activation and lateral diffusion. Based on simulations of the electrical behavior of such advanced devices, the requirements on simulation of doping profiles will be explained. To achieve the high dopant activation needed to reduce contact and channel access resistances, active concentrations if possible above solid solubility are required. The concepts pursued involve annealing with low thermal budgets as well as defect engineering. A further paradigm shift concerns the semiconductor material used for future devices. While silicon, especially in a strained state, is still in the lead, research is also looking for alternative materials like germanium, germanium-rich silicon–germanium alloys, and III–V compounds. In order to be helpful, models for such processes and materials have to be provided as soon as possible even if the complexity of models for alternative materials lags behind contemporary models for silicon. The personal view of the authors is guided also by the International Technology Roadmap for Semiconductors for which one of us coordinates the modeling and simulation chapter.

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 °C, we measured an active dopant concentration of about 2.1 × 10 20 cm − 3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1–4 × 10 13 cm − 2 ) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values.

In this letter, low-temperature (480°C) microwave annealing (MWA) for MOS devices with high-k/metal gate-stacks is demonstrated. The capacitance-voltage (C-V) characteristics of the MOS gate-stacks, TiN/HfO2, and TaN/HfO2, after different annealing methods are discussed. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated using low temperature MWA. In addition, the short channel effects in nMOSFETs annealed by MWA can be also improved because of the suppression of dopant diffusion and stabilization of EOT.

The transient activation model allows for a description of dopant deactivation through mechanisms such as dopant clustering. Here we propose a refined model to permit simulation of antimony (Sb) dopants in ultra-shallow junctions based upon data from differential Hall measurements, which are used to determine electrically active doping concentrations in relaxed (no epitaxial strain) and strained silicon. We determined the appropriate clustering parameters enabling the transient activation model to reproduce the supersaturated phenomenon of Sb dopants as well as the enhanced dopant activation observed for strained silicon relative to relaxed silicon. This refined version of the transient activation model is applicable for both metastable and thermal equilibrium conditions. Our analysis reveals that the forward rate for dopant clustering is suppressed for Sb as the strain is introduced. The energy barrier for Sb deactivation due to clustering is extracted for relaxed and 0.7% tensile strained silicon.

The presence of high electric fields at the drain junction in polycrystalline silicon (polysilicon) thin film transistors (TFTs), enhances several undesired effects, such as hot-carrier related instabilities and kink effect. In order to reduce the drain electric field, non-self-aligned (NSA) device architecture can be adopted. In this case, dopant activation and active layer crystallization are achieved at the same time by excimer laser annealing, resulting in a substantial lateral dopant diffusion. The gradual doping profile provides not only a reduction of the drain electric field, but also a channel length shortening. Therefore, an effective channel length (L eff ) has to be determined in such devices, in order to successfully design circuit applications. In this work, L eff and parasitic resistance (Rp) modulation effects have been investigated in both n- and p-channel NSA polysilicon TFTs. Three different parameter extraction methods, originally proposed for the crystalline MOSFETs technology, have been used and compared in order to extract L eff and R p , including: the "channel resistance" method; the "paired V g " method; the "shift and ratio" method. These methods indicate a channel length reduction up to 1 μm and a non negligible parasitic resistance effect. The reliability of the results of the three methods are discussed in terms of applicability of the underlying assumptions in the case of polysilicon TFTs and numerical simulations are used to support the analysis.

Solid phase epitaxy re-growth of arsenic implanted in silicon on insulator (SOI) was studied by Rutherford Backscattering Spectrometry and Transmission Electron Microscopy. Two SOI structures with different Si overlayer and buried oxide thicknesses were used. The As+ implantations were performed with a single energy of 20 keV to a dose of 5x1014 cm-2 in both substrates. A plateau-like profile was achieved in an additional set of SOI samples by triple energy implantation. Rapid thermal annealing and conventional furnace annealing were applied for re-crystallization and dopant activation. The results are discussed considering the amorphization depth reached by dopant implantation and the crystal recovery process via thermal treatment.

Off-axis electron holography has been used to measure the electrostatic potential profile across the p-n junction of an AlGaAs/GaAs light-emitting diode with linearly graded triangular AlGaAs barriers. Simulations of the junction profile showed small discrepancies with experiment when the nominal dopant concentrations of Si and Be impurities were used. Revised simulations reproduced the measurements reasonably using reduced dopant levels that reflected the efficiency of dopant activation. Band-edge diagrams simulated with the nominal and revised dopant concentrations were also compared in terms of the effect that activation efficiency had on the AlGaAs barrier shape and carrier transport. It is concluded that electron holography measurements combined with modeling offer device designers and growers a helpful tool for analyzing and confirming doping profiles in complex heterostructures.

This paper presents a novel approach to make high-performance CMOS at low temperatures. Fully functional devices are manufactured using back-end compatible substrate temperatures after the deposition of the amorphous-silicon starting material. The amorphous silicon is pretextured to control the location of grain boundaries. Green-laser annealing is employed for crystallization and dopant activation. A high activation level of As and B impurities is obtained. The main grain boundaries are found at predictable positions, allowing transistor definition away from these boundaries. The realized thin-film transistors (TFTs) exhibit high field-effect carrier mobilities of 405 cm2/Vmiddots (NMOS) and 128 cm2/Vmiddots (PMOS). CMOS inverters and fully functional 51-stage ring oscillators were fabricated in this process and characterized. The process can be employed for large-area TFT electronics as well as a functional stack layer in 3-D integration.

In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited- Al2O3 gate dielectrics. The magnitudes of the rectifying ratios for the Ge p+-n and n+-p junctions exceeded three and four orders of magnitude (in the voltage range of plusmn1 V), respectively, with accompanying reverse leakages of ca. 10-2 and 10-4 A ldr cm-2, respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300degC boosted the device on-current, decreased the Al2O3/Ge interface states to 8 times 1011 cm-2 ldr eV-1, and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm2 ldr V-1 ldr s-1 and > 103, respectively, for the p-FET (W/L = 100 mum/4 mum), while these values were less than 100 cm2 ldr V-1 ldr s-1 and ca. 103, respectively, for the n-FET (W/L = 100 mum/9 mum). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.

The recrystallization process for ion implanted Si was characterized by photoluminescence (PL) at room temperature. By comparing the results of PL, four-point probe measurements, and current-voltage measurements of shallow pn junctions, we found PL a sensitive indicator, as intensity increased with even small decreases in sheet resistance of less than 10 ohm/sq. PL intensity also increased as ideality factor n and leakage current (of shallow p-n junctions) decreased. These results indicate a strong correlation between PL intensity and dopant activation. PL measurement is non-contact and non-destructive and can be used as an in-line monitor for dopant activation and crystalline damage recovery.

Spike Rapid Thermal Annealing (RTA) is commonly used method for source and drain dopant activation in 65nm CMOS technology. It is found that the Idsat variation is very sensitive to RTA temperature. To better control the Idsat uniformity across the shot, a systematic study on STI and poly pattern density distribution across the shot field and their effects on the RTA temperature was carried out. It was demonstrated that the STI and poly pattern density variation across the field will result in more than 10ºC RTA temperature variation. To minimize the effect, an optimization of RTA ramp rate and peak temperature was studied. Source/drain (S/D) extension and S/D implant optimization has also been done for the reduction of PMOS device Idsat temperature sensitivity