CMOS compatible self-aligned S/D regions for implant-free InGaAs MOSFETs

CMOS compatible self-aligned access regions for indium gallium arsenide (In 0.53 Ga 0.47 As) implant-free n-type metal oxide semiconductor “eld effect transistors (MOSFETs) are investigated. In situ doped n+source/drain regions are selectively grown by metal-organic vapor phase epitaxy and self-alignedNickel InGaAs alloyed metal contacts are obtained using a self-aligned silicide-like process, where differ-ent process conditions are studied. Soft pre-epitaxy cleaning is followed by X-ray photoelectron spectros-copy, while the Ni InGaAs/III V interface is characterized by back-side SIMS pro“ling. Relevant contactand sheet resistances are measured and integration issues are highlighted. Gate-“rst implant-free self-aligned n-MOSFETs are produced to quantify the impact of Ni InGaAs contacts on the deviceperformance. 2012 Elsevier Ltd. All rights reserved. 1. IntroductionDue to their higher injection velocity, III V compound semicon-ductors and in particular indium gallium arsenide (InGaAs) arebeing studied as possible candidates to replace Si as the channelmaterial in metal oxide semiconductor “eld-effect-transistors(MOSFETs) for digital logic applications. Several challenges haveto be tackled to bene“t from the III Vs superior transport proper-ties and achieve a high drain current performance. Achieving lowresistance self-aligned source/drain access regions suitable forhigh-performance logic at 10 nm node and beyond is one of themost critical challenges. These contacts have to be highly compat-ible with standard CMOS ”ows, scalable to the small-pitch require-ments and thermally stable to stand the back-end process.Several approaches have been tried such as ion implantationwhich has shown its limits due to the too high thermal budget re-quired to achieve a decent S/D dopant activation[1]. Selective epi-taxy of in situ doped InGaAs S/D regions has been done bymolecular beam epitaxy (MBE)[2] and metal-organic vapor phaseepitaxy (MOVPE) [3], achieving a high carrier density in a self-aligned gate-“rst scheme. These two approaches require a III Vcleaning recipe which includes a wet etch down to an etch-stoplayer before regrowth. Etching the channel material prior to S/Dformation is not an option in the case of fully-depleted types ofarchitectures like extremely-thin compound semiconductor oninsulator (ETCSOI).Low contact resistance and self-aligned molybdenum (Mo)metal contacts have been demonstrated using a height-selectiveetching process[4]. However, this process might be dif“cult tomanufacture over large wafer size on scaled devices. A salicide-like(self-aligned silicide) process on III V has been developed using aNickel InGaAs (Ni InGaAs) alloy integrated in a metallic S/D n-MOSFET[5,6] which suffers from a high off-state drain currentdue to the absence of a channel-to-S/D p n junction.In this work we report on a CMOS compatible process ”ow toachieve self-aligned implant-free access regions for In