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Foundry-enabled Ge-on-Si waveguide (WG) photodiodes (PDs) with on-chip bias circuit are demonstrated. While a single-element PD has a 52-GHz bandwidth (BW) and a radio frequency (RF) saturation power of −11 dBm at 40 GHz, PD arrays composed of 2 and 4 PDs have RF saturation powers of −6.7 dBm at 40 GHz and −2.3 dBm at 27 GHz, respectively. The bias circuits are analyzed.

In this paper we revisit the memristor concept within circuit theory. We start from the definition of the basic circuit elements, then we introduce the original formulation of the memristor concept and summarize some of the controversies on its nature. We also point out the ambiguities resulting from a non rigorous usage of the flux linkage concept. After concluding that the memristor is not a fourth basic circuit element, prompted by recent claims in the memristor literature, we look into the application of the memristor concept to electrophysiology, realizing that an approach suitable to explain the observed inductive behavior of the giant squid axon had already been developed in the 1960s, with the introduction of "time-variant resistors." We also discuss a recent memristor implementation in which the magnetic flux plays a direct role, concluding that it cannot strictly qualify as a memristor, because its $v-i$ curve cannot exactly pinch at the origin. Finally, we present numerical simulations of a few memristors and memristive systems, focusing on the behavior in the $\varphi-q$ plane. We show that, contrary to what happens for the most basic memristor concept, for general memristive systems the $\varphi-q$ curve is not single-valued or not even closed., Comment: 13 pages, 19 figures

The upgrade to 30 T of the existing 25 T cryogen-free magnet (25 T CSM) at the High Field Laboratory for Superconducting Materials, Tohoku Univ., will consist in replacing the existing High Temperature Superconductor insert made of Bi-2223 by one wound using REBCO tape. The new insert is designed to produce 16 T instead of 11 T. In order to have good dynamics and allow sweeping mode experiment, the insert will be conventionally isolated, as it was the case for the previous Bi-2223 version. In previous work we modelled thermal runaway phenomenon and showed that a sensitive dissipative voltage detection technique can give sufficient warning to protect an HTS coil using external dump resistor even in the case of sharp local critical current drop. For the 30 T insert, the conductor will consist of a two tape bundle so as to reduce the chance of such sharp Ic drop due to tape performances inhomogeneities or local damage. We simulate the quench dynamics in the LTS outsert coupled with the HTS insert to demonstrate that the existing detection/protection system of the 25 T CSM can be re-used and determine the current dumping dynamics. We then use our thermal runaway modelling tool to study the behavior of the future 16 T REBCO insert in case of local sharp defect and determine realistic detection threshold for its safe protection.

This article presents a dual-mode power divider (PD) that offers new working mechanism, compact size, significant design freedom, wide working bandwidth, arbitrary power division, and ultrawide isolation between the two output ports. The structure is simple in comparison with conventional Wilkinson PDs in that only two composite right-and left-handed (CRLH) transmission lines (TLs) grounded through two resistors are used. Different from previous CRLH-TL-embedded studies in that almost all CRLH-TLs operate at quarter-wavelength phase responses, in the present work, the zero-degree property is noted and used to modify the impedance variation curves. Additionally, because of the use of grounded resistors, the proposed PD can operate in two modes, such that when high-value resistors are used, the PD operates in a lossless mode, while when low-value resistors are used, the PD operates in an attenuated mode. Because working power has been significantly improved due to progress in modern RF system development, more attenuation elements are required. This means that attenuated PDs will become very useful in the future. For verification, two PDs operating in different working modes and power divisions are designed and fabricated. Based on the experimental results, both PDs demonstrate good performance over more than 60% of the bandwidth with reference to the 15-dB $S_{11}$ , ultrawide isolation, full port matching, and compact size.

UHF RFID reader suffers from a strong transmitter (Tx) leakage signal coupled to a receiver (Rx), especially for an area-compact single-antenna implementation. Then, several Tx leakage cancellation schemes have been developed not to saturate the Rx and to minimize the performance degradation. This brief proposes a UHF RFID reader Rx with a low noise performance and a fast settling time by employing a digitally controlled leakage cancellation method in both passive and active realizations. A digitally-controlled passive vector reflector enhances the Tx to Rx isolation ratio by providing the optimum load impedance. An active anti-leakage feedback loop adaptively tracks the time-varying leakage and generate the phase-inverted leakage replica to suppress the leakage. The prototype chip is fabricated in a CMOS 55 nm process and the area of the chip is 2.1 mm $\times1.8$ mm. The passive leakage cancellation (PLC) with a vector reflector endures the 1 dBm leakage with a low Rx noise figure of 12.5 dB and 35.7 mW power consumption. The active leakage cancellation (ALC) with an anti-leakage feedback loop covers 6 dBm leakage with a fast settling time of $4.6~\mu \text{s}$ and 58 mW power consumption.

A perfect varistor is a constant voltage resistor as a function of current through the resistor. A perfect varistor can't exist, because its resistance would be infinite at zero current. In electronic devices, varistors are often used as surge protectors. A varistor can be used in place of an ordinary resistor as the discharge resistance across superconducting coil sections. When used this way, the integral of I2 dt during the discharge can be reduced by almost one third. When a varistor is used for quench protection of coils that are coupled to shorted secondary circuits the integral of I2 dt can be reduced much more. This can be a key factor when coil current densities and stored energies are high as in many potential HTS magnet systems. This paper discusses the types of varistors that are commercially available and their characteristics.

Recently, the circuit under pad (CUP) designs are getting very popular because they could save lots of silicon especially for high-density and high-complexity applications. Polysilicon is a material widely used in many electronic device components. When such devices are placed underneath the bond pads, it is highly expected not to show any change in the electrical behavior due to any kind of thermo-mechanical stresses such as probing or wire bonding mainly during the process of packaging. This article presents a detailed investigation of such impacts on a polysilicon resistor placed underneath the bond pads. The standard meander-shaped polysilicon resistor was used as a test vehicle. In this article, different stress-causing factors such as probing insertions, probing temperature, and wire bond materials were investigated in detail. The impact of such thermo-mechanical stresses is simulated using Comsol to understand the stress phenomenon and for qualitative analysis. Then, the wafer-level silicon testing was carried out to quantify the impact of such thermo-mechanical stresses using a standard design of experiments (DOEs). The impact in terms of change in resistance of the polysilicon resistor of two different widths (5 and 0.42 $\mu \text{m}$ ) for two different bond pad metal options viz. Middle thickness metal (METMID) (thickness of 880 nm) and thick metal (METTHK) (thickness of 3000 nm) was investigated. The percent change in resistance was observed to be very negligible after multiple probing attempts and probe temperatures. However, after wire bonding, up to ~14% change in resistance was observed when copper was used as the wire bonding material. Nevertheless, this percent change was still well within the reliability specification limit set by Joint Electron Device Engineering Council (JEDEC), which is widely used in the industry. This detailed investigation will help CUP designers choose the correct back end of line (BEOL) metal options and also wire bonding material upfront and accordingly plan their design margins.

A class AB two stage op-amp with accurate static current control, symmetric signal paths to the output transistors, and suitable for environments with uncertain or variable supply voltages is presented. The implementation of the conceptual floating voltage source for the push pull operation in the output stage has the ability to adopt positive and negative values indistinctively by means of a resistor with bidirectional currents driven by a control circuit. The latter requires very few additional devices and power consumption compared to the conventional scheme and is capable of operating with supply voltages as low as a gate-source voltage and a saturation voltage of a transistor, and as high as permitted by design and technology. Experimental results from a fabricated prototype in $0.5\mu \text{m}$ technology show the class AB operation of the amplifier driving a load capacitance of 16 pF.

Multiloop constant on-time (COT) controlled buck converter uses two weight resistors for sensing inductor current and detecting output voltage in its inner loop. When an output capacitor with a small equivalent series resistance (ESR) is employed, the converter will suffer the risk of instability due to different weight settings of inductor current and output voltage using a proportional–integral (PI) compensation gain in the outer voltage loop. However, no attention has been paid for their stability effects, which are important for designing the inner loop and outer voltage loop. To address these issues, a piecewise linear model is established for multiloop COT-controlled buck converter. Circuit parameter-related bifurcation behaviors and control weight-related dynamical distributions are explored to demonstrate these stability effects. Furthermore, by deriving an approximate discrete model, a control weight-related stability criterion is expressed explicitly, from which stability boundaries for dividing the normally stable and abnormally unstable operation parameter regions are thereby yielded. Besides, control weight-related transient performances under different circuit parameter settings are analyzed. Finally, PSIM circuit simulations and hardware circuit experiments verify the theoretical analysis well.

The negative holding voltage of high-voltage (HV) dual-directional silicon-controlled rectifier (DDSCR) is usually attenuated to a very low level due to the grounded guard ring, which has been ignored by many researchers nowadays. In this brief, a novel symmetrical DDSCR (SDDSCR) is proposed to suppress the deterioration of DDSCR’s negative holding voltage. By introducing a diffusion resistor into the p-type guard ring (PGR), experimental results indicated that the reverse parasitic SCR path associated with PGR is suppressed effectively. Thus, a symmetric high holding voltage characteristic is implemented for SDDSCR without increasing any silicon footprint. Moreover, the PGR resistor technology presented in this brief can be extended to various existing HV DDSCRs, which could improve their negative holding voltage deteriorated by guard ring.

We have developed a 6-kA/cm² superconducting integrated circuit fabrication process toward large-scale single flux quantum digital circuits. To evaluate the process reliability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and tested. Fabrication parameters, for example, film thicknesses and etched depths of the layers, were measured by testing specific patterns during fabrication. Design parameters such as the critical current density J c, normal-state resistance R n and actual sizes of Josephson junctions, the sheet resistance of Mo resistor R sh, and the penetration depth of Nb films were evaluated by electrically characterizing PCM circuits after fabrication. We also monitored superconducting critical currents for vias and Nb lines, and insulation properties between the metal layers systematically.

We present a study on the layout design of the rad-hard standard logical cells and fault-tolerant static random access memory (SRAM) cells. We used the previously developed layout-aware SPICE-based simulation technique to check the design patterns that involve sensitive node spacing and contact placement to increase the tolerance to multiple node upsets. The results of the simulations were transformed into layout design recommendations verified by the simulation and experimental data for SRAM cells with layout design supporting the recommendations. The results proved the efficiency of the proposed hardening measures.

Non-destructive measurements of nA beam currents in particle beam storage rings by detecting the azimuthal magnetic field generated by moving charged particles with a Cryogenic Current Comparator (CCC) are well established. The detection of beam currents with small amplitudes with a CCC in a storage ring demands a high slew rate which is caused by the rapid change of the beam current exceeding the operational limit of the SQUID in flux-locked loop mode. Previous solutions to increase the slew rate used a LCR first-order low-pass filter were a small resistor, unfortunately, dominated the current noise of the CCC. In this work we present a novel take by adding a second resonator into the CCC which in turn allows for higher resistances of the LCR low-pass filter and therefore lower thermal current noise. A second challenge connected with this CCC approach is the residual magnetization of the highly permeable magnetic core and the resulting shielding currents in the superconducting circuits of the CCC. The timing of a storage ring in the range of minutes opens a way to reduce these DC currents using a LR high-pass filter. Using serial sub-micro ohm resistors, time constants in the hour range can be achieved to improve the stability and performance of the CCC system.

A controller PHY for high-capacity DRAM is presented. To reduce precursor and postcursor intersymbol interference due to its dispersive channel characteristics and a heavy load of many DRAM chips and to attenuate reflection on a highly reflective command/address (C/A) channel, a damping-resistor-aided three-tap pulse-based feed-forward equalizer (PB-FFE) is introduced. An appropriate damping resistance can attenuate reflection, and the PB-FFE compensates for increased insertion loss due to the damping resistor. In addition, the current flows only before and after a signal transition in the PB-FFE, improving energy efficiency and maintaining the turn-ON resistance during the no-transition region. A controller PHY based on this equalizer was fabricated in a 55-nm CMOS process. The PB-FFE increases the timing margin of the C/A signal from 0.23 to 0.29 UI at 1067 Mb/s. At 2133 Mb/s, the read timing and voltage margins of the DQ signal are 0.53 UI and 211 mV after read training, and its write margin is 0.72 UI and 230 mV, respectively, after write training.

A gallium nitride (GaN) boundary conduction mode (BCM) dual-boost ac–dc converter for low-voltage electromagnetic energy harvesting (EH) is presented in this article. The μ W-to-mW EH system is very susceptible to any tiny losses from power converters, interconnections, and system parasitic. To have better utilizations of harvested energy, an output power enhanced power conversion design is proposed. First, impedance matching is satisfied between electromagnetic generator and ac–dc converter to achieve maximum delivered power. The ac–dc converter is designed under BCM for constant input impedance. EH's winding inductance is employed as the boost inductor in the ac–dc converter. A codesign principle for converter on -time with electromagnetic generator's winding characteristics is revealed. Second, power transistors in EH low-voltage conversion are optimized to realize high efficiency. Power transistors’ low-voltage switching characteristics are significantly different from high-voltage situation with no or little miller plateau region. Low-voltage power transistors are compared from both device characteristics and calculated power loss to provide device selection guidance. A GaN-based dual-boost ac–dc converter under BCM operation with constant on -time controller is designed in this article to provide 3.3 V output for a 500-Ω load resistor. It achieves peak efficiency of 82.4% for open-loop operation at 0.6 V/100 Hz input and peak efficiency of 72.3% for close-loop operation at 0.75 V/100 Hz.

A frequency selective surface (FSS) absorber with a biasing control system is presented in this letter. The absorber consists of the top-layer FSS structure, the bottom-layer metal sheet, and an air spacer in between. The biasing circuit is controlled by a single-chip microcomputer with constant current outputs and each output port is connected to one p-i-n diode, which is employed to realize different absorption bands by controlling the induced current distribution. Both simulated and measured results demonstrate that fast switching function can be realized within certain frequency ranges (3.62–5.35 GHz and 7.92–9.27 GHz) with the absorption depth below −10 dB.

Insulated gate bipolar transistor (IGBT) collector current measurement based on the package parasitics between the power emitter ( E ) and the Kelvin emitter ( E′ ) is a lossless and real-time monitoring method. A step to improve accuracy is to precisely match the time constant ( Rf × Cf ) of the measurement circuit against the package parasitics ( LEE′ / REE′ ). This article proposes an automated time constant matching method to realize the tuning of Rf × Cf to LEE′ / REE′ , and a detection circuit to continuously measure the IGBT collector current using the package parasitics. In the proposed method, the Miller plateau voltage is first sampled, and a polynomial curve fit is carried out to determine the fitting parameters associated with the IGBT collector current ( IC ). A programmable resistor Rf is then adjusted automatically based on the step response of the readout voltage until the time constant is matched. A ratio between the readout voltage and a known IC is then calculated based on the Miller plateau voltage. The proposed system is verified using a field-programmable gate array controller and discrete components. Experimental results confirmed the functionality of the proposed method, showing that the readout voltage versus IC relationship has good agreement in the range of 0–165 A, with less than 3% error. The proposed method can also be used for overcurrent protection with a detection time of less than 0.7 μ s.

We demonstrated interface circuits between a half-flux-quantum (HFQ) circuit and a rapid single-flux-quantum (RSFQ) circuit to obtain SFQ/HFQ and HFQ/SFQ converters. These converters were created by simply inserting a resistor between an RSFQ circuit and the adjacent HFQ circuit, where both circuits are based on pulse logic. These converters enable us to create combinatory circuits that make the best use of the features of the two circuits. Using a DC/SFQ, SFQ/HFQ, HFQ/SFQ, and SFQ/DC converter, we measure an HFQ Josephson transmission line (JTL) composed of eight 0-0-π superconducting quantum interference devices (SQUIDs), which are the essential elements of an HFQ circuit. The 0-0-π SQUIDs are composed of two conventional Josephson junctions and a π-shifted ferromagnetic junction. The HFQ JTL demonstrated in this study is driven by a bias current 11-fold lower than that of a similar RSFQ JTL. These experimental results indicate that the HFQ circuit requires power that is two or more orders of magnitude lower than that of an RSFQ circuit.

We present in this paper the design and implementation of a multilayer 6-bit resistor ladder network capable of operating up to 50 GHz for use in superconductor flash analog to digital converters (ADCs). Implementation of such a resistor network requires the design and optimization of various resistors (25 Ohm, 37.5 Ohm, and 50 Ohm). It is important to minimize the parasitic elements (inductance and capacitance) associated with resistor layout in-order to maintain the performance of the resistor ladder network up to 50 GHz. The paper proposes the use of floating niobium layers around the resistor layer to minimize parasitic effects. The fabricated 6-bit resistor network has a size of 3.2 mm $ \times $ 3.2 mm and is tested in a Lake Shore Cryogenic probe station. The measured results for the individual resistors and the overall integrated network are in agreement with the EM simulation results.

Although large piezoresistive sensor arrays are vital in obtaining 2D pressure distributions in many applications, they suffer from crosstalk forming parasitic parallel paths as a result of their generic shared row-column architecture. Existing software based algorithms and post processing is the industrially utilized crosstalk suppression mechanism which is below par in meeting the desired measurement accuracy and shape accuracy requirements. However, several hardware based implementations based on the zero potential method have been proposed in literature to mitigate crosstalk and deliver reasonable measurements with repressed crosstalk. Nevertheless, they are often confined to smaller sensor array sizes meeting the requirements of low density applications like robotics where power consumption, design complexity, magnitude of external dimensions, cost of implementation and higher scanning rates are not the governing constraints during the design process. Adopting existing mechanisms directly into scanning large sensor arrays violate the aforementioned design constraints, thus, a novel approach is required. Here, we have proposed and implemented a readout circuit based on zero potential crosstalk suppression, with an improved decoder-transistor based scanning architecture, for a large piezoresistive sensor array containing 30000 sensels meeting the design constraints. The developed circuit was validated using a miniaturized resistor model in conjunction with circuit simulations in PSPICE to determine the propensity of the readout circuit to deliver a measurement accuracy (error less than 1%) while maintaining shape accuracy at the hardware level.

To optimize the high-speed modulation package of the TO-can mounted violet laser diode (VLD) for optical wireless communication, three different impedance matching methods with adding or removing resistor/inductor/capacitor (R/L/C) elements are employed to discuss their effects on the direct encoding bandwidth of the VLD. With reducing the parasitic inductance by shortening the cathode/anode pin length of the TO-can VLD, the 2.5-mm-long pin acts as a series inductance to 1.74 nH to enormously improve the modulation bandwidth of the VLD for encoding the 16 quadrature amplitude modulation orthogonal frequency division multiplexing data as high as 20.4 GB/s. Neither the surface mounted device (SMD) resistor nor the SMD inductor in series connection can further improve the modulation bandwidth of the VLD. In contrast, a parallel connection of the VLD with Teflon ring capacitor can somewhat broaden its encodable bandwidth at low biased conditions, whereas the allowable bandwidth still degrades when increasing the VLD bias to enlarge its modulation throughput. Numerical simulations also verify that the shortening pin length (with reducing the inductance) of TO-can VLD is the best selection for bandwidth enlargement. With optimized impedance matching design, the comparison on data transmission characteristics for several 2.5-mm-pin VLDs with different rated powers is presented.

Silicon carbide (SiC) power devices possess many beneficial properties for power electronics applications, but commercial 62-mm SiC power module packages with the direct drop-in replacement of Si devices limit many benefits of these SiC power devices. To fully utilize the advantages of the SiC power devices, this article presents a low-profile and high power density packaging solution of a 62-mm 1200-V/300-A SiC power module with enhanced electrical and thermal performance. The design optimizations on layout, chip placement, and terminal structure are compatible with the conventional module fabrication processes. An increase of power density by threefold is achieved with a low-profile package by reducing the height of the terminal connectors. Moreover, lower voltage overshoots of gate–source and drain–source of the proposed module are demonstrated due to low inductance in both gate and power loops. Thermal simulations show that the proposed module has a lower peak junction temperature and a more balanced temperature distribution among paralleled devices. Finally, the commercial and fabricated modules are characterized experimentally under the same conditions. Both simulation and experimental results show that the gate and power loop inductances of the proposed module are reduced by 96% and 76%, respectively. Moreover, the total switching loss and drain–source voltage overshoot are reduced by 44% and 54%, respectively, at 300 A using a 2- $\Omega $ external gate resistor.

Modular multilevel converters (MMCs) are very promising and attractive in medium-/high-voltage applications. One of the main technical challenges associated with MMCs is to precharge all submodule (SM) capacitors to their nominal voltage values during a startup process. This article proposes a simple and effective startup strategy for MMCs based on a deadbeat predictive current control. This strategy can realize a fast precharge for all the SM capacitors from either ac-side or dc-side main voltages without any inrush current and, thus, guarantees a rapid and safe startup of MMCs. With the developed strategy, precharge currents from both ac-side and dc-side can be easily regulated in a closed-loop manner with an excellent dynamic performance. Moreover, conventional controller design and parameter tuning are not necessary, which greatly reduces design burdens and structural complexities of the control algorithm, and consequently facilitates its implementations. Detailed design processes and considerations of the proposed startup strategy are introduced and analyzed. The effectiveness and performance of the developed strategy are verified by sufficient experimental results.

We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2 films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance R sh of 2 Ω, followed by the deposition of Nb/Al-AlO x /Nb trilayer Josephson-junction. The target critical current density J c was set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.

In this study, the trade-off among power consumptions, operating frequencies, and error rates in low-power single-flux-quantum (SFQ) circuit is investigated. The power consumption of SFQ circuits can be reduced by the lowering critical currents ( $I_{\mathrm{c}}$ values) of the Josephson junctions (JJs), or the bias voltage ( $V_{\mathrm{b}}$ ). The shifts and spreads of timing parameter fluctuations when $I_{\mathrm{c}}$ and $V_{\mathrm{b}}$ were lowered were numerically analyzed, with consideration of thermal noise at 4.2 K. The timing behaviors after $I_{\mathrm{c}}$ was lowered were relatively simple, being based on the signal-to-noise ratio, whereas those for lowered $V_{\mathrm{b}}$ values were complicated because of the dynamic behaviors of JJs driven at reduced voltage. The simulation results imply that the operating frequencies decreased because the timing windows narrowed, but the highest energy efficiency was obtained when we lowered $I_{\mathrm{c}}$ or $V_{\mathrm{b}}$ to 6.25% of their conventional values, and the energy reduction after lowering of $V_{\mathrm{b}}$ was 26% better than that after lowering of $I_{\mathrm{c}}$ . Moreover, if a small error rate (for example $10^{-6}$ ) is acceptable, further improvement in energy efficiency would be expected at significantly higher clock frequencies than would be the case if the SFQ circuit must exhibit error-free operation.

Integrated circuits sensitive to both total ionizing dose (TID) and displacement damage (DD) effects can exhibit degradation profiles resulting from a combination of degradation mechanisms induced by both effects. This work presents circuit simulations based on experimental data to explain degradation mechanisms induced by combined TID and DD effects on a bipolar IC current source. First, the effect of the degradation of each internal transistor on the circuit’s response is evaluated by applying electrical parametric changes. Then simulations are performed from different degradation scenarios based on observed circuit behaviors to reproduce the different TID, DD, and combined TID–DD responses. These simulations show that a synergistic interaction between a current leakage induced by DD on a transistor located in the bandgap reference part with the gain degradation of a current mirror induced by both TID and DD appears to be responsible for the combined TID–DD response. It is also shown that the circuit degradation rate depends on the DDD/TID rate ratios encountered during the exposition.

Sensor integration is widely demanded in many applications. For sensor fabrications, a cross-point structure is beneficial because of its low cost, while the readout interface circuit suffers from sneak currents, which can lead to enormous readout error. In this study, the developing electric olfaction system which integrates over 1,000 gas sensors was introduced. Compared to previous works, the array size tends to become large, and resistance values can be widely distributed. We employed the conventional voltage feedback method for the interface circuit because it can measure a wide range of resistance. However, since it constitutes the voltage divider circuit with the selected resistor and the reference resistance by an op-amp unity gain feedback, the readout accuracy is affected by its large load sensor resistance. Therefore, a calibration technique for the voltage feedback method was proposed. The feedback error caused by the load resistance and op-amp nonidealities was analyzed with a simplified circuit, in which circuit parameters such as an array scale, a reference resistance, and an op-amp output impedance were variable. The sneak currents were estimated in the calibration by utilizing the op-amp input difference, and their effects were eliminated. The simulation results showed that the readout error of $32\times 32$ resistive array with 10% distributed resistance could be decreased from around 3% to less than 0.005%. The dependency of the readout accuracy on an op-amp’s gain input offset voltage was evaluated systematically to apply the calibration to a practical system.

This research article reports electronically tunable high-frequency meminductor based on single output operational transconductance amplifiers (OTA) and differential voltage current conveyor (DVCC). The reported design has two OTAs, one DVCC, two capacitors and a resistor. Here we have presented both theoretical as well as the simulation aspects of the meminductor design using Cadence Virtuoso at 0.18 µm CMOS technology. Both methods verify the realization of meminductor behaviour. It demonstrated huge electronic tunability with external bias voltage in a wide operating frequency range of 10 MHz. Further, the circuit performance estimation with respect to various parameters such as process corners, capacitor, voltage, temperature, and frequency variation is also carried out here in detail.

Abstract Purpose This paper aims to achieve two main objectives. First, to introduce to the literature a new versatile active building block, namely, voltage differencing differential voltage current conveyor (VD-DVCC) for analog signal processing applications. Second, to design a novel electronically tunable mixed-mode universal filter. The designed filter provides low-pass, high-pass, band-pass, band-reject and all-pass responses in voltage-mode (VM), current-mode (CM), trans-impedance-mode (TIM) and trans-admittance-mode (TAM). Design/methodology/approach The proposed filter uses two VD-DVCCs, three resistors and two capacitors. All the capacitors used are grounded, which is advantageous from the monolithic integration point of view. The VD-DVCC is designed and validated in Cadence software using CMOS 0.18 µm process design kit from Silterra Malaysia at a supply voltage of ±1 V. Findings The proposed novel filter enjoys many attractive features including as follows: the ability to operate in all four modes, no requirement of capacitive matching, tunability of quality factor (Q) independent of pole frequency, availability of both inverting and non-inverting outputs for VM and TIM mode, high output impedance explicit current output for CM and TAM, no requirement for double/negative input signals (voltage/current) for response realization and low active and passive sensitivities. The filter is designed for a pole frequency of 5.305 MHz. The obtained results bear a close resemblance with the theoretical findings. Originality/value The proposed novel filter structure requires a minimum number of active and passive components and provides operation in all four operating modes. The filter will find application in structures of mixed-mode systems.

This article presents a Photoplethysmography (PPG) sensory system for continuous health monitoring. The PPG chip is fabricated using $0.35~\mu \text{m}$ standard CMOS technology and occupies 2.3 mm $\times$ 1.7 mm. The average power consumption of the receiver analog front-end (AFE) is $50.75~\mu \text{W}$ , the LED driver is power $29.3~\mu \text{W}$ . The consumed power is dramatically reduced due to the using of both low duty cycle for LED lighting and automatic light control (ALC). The PPG sensor has a low input noise current of 41.3 pA and can reject a DC photocurrent up to $24~\mu \text{A}$ because of the integrated background light cancelation (BLC) loop. 12-b SAR-ADC and Serial Peripheral Interface (SPI) are integrated for communication with MCU used for signal processing and results display. Readings of 9 subjects show mean absolute error (MAE) and standard deviation (SD) of 1.95±2.13 beats per minute (BPM), 6.00±4.18mmHg, and 6.13±3.93mmHg, for heart rate (HR), systolic blood pressure (SBP), and diastolic blood pressure (DBP), respectively.

Purpose The purpose of this study is to investigate the utility of carbon black containing coating formulations that are conventionally used for pigment printing of textiles in fabricating electrically heated fabrics. Design/methodology/approach Specifically, electrical and thermal characterisation of the coating system was carried out to establish the feasibility of the system for use in the manufacturing of flexible heating elements on textile substrates. The coating formulations were applied via a simple padding technique followed by stitching the electrodes using a conductive yarn. Findings The heating elements of different sizes thus produced showed Ohmic behaviour as a resistor and attained a targeted temperature difference of up to 40°C within the applied voltage range. A prototype heater was also produced, and thermography results showed uniform heating and cooling of the heater that was incorporated into a jacket. Originality/value The proposed method is envisaged to be very practical for the realisation of completely textile-based heating elements of different shapes and sizes. Furthermore, the proposed manufacturing method can be used to convert conventional ready-made articles of clothing into heated textiles for various applications.

This paper presents carbon nanotube field effect transistor (CNTFET) implementation of voltage differencing current conveyor (VDCC). We propose new topology of multi input–single output (MISO) CNTFET VDCC universal filter using only 2 resistors and 2 capacitors. The CNTFET VDCC filter circuit can be tuned electronically only by changing transconductance value, and there is no need for component matching conditions. The proposed CNTFET VDCC filter shows 2711 times less power consumption compared to 0.18 µm TSMC technology and around 500 times reduction in chip area. Center frequency shift between 0.33 and 2.45 MHz was observed by varying transconductance value. Besides, the quality factor of VDCC filter was improved by increasing resistor value. All simulations were performed by using SPICE simulation tools.

This paper introduces a simulated grounded inductor (SGI) circuit realization based on two terminal active devices, namely negative impedance converters. The proposed SGI contains a minimum number of passive components when compared to its two terminal active device-based realization counterparts in the literature. It includes a grounded capacitor that is an advantage in integrated circuit process. Nonetheless, a single resistive matching constraint is needed for its realization. SPICE simulations are performed with 0.13 mu m CMOS IBM technology parameters with supply voltages of +/- 0.75 V. Also, an experimental study is included to verify the theory.

Calibration of electrical resistance measures is considered by the indirect method, which is realized through measuring the voltage drop across the series-connected reference and calibrated resistors. The biases of the estimates of the measurand and the combined standard uncertainty due to the nonlinearity of the measurement model were calculated. The distribution laws of the input quantities in the calculation of the expanded uncertainty were taken into account by the kurtosis method. An example of measurement uncertainty evaluating during calibration of single-size electrical resistance measure R331 with a nominal resistance of 1000 Ω by comparing its value using a potentiometer R345 with the value of the calibrated reference standard is considered. Estimates of the measurand and its standard and expanded uncertainties obtained using the proposed method showed good agreement with the estimates obtained using the Monte Carlo method.

In this brief, a 2.4-GHz low-power single-quadrature low-IF Bluetooth low energy receiver employing a quadrature local oscillator (LO) buffer is presented for Internet of Things applications. The quadrature LO buffer, which consists of common-source amplifiers with capacitive degeneration, compensating resistors, compensating PMOS transistors and LC tanks, performs quadrature generation and supplies quadrature signals to a single-quadrature mixer, thus eliminating an additional circuitry for quadrature generation in the LO path and saving dc current consumption. The implemented receiver consists of a low-noise amplifier, a $G_{m}$ -stage, double-balanced current-mode passive mixers, transimpedance amplifiers, an active- RC complex bandpass filter, and the quadrature LO buffer. Fabricated in a 65-nm CMOS process, the implemented receiver achieves a noise figure of 8.16 dB, a conversion gain of 54.5 dB, an image rejection ratio of 32.1 dB, and an input-referred third-order intercept point of –27.5 dBm. It draws a bias current of 2.5 mA from a nominal supply voltage of 0.8 V, and the active die area is 1.65 mm2.

In recent years, SiC MOSFET s have gained strong attention in medium-voltage power conversion applications. To increase the blocking voltage level, series-connection of SiC MOSFET s is an attractive solution but may suffer a severe voltage unbalance issue. To gain insights into the voltage unbalance issue, this article presents a detailed study of the impact of parasitic capacitors on the voltage sharing of series-connected SiC MOSFET s and body-diodes. The parasitic capacitors are categorized into two groups for analysis: 1) parasitic capacitors from gate terminal; 2) parasitic capacitors from drain/source terminals. The study reveals that gate parasitic capacitors affect gate miller-plateau voltage and ultimately the d v /d t during the turn- off . The voltage sharing will be worse under higher turn- off current or larger gate resistor. The drain/source parasitic capacitors will introduce additional capacitance across device drain-source terminals which results in an unbalanced voltage sharing. The position of switching unit and the heatsink connection schemes will affect the distribution of drain/source parasitic capacitors to cause different voltage sharing results. The drain/source parasitic capacitors will also cause voltage unbalance of series-connected body-diodes under different conditions. To verify the analysis, the voltage sharing between two series-connected 10 kV SiC MOSFET s is tested under different parasitic capacitors conditions.

This brief proposes a method to dynamically modeling the coupled-inductor double-boost converter operating in continuous-conduction mode. Such method has the advantage of including the leakage inductance effect on the dynamic behavior of the converter in a simple, straightforward approach. The presence of the leakage inductance is initially neglected and a traditional circuit-averaging technique is used. The averaged models are then refined by accounting the impacts of the reported inductance. Since its major impact is on the damping factor of the system, this dynamic change is modeled by equivalent resistors. Equations for describing the equivalent resistors are derived based on the analysis of the duty cycle loss caused by leakage inductance in the static gain of the converter. The effect on the averaged small-signal model is shown by a closed-form control-to-output transfer function and experimental results demonstrate its accurate performance.

Cochlear implants use electrical stimulation of the auditory nerve to restore the sensation of hearing to deaf people. Unfortunately, the stimulation current spreads extensively within the cochlea, resulting in “blurring” of the signal, and hearing that is far from normal. Current spread can be indirectly measured using the implant electrodes for both stimulating and sensing, but this provides incomplete information near the stimulating electrode due to electrode-electrolyte interface effects. Here, we present a 3D-printed “unwrapped” physical cochlea model with integrated sensing wires. We integrate resistors into the walls of the model to simulate current spread through the cochlear bony wall, and “tune” these resistances by calibration with an in-vivo electrical measurement from a cochlear implant patient. We then use this model to compare electrical current spread under different stimulation modes including monopolar, bipolar and tripolar configurations. Importantly, a trade-off is observed between stimulation amplitude and current focusing among different stimulation modes. By combining different stimulation modes and changing intracochlear current sinking configurations in the model, we explore this trade-off between stimulation amplitude and focusing further. These results will inform clinical strategies for use in delivering speech signals to cochlear implant patients.

A pulse matching tapered post-wall slotline antenna based on the lumped resistive and reactive loading network is proposed, and its time-domain operation mechanism, design method, and performance are investigated. The loading network is composed of a series branch of a resistor and a parallel branch of an inductor and a resistor. The network can effectively assimilate the nonradiated low-frequency components and transmit the short pulse with little distortion for the short-pulse excited antenna, and thus this design is termed as pulse matching antenna (PMA). The time-domain analysis for the loading network and the entire structure demonstrates the pulse matching and pulse radiation characteristics of the loaded antenna. The PMA is fabricated and its performance in both the frequency and time domains is demonstrated. The proposed antenna exhibits a good match for a Gaussian pulse with a spectrum of up to 10 GHz, an average realized gain of 8.10 dBi from 6 to 10 GHz with a fluctuation less than 1.62 dB, and a radiation efficiency greater than 46.39% from 4 to 10 GHz. The proposed antenna is featured by pulse matching and short-duration pulse radiated field and is suitable for short-pulse and ultrawideband applications.

This work reports first original results on the impact of active in-situ electro-thermal recovery, on the electrical and low-frequency noise characteristics of N-type MOS transistor with thick high-k metal gate oxide, from 28 nm Fully Depleted Silicon-On-Insulator (FDSOI) process. In order to recover “typical” device characteristics, four cycles of local thermal annealing up to 590K are applied for 14 ms each, using an active silicide source. Experimental results reveal an important improvement of the “corner” transistor’s I-V behavior allowing the recovery of “typical” device characteristics. An increase of the maximum transconductance by 43% is obtained. In the same time, a typical device stays unaffected by this local annealing. Low-frequency noisemeasurements showa clear reduction of the 1/f noise and Random Telegraph Noise by almost one decade, after the electro-thermal recovery. This can explain the improvement of the electrical characteristics by annealing of defects.

Metal-oxide based bipolar Resistive RAM (RRAM) is one of the most promising candidates for the future non-volatile data storage. Due to unique properties e.g., small footprint, ability to modulate resistance states in wide ranges dynamically, hysteresis and CMOS compatibility, RRAM can be a fruitful candidate for analog circuit design. However, the recent literature only scratches the surface of this interesting prospect. In this paper, a single RRAM behavior is studied under temperature, voltage and process variations from an analog design standpoint. A comparative study is performed between two analog circuits namely, Common Source (CS) amplifier and differential amplifier with traditional passive resistors and with passive resistors replaced by RRAM along with two other design examples, namely constant $g_m$ g m biasing circuit and active low-pass filter, where RRAM can be integrated into analog circuits. Our study shows that blind swapping of passive resistors with RRAM in analog circuits can actually degrade the performance metrics. We propose techniques such as usage of RRAM Low Resistance State (LRS) to recover the loss. We also note that hyperbolic I-V characteristics of RRAM can inherently improve the linearity of RRAM based analog designs. Simulation results indicate that RRAM based amplifiers can achieve 2X area reduction, about 1.5X higher bandwidth with only $\approx 9\%$ ≈ 9 % reduction in gain. The resistance modulation property of RRAM is applied to realize a source degenerated amplifier with reconfigurable linearity, to a constant transconductance bias circuit to avoid resistance trimming and to design a programmable active low pass filter.

The practical aspect of nanotechnology includes the production of devices and their components needed to create, process and manipulate atoms, molecules and nanoparticles. The phenomena of aging and self-heating significantly affect the operation of microelectronic circuits. This paper developed a model of a three-bit, parallel analog-to-digital converter with low power consumption, as a result of which the circuit does not use resistors and comparators. The absence of resistors improves the static power consumption of the circuit and reduces the problems associated with aging and self-heating, while the absence of comparators has a positive effect on the dynamic power consumption. The Parallel A/D converter has been designed for a 14 nm process, at 25°C, for input signals with an amplitude of 1.8 V. The results obtained show that the developed converter uses about 100 times less energy compared to the classical architecture. Since the eight resistors were removed from the circuit, the area of the resulting converter was reduced by at least 8Rnom, where Rnom = 0.7225 μm is the area of the 1 KΩ resistor.

A subranging analog-to-digital converter (ADC) with reference-embedded comparators (RECs) is proposed. By adjusting the bias current and/or body voltage of the REC’s input differential pair, the REC offset can be adjusted to a specific voltage equal to a reference voltage referred to henceforth as the embedded reference. For the ADC’s coarse stage, RECs with wide-range embedded references are implemented by adjusting the bias currents using current source arrays to cover the full-scale input. By contrast, for the ADC’s fine stage, RECs with narrow-range embedded references are implemented by adjusting the body voltage. In addition, the centers of the embedded references in the different ADC subranges are created by current source arrays, which are digitally scaled according to the coarse ADC’s output codes. As a result, the reference-voltage-switching network used in conventional subranging ADCs is not required, and hence the speed of the ADC is increased. Moreover, to eliminate the effects of process variation, the bias currents and body voltages in the RECs are calibrated with an auxiliary resistor ladder. After the calibration, the resistor ladder is removed. Consequently, no resistor ladder is used during normal operation, which greatly saves power. A 3 mW 6-bit 4 GS/s REC-based subranging ADC is implemented in 28-nm CMOS technology. With a near Nyquist frequency input, the ADC achieves SNDRs of 31.8 dB and 30.7 dB at 3.6 GS/s and 4 GS/s, respectively. Moreover, at 3.6 GS/s, the ADC has a Walden Figure-of-Merit (FoM $_{W}$ ) of 22.7 fJ/conv-step, which is the best compared with prior state-of-the-art 6-bit high-speed ADCs.

In this article, a novel $n$ -way topology is proposed to design a class of multiway wideband filtering power dividers (FPDs). It consists of $n$ -coupled multimode resonators and $n$ resistors. To achieve a wideband filtering response, the stub-loaded multimode resonator is first employed. A good port–port isolation can then be obtained by electrically connecting the original open end of the two half-wavelength stubs of the two adjacent multimode resonators, and amounting a shunt resistor in-between the two adjacent stubs, which is allocated a quarter-wavelength away from the electrical connection point. The frequency responses of power division and isolation are analyzed based on even–odd mode, aiming to carry out theoretical analysis for wideband $n$ -way power dividers. To verify the proposed design method, a prototype three-way wideband FPD and a four-way wideband FPD are designed and fabricated. The simulated and measured results show a good agreement from each other, thus verifying the feasibility of this proposal.

This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) voltage-mode transmitter (TX) with a four-tap feed-forward equalizer (FFE). A two-step coarse-/fine-tuning technique is adopted in the voltage-mode FFE to reduce the number of front-end slices while maintaining sufficient resolution. In addition, the device sizes in the preceding multiplexer (MUX) and predriver can be enlarged, relaxing the self-loading effect from the layout and improving the bandwidth. An analog impedance control loop is applied to achieve output impedance matching and maintain the corresponding weighting between coarse- and fine-FFE stages. The quarter-rate 4:1 MUX incorporates an automatic phase alignment technique to eliminate the timing constraint. As a result, all of the retiming latches can be removed, saving significant power. Designed and fabricated in 40-nm CMOS, the PAM-4 TX demonstrates a high-quality eye diagram at 112 Gb/s with 3.89-pJ/b energy efficiency under a chip-on-board assembly with 5.5-dB Nyquist loss.

This brief presents a low-noise chopper amplifier that uses a lateral PNP input stage with automatic base current cancellation in complementary metal–oxide–semiconductor (CMOS) process. A bipolar junction transistor (BJT) input stage can achieve lower noise level than the MOS transistor input stage, but its base current causes low DC input impedance. To enhance the DC input impedance of the BJT input stage, an automatic base current cancellation circuit is implemented using a 10-bit current digital-to-analog converter (DAC) and a successive approximation register (SAR) logic. The output current of the DAC tracks the base current of the BJT input stage using a binary search operation of the SAR logic, and the current DAC provides a cancellation current to the base of the BJT input stage to cancel the input base current. The amplifier is implemented in 0.18- $\mu \text{m}$ CMOS process, and the proposed amplifier occupies an active area of 0.297 mm2. The current consumption of the chopper amplifier is 146 $\mu \text{A}$ with 3.3 V supply voltage. The input referred noise of the chopper amplifier is 5.53 nV $/\surd $ Hz. The input bias current of the proposed amplifier with lateral PNP input stage implementing automatic base current cancellation is 0.391 nA.

This brief presents the ultra-miniaturized wideband input-absorptive bandstop filters with one and three transmission zeros using the thin film integrated passive devices (TFIPD) technology. It is based on a novel T-shape structure with lumped-element resonators and one resistor chained on the input port. The basic bandstop block composed of lumped-element resonators can be synthesized by the Chebyshev reflective prototype values ( ${g}$ -parameters). In order to further expand the stopband bandwidth and improve the frequency selectivity, the series inductance and capacitance resonator (SICR) is loaded on the basic bandstop block, thus resulting in two extra transmission zeros. The chained resistor on the input port is used to absorb the input-signal power. For demonstration, the one-zero and three-zero design cases operating at 5 GHz are simulated, manufactured and measured, respectively.

In this article, a novel wideband high-selectivity filtering power divider (FPD) with all-frequency absorptive performance is presented. It is based on two cascaded coupled-line (CL) sections loaded with half-wavelength open-circuit stubs and three resonator absorptive stubs. To realize all-frequency absorption of the RF-input-power, three simple absorptive stubs composed of quarter-wavelength short-circuit stubs series with resistors are applied. By introducing the CL sections with half-wavelength open-circuit stubs, the power divider (PD) is easy to realize wideband high-selectivity filtering performance and deep stopband suppression. Besides, the impedances of the open-circuit stubs can be independently adjusted to control the bandwidth. Furthermore, explicit design equations and limitations of implementations are derived and discussed. Good agreements between the simulated and measured results verify the correctness of the design theory.

Recurrent ladder network models are encountered in the analysis of many natural systems including wave propagation in transmission lines, porous electrode/electrolyte interfaces and viscoelastic (bio)materials. Here we re-visit the equivalent impedance of self-similar ladder networks composed of two arbitrary impedances recursively arranged, with the goal of correlating the behavior of the whole versus that of the part. We show that the macroscopic and microscopic scales are related via a generally complex-valued parametric scaling factor. We report on two new universal complex numbers that we denote as the Complex Golden Ratios . We also show that a lumped inductor (with its internal series resistance) or a lumped capacitor (with its parallel parasitic resistance) are actually equivalent to an infinite ladder network that involves resistors and imaginary resistors only. Finally, we show that the Cole-Davidson model, widely used in material characterization, naturally arises from the self-similar circuit ladder structure. Comparison with tree networks is also discussed.