Analysis of Bipolar Integrated Circuit Degradation Mechanisms Against Combined TID–DD Effects

Integrated circuits sensitive to both total ionizing dose (TID) and displacement damage (DD) effects can exhibit degradation profiles resulting from a combination of degradation mechanisms induced by both effects. This work presents circuit simulations based on experimental data to explain degradation mechanisms induced by combined TID and DD effects on a bipolar IC current source. First, the effect of the degradation of each internal transistor on the circuit’s response is evaluated by applying electrical parametric changes. Then simulations are performed from different degradation scenarios based on observed circuit behaviors to reproduce the different TID, DD, and combined TID–DD responses. These simulations show that a synergistic interaction between a current leakage induced by DD on a transistor located in the bandgap reference part with the gain degradation of a current mirror induced by both TID and DD appears to be responsible for the combined TID–DD response. It is also shown that the circuit degradation rate depends on the DDD/TID rate ratios encountered during the exposition.