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Systems of negative silicon carbide crystals are classified and studied by experimental methods. The crystal structure and morphology forming during growth, etching, and erosion are discussed.

From the study of 6H and 4H single crystals, grown under various conditions on Si- and C- terminated seed surfaces, two types of defects with different slit length are discussed. Short slits with a length in the submillimetre range are spread between micropipes in an advanced growth stage. Their generation is correlated to micropipe agglomeration. The long slits up to some millimetres, which are associated with dislocation bundles in the basal plane, are correlated to polytype domain walls. In this region the slit formation seems to be favourable similar to the Frank mechanism of micropipe generation (Acta Crystallogr. 4 (1951) 479).

The disturbance of the growth steps in SiC epitaxy and the formation of stacking faults (SFs) in the vicinity of a micropipe were studied by Atomic Force Microscopy and Transmission Electron Microscopy. Shallow trenches are observed in front of the micropipes due to the distortion of the growth steps towards of the micropipe. The trenches are related with extended (1 (1) over bar 00) type SFs bounded by 1/6 partial dislocations. These results are also supported by synchrotron X-ray topography.

Micropipe is a vital defect for fabricating SiC based devices. In order to understand the evolution of micropipe during growth process, the authors studied axial cuts sliced from different parts of the sublimation grown SiC single crystals. The cuts have been characterised using optical microscopy, etching in molten mixed KOH and K2CO3, scanning electron microscope and X-ray photoelectron spectroscopy. It is found that second phase inclusion (silicon droplet) is contributing not only to the formation of micropipe defect but also to its termination during SiC growth process. And X-ray photoelectron spectroscopy measurement result shows that growth interface can be demarcated obviously without intentionally doping any other impurity, which offers a good and simple method for observing crystal growth process.

The interference pattern around micropipes of 6H-SiC single crystal (0 0 1) substrate has been characterized by polarizing optical microscopy. The interference pattern showed anisotropy around micropipes, which was thought to result from edge dislocation caused by internal strain. A model experiment using a stress-induced acryl resin board certainly demonstrated a similar interference pattern to the 6H-SiC single crystal, when tensile and compression stresses were applied to each side in the vicinity of an open hole in the acryl resin board. Stress distribution around the micropipe of 6H-SiC single crystal was discussed in connection with the existence of edge and screw dislocations. The size of the micropipe depended on the Burgers vector, and an internal strain generated around the micropipe was correlated with the edge dislocation.

This paper reviews the present understanding of defect formation and development in relation to process conditions in 4H-SiC crystal growth and epitaxy. The polytype uniformity during seeded sublimation growth of SiC boules has been discussed. Insight into different structural imperfections has been attempted. The role of the temperature distribution, as well as of the quality of seed/crystal interface in the occurrence of grown-in defects has been demonstrated. Micropipe termination by liquid-phase deposition along with defect evolution in subsequently grown layers due to rough interface has been addressed. Finally, a relation between extended morphological defects in thick (50-100 µm) 4H-SiC epitaxial layers and local stress in the material has been suggested. Optimised growth conditions to reduce the overall defect density have been proposed. © 2001 Elsevier Science B.V. All rights reserved.

Fundamental issues of silicon carbide, i.e., characteristics, crystal growth, doping of impurity atoms, metal-SiC contacts, electronic devices, etc., are given. Applications for the detection of energetic particles are also shown.

Silicon carbide (SiC) single crystals, a promising material for high power and high temperature semiconductor devices, have microscopic hollow defects, so-called “micropipes.” Their formation mechanism is not satisfactorily clarified yet. In this paper, a surface step model for micropipe formation in SiC single crystals is proposed, where the strong repulsive interaction between surface steps on the SiC(0 0 0 1) surface is a major driving force for coalescing unit cell size screw dislocations.

The production of large diameter, high quality SiC substrates is essential to realize the full potential of this important semiconductor material. The current status of SiC bulk sublimation growth for the production of these substrates is reviewed from an industrial point of view. Specific efforts towards larger diameter high quality substrates have led to the production of 50 and 75 mm diameter 4H and 6H wafers and the demonstration of high quality 100-mm wafers. We present thermal conductivity data for material of different doping levels, relevant for device applications. In SiC, micropipes are the most harmful defects for SiC device production. By continuous optimization of the growth process we were able to steadily decrease the micropipe density over the past several years, down to densities as low as 1.1 cm −2 for an entire 50-mm wafer, indicating that micropipes may be totally eliminated in the next few years. In order to achieve this goal for SiC substrates of increasing diameter, a thorough understanding of the growth process is essential. We will summarize results of modeling the growth process and its experimental verification. The effect of micropipe densities and their characteristic lateral distribution in SiC wafers on achievable device yields will be discussed, using large area Schottky diodes as an example.

Recent development and current status on the growth technology of silicon carbide (SiC) single crystals, long-known as a promising wide bandgap semiconductor material applicable to electronic devices of higher performance, are briefly described. The micropipe defect density, which is known to cause fatal problems in SiC devices, has been reduced significantly, and up to date no longer cited as the most harmful defect for device applications. In addition, such technological advance has led to the increase of the crystal diameters up to 100mm, evoking acceleration of SiC device productions.

Micropipes in a 6H–SiC semiconductor wafer were studied by scanning electron and atomic force microscopy. The screw dislocations intersecting the wafer's surface were located by etch pitting, and their Burgers vectors determined by x-ray topography. The etch pits were eroded into smooth craters by ion beam etching to expose levels of dislocation line from inside the sample's bulk. There a micropipe's diameter is distant from surface relaxation effects. Hollow cores (micropipes) were observed at the base of the craters whose screw dislocations had Burgers vectors of magnitude three multiples of the c-lattice parameter and higher. Screw dislocations with 1c and 2c Burgers vectors had no associated micropipes.

Commercial epilayers are known to contain a variety of crystallographic imperfections. including micropipes, closed core screw dislocations. low-angle boundaries, basal plane dislocations, heteropolytypic inclusions, and non-ideal surface features like step bunching and pits. This paper reviews the limited present understanding of the operational impact of various crystal defects on SiC electrical devices. Aside from micropipes and triangular inclusions whose densities have been shrinking towards manageably small values in recent years, many of these defects appear to have little adverse operational and/or yield impact on SiC-based sensors, high-frequency RF, and signal conditioning electronics. However high-power switching devices used in power management and distribution circuits have historically (in silicon experience) demanded the highest material quality for prolonged safe operation, and are thus more susceptible to operational reliability problems that arise from electrical property nonuniformities likely to occur at extended crystal defects. A particular emphasis is placed on the impact of closed-core screw dislocations on high-power switching devices, because these difficult to observe defects are present in densities of thousands per cm,in commercial SiC epilayers. and their reduction to acceptable levels seems the most problematic at the present time.

In this study we demonstrate the feasibility of micropipe reduction in SiC commercial wafers by using liquid phase epitaxial (LPE) growth. We have studied the stability of the micropipe healing by performing hot KOH etching and growing thick (40-50 mum) layer with sublimation epitaxy at temperature higher than that used for the LPE growth. Experimental evidences have been collected by means of different techniques and a phenomenological model for micropipe healing is proposed.

A major obstacle to commercial insertion of silicon carbide device technology into power electronics is the presence of hollow-core defects, known as micropipes, in the substrate material. Although considerable progress has been made to reduce the micropipe density to less than 100 per cm, the continuing presence of these defects is widely believed to be a limiting factor in the development of large-area devices. Additionally, the presence of large numbers of closed-core screw dislocations, dislocation defects and other defects contribute to poor scaling of SiC power devices [1]. A process to reduce the micropipe density by filling the defects with silicon carbide and covering the repaired material with a Liquid Phase Epitaxy (LPE) layer has been developed at TDI, Inc. [2-5]. Large area Schottky diode device performance on SiC epi layers grown using Chemical Vapor Deposition (CVD) on both conventional and repaired substrates at the Emerging Materials Research Laboratory (EMRL) have also been reported [6]. One result of these early experiments was a significant improvement in the surface morphology (reduction of step-bunching in the LPE layer) of the reduced micropipe substrate material. More recently, a transmission electron microscopy (TEM) investigation of TDI’s micropipe reduction method with CVD epi has suggested that few dislocations may be generated at the LPE/CVD interface [7].

Recent achievements in crystal growth and homoepitaxy of SiC, mainly of the 4H polytype, have been discussed. Several growth techniques, such as seeded sublimation growth, high temperature chemical vapor deposition, sublimation epitaxy and liquid phase epitaxy have been utilized to develop technological procedures and understand the growth processes better. The advantages of either method have been stressed. The main target has been the reproducible growth of micropipe free substrate material and thick epitaxial layers for device applications. The purity of the layers has been of special interest. The results obtained are indicative for the massive progress that has been achieved in SiC crystal growth during recent years.

High-purity SiC single crystals with diameter up to 50 mm have been grown by the physical vapor transport method. Finite element analysis was used for thermal modeling of the crystal growth cavity in order to reduce stress in the grown crystal. Crystals are grown in high-purity growth ambient using purified graphite furniture and high-purity SiC sublimation sources. Undoped crystals up to 50 mm in diameter with micropipe density less than 100 cm −2 have been grown using this method. These undoped crystals exhibit resistivities in the 10 3 Ω cm range and are p-type due to the presence of residual acceptor impurities, mainly boron. Semi-insulating SiC material is obtained by doping the crystal with vanadium. Vanadium has a deep donor level located near the middle of the band gap, which compensates the residual acceptor resulting in semi-insulating behavior.

Silicon-carbide-based device technology as well as the volume production of nitride-based, high brightness blue and green LEDs fabricated on SiC substrates has made tremendous progress within the last several years. The commercial availability of large, high-quality SiC substrates is a key issue for the realization of the full potential of this technology. The current status of SiC bulk sublimation growth for the industrial production of 50 mm diameter 4H and 6H wafers and the quality improvement of 75 mm wafers is reviewed. Results at Cree show a continous reduction of the micropipe density in SiC substrates, demonstrating micropipe free material of a 25 mm diameter and densities as low as 1.1 cm −2 for an entire 50 mm 4H–SiC wafer. We present results of modeling the relevant heat transfer processes during crystal growth and the thermoelastic stress in the growing crystal. The effect on dislocation generation is discussed. The recent interest in SiC for the production of a unique gemstone material (moissanite) additionally increases the demand for high-quality SiC bulk material.

A technique to reduce the micropipe density in SiC substrates by first filling in the defects and then growing an LPE layer on the filled material has been developed by TDI. LPE growth in SiC is known to result in poor surface morphology, namely step-bunching due to the off-axis substrate orientation. Chemical vapor deposition (CVD) growth experiments on SiC substrates with reduced micropipe density using a cold-wall CVD reactor resulted in a significant improvement in the surface morphology. Although preliminary device results are encouraging, the exact nature of the filled micropipes nor the impact of growing CVD epitaxial layers on LPE SiC had not been fully characterized. We have preformed transmission electron microscopy (TEM) measurements to evaluate the crystallographic properties of the CVD/LPE and LPE/substrate interface. It was observed that no new dislocations were nucleated at the LPE/CVD interface. Although a micropipe was not located in the samples characterized, a tilt of 1.5° was observed between the LPE layer and the substrate. In addition, dislocations were observed to propagate through the LPE layer from the substrate which are most likely the 1C close-core screw dislocations common to SiC hexagonal substrates.

This paper presents an overview of SiC power devices. The progress in pn junction diode development is described. The data on 10 A, 1000 V, packaged 4H–SiC ion-implanted p + nn + diode are presented. It is found that in order to develop high voltage, high current diodes, it is critical to reduce dislocation density below 10 3 cm −2 , and increase substrate doping of n + 4H–SiC above 10 19 cm −3 . It is simply not enough to reduce the micropipe density to below 1 cm −2 . The paper introduces a new power switching device configuration, namely, JFET controlled thyristor (JCT). It is the most promising near term SiC switching device given its high power potential, ease of turn-off, potential for 500°C operation and resulting reduction in cooling requirements. Experimental demonstration of the hybrid JCT is presented with a turn-off measurement of 1 A in less than 100 ns. It is further concluded that in order to take advantage of SiC power devices, high temperature packages and components with double sided attachment need to be developed along with the SiC power devices.

For high-voltage, high-current devices that can be operated at elevated temperatures, silicon carbide (SiC) has been the material of choice. Efforts to produce single-crystal SiC began 30 years ago, but intrinsic problems in growing high-quality single-crystal boules free of micropipe defects—micrometer-scale pinholes created by dislocations—have only recently been overcome. A series of developments in crystal growth have made large-area, high-quality SiC substrates readily available for applications such as high-frequency transmitters and solid-state white lighting. Additional reductions in defects in the active region of devices have been achieved through epitaxial approaches, in which single-crystal layers are grown on the substrate. SiC is now poised as the linchpin to “green energy” that will replace less energy-efficient switches now based on silicon technology.

Micropipes and dislocations in silicon carbide single crystals are revealed by chemical etching. Micropipes are shown to be interconnected with other structural defects and the reason for this is discussed. The Si and C faces are attacked by molten KOH preferentially and isotropically, respectively. The mechanism is discussed in relation to the different surface free energies on the Si and C faces. The revealing of micropipes is more pronounced on the Si face. The hexagonal pattern of micropipes are revealed by rapid etching provided by a large undersaturation at the surface. It is shown that etching from a melt gives a disintegration of the SiC crystal at the micropipe via spiral dissolution which is due to etching near equilibrium conditions. The temperature dependence of the etch rate follows an Arrhenius dependence with an apparent activation energy of about 12-15 kcal mol-1 derived from measuring etch rate and weight loss.

Growth of 6H and 4H-SiC crystals via sublimation technique has been studied in a temperature range of 2300–2450°C. The growth rate strongly depends on temperature distribution, growth pressure, and source to seed distance. The influence of the seed quality on the polytype stability and defect occurrence has been studied. 6H–SiC crystals up to 35 mm in diameter and 20 mm in length have been grown with low micropipe density, 50 cm −2 . Micropipe free areas up to 1 cm 2 have been obtained under optimized growth conditions. The analysis of the results obtained with 4H–SiC growth has shown that this polytype has more narrow window of growth parameters which requires more strict control especially at the initial stage of growth. The seed quality plays an important role for the stability of the polytype and for defect control in the growing crystal.

Silicon carbide devices are being developed for high-power applications. High current operation of these devices is limited by substrate quality. In SiC substrates, micropipes (sometime referred to as micro pores) are a common defect. The presence of even a single micropipe defect intersecting the active region of the device has been shown to produce pre-mature electric breakdown. As a result, the active area of SiC devices usually does not exceed 1 mm 2 . In order to fabricate high-power SiC devices, operating at currents of 100 A and higher, the device area must exceed 10 mm 2 (using reasonable values of current density possible in SiC). Recently, we reported on the fabrication of silicon carbide epitaxial wafers with reduced micropipe density (Rendakova et al., J. Electron Mater. 27 (1998) 292). The best R&D wafers 35 mm and 41 mm in diameter, both 6H and 4H polytypes, have no micropipes. We proposed these wafers as substrates for SiC high-power devices (Chelnokov et al., Diamond and Related Mater. 6 (1997) 1480–1484). In this paper, we report on the fabrication of large area Schottky barriers (up to 8 mm 2 ) based on 4H-SiC layers grown on SiC wafers with reduced micropipe density. Schottky barriers produced on this material demonstrate that large devices can be fabricated without the usual degradation associated with the presence of micropipes.

SiC crystals (1.2–1.5′′ diameter) were grown by the modified Lely technique on seeds with different micropipe densities in order to study the defect generation during seeding and subsequent bulk growth. The micropipe generation is found to be strongly correlated with the occurrence of second phases in SiC like carbon inclusion formation. Model approaches for stable SiC growth conditions, i.e. without inclusions, are discussed. Numerical modeling was performed to reveal the radial and axial temperature gradients of our crucible set-up. Stress formation and micropipe generation are determined to be enhanced in the presence of a large axial temperature gradient.

Silicon carbide single crystals of the 4H-, 6H- and 15R- polytype are grown by using physical vapor transport (PVT). The crystal growth is performed at conditions where the growth chamber is close to thermal equilibrium. Micropipe-free growth of 6H-SiC on both the C- and Si-face of a 6H-SiC seed is demonstrated. 4H/15R bulk material has been grown on 4H-/15R-seeds, respectively. The growth of 4H-/15R-SiC can not yet be stabilized for the entire boule. Micropipe generation is observed in the neighborhood of polytype transitions, where Raman spectroscopy reveals internal stress. Nitrogen donor concentrations and concentrations of the compensation range from 5.9×10 17 to 1.5×10 18 cm −3 and from 3×10 17 to 6×10 17 cm −3 , respectively. The maximum of the electron Hall mobility is about 200 cm 2 (Vs) −1 (6H–SiC) and 300 cm 2 (Vs) −1 (4H- and 15R-SiC).

Experimental results of structural defect visualization and oxide breakdown in SiC wafers after thermal oxidation is presented. The long-range influence of bulk defects on the oxidation behavior of the C-face of SiC wafers, as well as the delineation of polishing marks on the Si face, after oxidation, is presented. High field measurements on a large number of MOS-capacitor structures, fabricated on the SiC wafers, indicates that while oxide breakdown was never observed to occur in the region atop a micropipe, it generally coincided with the edge of bulk defects (within the SiC wafer) under the gate contact.

This paper presents an overview of SiC power devices. The progress in P–N diode development is described. It is found that in order to develop high voltage, high current diodes, it is critical to reduce dislocation density below 103 cm−2, and increase substrate doping of N+ 4H–SiC above 1019 cm−3. It is simply not enough to reduce the micropipe density to below 1 cm−2. The paper introduces a new power switching device configuration, namely, JFET Controlled Thyristor (JCT). It is the most promising near term SiC switching device given its high power potential, ease of turn-off, potential for 500 °C operation and resulting reduction in cooling requirements. It is further concluded that in order to take advantage of SiC power devices, high temperature packages and components with double sided attachment need to be developed along with the SiC power devices. The progress in power MOSFET development is summarized and the phenomenon of “step-bunching” is introduced. This mechanism is responsible for causing surface roughness which results in low electron inversion layer mobility. It is found that by avoiding step-bunching, surface electron mobility of about 55 cm2 V−1 s−1 can be obtained in 6H–SiC planar MOSFETs. The cause for low surface electron mobility in 4H–SiC is still an unknown.