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Logical gates have been used in implementation of logic sequential and combinational circuits especially in computers, DSPs and microprocessors. They are mostly fabricated based on CMOS technology that provides a few nano-seconds of delay for each digital gate. Due to limitations in more scaling CMOS transistors and cause of short channel effects, some engineers and researchers believe that there is a huge demand for new devices and fabrication technologies to produce faster logic gates. In this paper, a new architecture for NAND gate is presented which operates based on mechanical resonance of a network of weakly coupled resonators that resonate in radio frequencies. This design is achieved by employing the associative memory property of Hopfield neural networks and the theory of weakly coupled resonators. The main advantage of the proposed design is in its capability to reach out delay times of the order of 1 nano-seconds or even less. One solution to decrease the delay time can be increasing the resonance frequency of resonators which are processing elements of resonators network. In this paper just the new idea of implementation NAND gate based on weakly coupled RF MEMS resonators is presented and evaluated. Other criteria like gate power consumption, effects of temperature, fan in, fan out and noise margin are not discussed. Regarding the rapid growth in MEMS technology, resonators with super high frequency (SHF 3–30 GHz) are now available and those with Extremely High frequency (EHF 30–300 GHz) will soon be in market which enables the presented design to achieve higher speeds. In addition, mechanical resonators are more fault tolerant than CMOS circuits when utilized in harsh environments which exposed to ionic beams or electron beam radiations. In space applications, the satellite and payload are exposed to huge bombardments of space electrons and ions beams. So, the proposed NAND gate can be a good solution for enhancing reliability of devices and systems exposed to space radiations. [ABSTRACT FROM AUTHOR]

In this work, a complementary metal‐oxide‐semiconductor (CMOS) based leaky‐integrate and fire neuron has been proposed and investigated for neuromorphic applications. The neuron has been designed in Cadence Virtuoso and validated experimentally. It has been observed that the neuron consumes a maximum energy of 68.87 fJ/spike. The response of the neuron to excitatory as well as inhibitory inputs has been studied. To verify the applicability, the proposed neuron has been explored for reconfigurable threshold logic to implement various linearly separable Boolean functions including OR, AND, NOT, NOR, and NAND. Moreover, the threshold tunability of the neuron has also been verified and this property has been exploited to design threshold‐controlled logic gates. Instead of adjusting the weights of the applied inputs, the functionality of such gates can be controlled by changing the threshold of the neuron, simplifying the synaptic architecture of a neural network. Finally, a multilayer network has been designed and the recognition ability of the proposed network for MNIST handwritten digits has been verified with an accuracy of 96.93%. [ABSTRACT FROM AUTHOR]

[Display omitted] New ortho -substituted diarylamines prone to different types of the intramolecular H-bonding (IMHB) were obtained. In-depth NMR, IR and voltammetry study allowed selecting the amine that demonstrates stable reversible switching of the IMHB bond under the external stimuli, which can be used for the logic gate construction. [ABSTRACT FROM AUTHOR]

This paper presents a novel circuit technique NSCDH, to construct OR gates with 8 inputs up to 128 inputs and single output, which can be cascaded to further stages. It uses stage isolation technique to provide current free nodal state comparison with the ability to hold circuit at an optimal state, thereby resulting in 44.6% lesser power consumption and 16.1% higher noise immunity at 8 inputs as compared to CDDK (2019) and 24.4% lesser power consumption at 128 inputs as compared to CDDK (2019). Circuit simulation is done using HSpice. Standard BSIM4 90 nm PTM file is used to model NMOS and PMOS transistors. Circuit schematic is made using LT Spice. OR gates built using this technique can be used in many applications as multiplexers, read–write data paths, memories, and adders. [ABSTRACT FROM AUTHOR]

Current-induced domain wall (DW) motion in ferromagnetic nanostructures is an important research area to realize spin-based logic devices. Using micromagnetic simulations, we have designed and demonstrated a NOT gate logic operation via DW chirality flipping in a ferromagnetic nanostructure with an anti-dot. The DW chirality flipping is due to the Walker breakdown occurring at the anti-dot structure. The DW configuration transforms from a transverse DW (TDW) to an anti-vortex DW and back to TDW, however, with opposite chirality when driven by a particular current density. The device is capable of bidirectional operation, wherein the DW driven in both directions undergoes chirality flipping. The DW speed is a critical parameter for the logic operation. The dimensions of the anti-dot govern the DW speed; thus, the successful operation is seen only below the critical anti-dot width. Moreover, the DW needs to travel a certain distance before it can undergo Walker breakdown, making the anti-dot length also a key parameter. Finally, the current density is a pivotal factor in the logic-gate operation. At relatively lower current densities, the DW does not undergo Walker breakdown, whereas it may undergo Walker breakdown with several transformations before it reaches the output at higher current densities. We have shown the window of successful NOT gate logic operation, as a function of anti-dot width, length, and current density. [ABSTRACT FROM AUTHOR]

Electric double layer (EDL) gating is a technique in which ions in an electrolyte modulate the charge transport in an electronic material through electrical field effects. A sub-nanogap capacitor is induced at the interface of electrolyte/semiconductor under the external electrical field and the capacitor has an ultrahigh capacitance density (~µF cm−2). Recently, EDL gating technique, as an interfacial gating, is widely used in two-dimensional (2D) crystals for various sophisticated materials characterization and device applications. This review introduces the EDL-gated transistors based on 2D materials and their applications in the field of bioinspired optoelectronic detection, sensing, logic circuits, and neuromorphic computation. [ABSTRACT FROM AUTHOR]

In this article, a two-dimensional photonic crystal-based XOR gate is designed and simulated. For this purpose, an initial two-dimensional photonic crystal structure is chosen and waveguides are created for inputs and outputs. Then, defect rods are selected so that the obtained outputs are approximately consistent with the XOR gate truth table. After that, we will be looking for the best output so that the highest optical power is created for logic 1 and the lowest power in the logical state of 0. For this reason, the simulation is performed for four defect rods and the output is obtained for different the radius of the rods. Then, using the K-Nearest Neighbors algorithm, which is a machine learning algorithm, the best output for logic 0 and also for logic 1 is obtained. The results show that the designed logic gate has high output power in logic 1 and very low power in the logic 0 state. [ABSTRACT FROM AUTHOR]

The 25 Hz phase sensitive track circuit has different characteristics from ZPW-2000A track circuit. However, during the retrofitting of automatic block and station coding systems, these two track circuits are often used together. The different characteristics of these two track circuits may lead to the failure of logic check at their junction. This paper analyzes the failure of normal release of the yard connection route and the loss of shunting kept in the third approach block section, and introduces the scenario and causes of these faults. It also discusses the solutions of the interlocking system, train control center system, integrated section monitoring system and relay logic check circuit for these failures, which provides reference for engineering design and fault handling in the future. [ABSTRACT FROM AUTHOR]

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In response to the growing demand for wearable devices designed for seamless integration with 3D bio‐surfaces, fiber‐based devices have gained prominence in textile‐based wearable electronics due to their flexibility and unique structure. In particular, though diodes with rectifying properties are crucial for a range of electronic systems, there has been scant reporting on diodes with a fiber structure. This study introduces a fiber‐based flexible ionic diode that exhibits a rectification ratio of 2773 and an output current of 28.2 mA at 3 V. The diode is composed of a double helical Zn‐based fiber anode, a Ti‐based fiber cathode on Au nanoparticle‐based flexible fiber electrodes, and a LiCl hydrogel electrolyte. By modulating the double helical design and the ionic conductivity of the hydrogel, the electrical performance of the diode to achieve varying rectification ratios and output currents can be tailored. Owing to the remarkable flexibility and stability of the fiber electrodes, the fiber‐based ionic diode consistently upholds its rectifying capabilities, even under washing procedures and significant bending deformation. Furthermore, this diode seamlessly integrates into various electronic circuits, including half‐wave rectifiers, capacitor–diode filters, and logic gate systems. [ABSTRACT FROM AUTHOR]

The paper describes the design and implementation of optical data transmission circuits using an innovative approach based on the electro-optic effect in a directional coupler (EODC). Optical multiplexers (MUX), demultiplexers (DEMUX), encoders, decoders, and priority encoders are all included in the proposed circuit design to enable efficient and reliable data transfer. Electro-optic effect in a directional coupler have been analysed theoretically and numerically, including the detailed mathematics of coupled wave theory. The proposed device is made of GaAlAs material produced from a 3μm × 3μm modulator. The appropriate vale of coupling length (Lc), light wavelength, refractive index change (Δn), electric field magnitude and other parameters are considered for an efficient generation of fundamental logic gates. The design process and the simulation results provide in-depth analysis, highlighting the feasibility and utility of our approach in enhancing the performance of optical data transmission devices. [ABSTRACT FROM AUTHOR]

The increasing demand for high-speed, energy-efficient, and miniaturized electronics has led to significant challenges and compromises in the domain of conventional clock-based digital designs, most notably reduced circuit reliability, particularly in mission-critical hardware. At scaled technology nodes, devices are vulnerable to transient or soft errors, such as Single Event Upset (SEU) and Single Event Latch-up (SEL). External radiation, internal electromagnetic interference (EMI), or noise are the primary sources of these errors, which can compromise the circuit functionality. In response to these challenges, the Quasi-Delay-Insensitive (QDI) Null Convention Logic (NCL) asynchronous design paradigm has emerged as a promising alternative, offering advantages such as ultra-low power performance, reduced noise and EMI, and resilience to process, voltage, and temperature variations. Moreover, its unique architecture and insensitivity to timing variations offers a degree of resistance against transient errors; however, it is not entirely resilient. Several resiliency schemes are available to detect and mitigate soft errors in QDI circuits, with approaches based on redundancy proving to be the most effective in ensuring complete resilience across all major QDI implementation paradigms, including NCL, Pre-charge/Weak-charge Half Buffers (PCHB/WCHB), and Sleep Convention Logic (SCL). This research focuses on one such redundancy-based resiliency scheme for QDI NCL circuits, known as the dual-modular redundancy-based NCL (DMR-NCL) architecture, and addresses the absence of formal methods for the verification and analysis of such circuits. A novel methodology has been proposed for formally verifying the correctness of DMR-NCL circuits synthesized from their synchronous counterparts, covering both safety (functional correctness) and liveness (the absence of deadlock). In addition, this research introduces a formal framework for the vulnerability analysis of DMR-NCL circuits against SEU/SEL. To demonstrate the framework's efficacy and scalability, a prototype computer-aided support tool has been developed, which verifies and analyzes multiple DMR-NCL benchmark circuits of varying sizes and complexities. [ABSTRACT FROM AUTHOR]

In the wireless communication technologies of today are used to transfer enormous amounts of digital data frequently between various embedded devices. For avoiding information loss and stopping cybercrimes, data security is regarded as a crucial factor. Modern cryptography encryption techniques are essential for creating secure communication. The Advanced Encryption Standard (AES) is widely regarded as the cryptography field's strongest encryption technique. In AES has three types of keys using that is AES128, AES192, AES256 and blocksize only 128bits. In this paper using AES-256, because it's very secure for valuable information. This research paper describes how the AES algorithm uses a low area, little latency, high-speed FPGA design to secure data. The implementation of the SubBytes and InvSubBytes phases of AES encryption and decryption in this research did not rely on Look-Up Tables (LUTs). Instead, this novel approach employed combinational logical circuits to construct the SubBytes and InvSubBytes transformation. Here analysed AES Logic gates approach reduced area in terms of number of slices LUTs are 6120, slice registers are 226, flip flops are 6120, and bonded IOB are 513 when compared to the LUT. Unwanted delays in this design are reduced because of the removal of LUTs, and a Three Stage pipelining structure is added to enhance the performance of the AES algorithm. AES Logic gates three stage pipeline approach reduced delay up to 60.55ns when compared to Logic gates without pipeline approach. The proposed approach simulated, synthesized Implemented with Virtex-5 FPGA device along with design in Verilog code in XILINX 14.7 Software. [ABSTRACT FROM AUTHOR]

In recent years, reversible logic gates have garnered significant interest because of their potential to decrease energy consumption and meet the growing need for low-power computing systems. Unlike conventional logic gates, reversible logic gates ensure that no information loss happens during computation, allowing for the reversal of the entire computation process. This unique characteristic opens up new avenues for developing energy-efficient digital circuits. This review paper serves as a vital contribution to the field by addressing a noticeable gap in the existing literature regarding reversible logic gates. The study not only comprehensively analyzes the array of reversible logic gates available but also underscores their practical applications and significance. It encompasses a wide variety of reversible logic gates, including Toffoli gates, Fredkin gates, and newer innovations. It is found that Toffoli gates outperformed in terms of gate count and quantum cost reduction, making them a preferred choice for quantum circuit optimization. Additionally, Fredkin gates showed exceptional performance in specific applications, like data swapping and quantum state control. The digital circuits like adders, multiplexers, ALU etc. are successfully designed using reversible gates like HNG, DKG etc. The significant gap this study fills lies in the need for a consolidated and in-depth analysis of the state-of-the-art reversible logic gates and their real-world utility. While prior research has discussed these gates individually, this paper takes a novel approach by offering a holistic assessment of their performance, quantum cost, gate count, and practical applications, thereby presenting a comprehensive resource for researchers, engineers, and designers in the field. This innovative contribution plays a pivotal role in shaping the progress of energy-efficient and quantum computing systems as well as in optimizing VLSI chip designs for various applications, with a particular emphasis on enhancing cryptographic and data processing capabilities. The findings of this review aim to stimulate further research and development in reversible computing, contributing to the advancement of energy-efficient and information-preserving computing systems. [ABSTRACT FROM AUTHOR]

Electronic processors are reaching the physical speed ceiling that heralds the era of optical processors. Multifunctional all-optical logic gates (AOLGs) of massively parallel processing are of great importance for large-scale integrated optical processors with speed far in excess of electronics, while are rather challenging due to limited operation bandwidth and multifunctional integration complexity. Here we for the first time experimentally demonstrate a reconfigurable all-in-one broadband AOLG that achieves nine fundamental Boolean logics in a single configuration, enabled by ultrabroadband (400–4000 nm) plasmon-enhanced thermo-optical nonlinearity (TONL) of liquid-metal Galinstan nanodroplet assemblies (GNAs). Due to the unique heterogeneity (broad-range geometry sizes, morphology, assembly profiles), the prepared GNAs exhibit broadband plasmonic opto-thermal effects (hybridization, local heating, energy transfer, etc.), resulting in a huge nonlinear refractive index under the order of 10−4−10−5 within visual-infrared range. Furthermore, a generalized control-signal light route is proposed for the dynamic TONL modulation of reversible spatial-phase shift, based on which nine logic functions are reconfigurable in one single AOLG configuration. Our work will provide a powerful strategy on large-bandwidth all-optical circuits for high-density data processing in the future. Multifunctional all-optical logic gate (AOLG) with broadband-based massively parallel processing is desirable for high-speed optical processor. Here, authors propose a reconfigurable all-in-one ultra-broadband AOLG with experimentally achieving 9 fundamental Boolean logics in a single configuration. [ABSTRACT FROM AUTHOR]

Organic electrochemical transistors (OECTs) are ideal devices for translating biological signals into electrical readouts and have applications in bioelectronics, biosensing, and neuromorphic computing. Despite their potential, developing programmable and modular methods for living systems to interface with OECTs has proven challenging. Here we describe hybrid OECTs containing the model electroactive bacterium Shewanella oneidensis that enable the transduction of biological computations to electrical responses. Specifically, we fabricated planar p-type OECTs and demonstrated that channel de-doping is driven by extracellular electron transfer (EET) from S. oneidensis. Leveraging this mechanistic understanding and our ability to control EET flux via transcriptional regulation, we used plasmid-based Boolean logic gates to translate biological computation into current changes within the OECT. Finally, we demonstrated EET-driven changes to OECT synaptic plasticity. This work enables fundamental EET studies and OECT-based biosensing and biocomputing systems with genetically controllable and modular design elements. Interfacing living systems with electronics for biosensing and biocomputing applications is challenging. Here, Gao et al. present hybrid transistors with electroactive bacteria capable of extracellular electron transfer, enabling transduction of biological computations to electrical readouts. [ABSTRACT FROM AUTHOR]

RNA plays an indispensable role in mammalian cell functions. Cas13, a class of RNA-guided ribonuclease, is a flexible tool for modifying and regulating coding and non-coding RNAs, with enormous potential for creating new cell functions. However, the lack of control over Cas13 activity has limited its cell engineering capability. Here, we present the CRISTAL (Control of RNA with Inducible SpliT CAs13 Orthologs and Exogenous Ligands) platform. CRISTAL is powered by a collection (10 total) of orthogonal split inducible Cas13 effectors that can be turned ON or OFF via small molecules in multiple cell types, providing precise temporal control. Also, we engineer Cas13 logic circuits that can respond to endogenous signaling and exogenous small molecule inputs. Furthermore, the orthogonality, low leakiness, and high dynamic range of our inducible Cas13d and Cas13b enable the design and construction of a robust incoherent feedforward loop, leading to near-perfect and tunable adaptation response. Finally, using our inducible Cas13 effectors, we achieve simultaneous multiplexed control of multiple genes in vitro and in mice. Together, our CRISTAL design represents a powerful platform for precisely regulating RNA dynamics to advance cell engineering and elucidate RNA biology. The lack of control over Cas13 activity has limited its utility. Here the authors report Control of RNA with Inducible SpliT CAs13 Orthologs and Exogenous Ligands (CRISTAL), controlled by orthogonal split inducible Cas13 effectors that can be turned ON or OFF, providing precise temporal control. [ABSTRACT FROM AUTHOR]

The dual-band polarization-independent all-optical logic gate by coherent absorption effect in an amorphous silicon (a-Si) graphene metasurface is investigated theoretically and numerically. Taking the substrate effect into consideration, the coherent perfect absorption condition of the a-Si graphene metasurface is derived on the basis of the Cartesian multipole method. The coherent nearly perfect absorption of the a-Si graphene metasurface is realized by the interference of multipole moments and the interband transition of monolayer graphene, achieving peak values of 91% and 92% at 894.5 nm and 991.5 nm, respectively. The polarization independence of the coherent absorption is revealed due to the center symmetry of the structure of the a-Si graphene metasurface. The dual-band polarization-independent all-optical XOR and OR logic gates are implemented at 894.5 nm and 991.5 nm by the a-Si graphene metasurface based on the coherent nearly perfect absorption, which has the opportunity to be utilized in all-optical computing, all-optical data processing, and future all-optical networks. [ABSTRACT FROM AUTHOR]

In industrial electronic equipment or communication equipment, a reference clock should be generated for stable operation of the equipment, which requires precise and stable reference frequency generation. As a method for generating this reference frequency, an analog method called PLL (phase locked-loop) has been devised and widely used. However, in order to make a more precise and stable reference frequency simple and economical, a DDS (direct digital synthesizer) has been developed. In this paper, we propose a stable and accurate method to generate a low frequency of the PWM method via pure logic circuit configuration without a microprocessor for digital reference frequency generation. Depending on the electronic communication equipment, the required reference frequency varies from a low frequency to a very high frequency. The reference frequency synthesis required in these frequency bands has been studied in various ways, but in industries such as railways, the low-frequency band based on the DDS method is used. In particular, it is very important to operate without a single operating error or failure in order to obtain information for stopping the train. Therefore, it is necessary to design a pure logic method that excludes a stored program type processor that minimizes the possibility of temporary interruption due to disturbance such as surge or high voltage. Therefore, through this study, the algorithm is implemented so that the duty ratio is output at 50:50, the circuit is configured so that two target frequencies are generated at the same time, and the performance is verified by generating the low-frequency band used for stopping the railway train. It was confirmed that the accuracy and stability were improved compared to the analog method used for stopping the railway train, and it was verified that the frequency resolution was superior to the similar results obtained in the digital frequency synthesis field so far. [ABSTRACT FROM AUTHOR]

In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC. [ABSTRACT FROM AUTHOR]

As transistor footprint scales down to the sub-10 nm regime, the process development for advancing to further technology nodes has encountered slowdowns. Achieving greater functionality within a single chip requires concurrent development at the device, circuit, and system levels. Reconfigurable transistors possess the capability to transform into both n-type and p-type transistors dynamically during operation. This transistor-level reconfigurability enables field-programmable logic circuits with fewer components compared to conventional circuits. However, the reconfigurability requires additional polarity control gates in the transistor and potentially impairs the gain from a smaller footprint. In this paper, we demonstrate a 2D control-gate-free reconfigurable transistor based on direct modulation of out-of-plane conduction in an ambipolar MoTe2 channel. Asymmetric electrostatic gating at the source and drain contacts is employed in the MoTe2 transistor resulting in different Schottky barrier widths at the two contacts. Consequently, the ambipolar conduction is reduced to unipolar conduction, where the current flow direction determines the preferred carrier type and the transistor polarity. Temperature dependence of the transfer characteristics reveals the Schottky barrier-controlled conduction and confirms that the Schottky barrier widths at the top contact are effectively tuned by electrostatic gating. Without the complexity overhead from polarity control gates, control-gate-free reconfigurable transistors promise higher logic density and lower cost in future integrated circuits. [ABSTRACT FROM AUTHOR]

The next generation of high-capacity, multi-task optical informatics requires sophisticated manipulation of multiple degrees of freedom (DoFs) of light, especially when they are coupled in a non-separable way. Vector beam, as a typical non-separable state between the spin and orbital angular momentum DoFs, mathematically akin to entangled qubits, has inspired multifarious theories and applications in both quantum and classical regimes. Although qubit rotation is a vital and ubiquitous operation in quantum informatics, its classical analogue is rarely studied. Here, we demonstrate the logical rotation of vectorial non-separable states via the uniform self-assembled chiral superstructures, with favorable controllability, high compactness and exemption from formidable alignment. Photonic band engineering of such 1D chiral photonic crystal renders the incident-angle-dependent evolution of the spatially-variant polarizations. The logical rotation angle of a non-separable state can be tuned in a wide range over 4π by this single homogeneous device, flexibly providing a set of distinguished logic gates. Potential applications, including angular motion tracking and proof-of-principle logic network, are demonstrated by specific configuration. This work brings important insight into soft matter photonics and present an elegant strategy to harness high-dimensional photonic states. The logical rotation of non-separable states with a large tunable range is demonstrated by the uniformly self-assembled chiral superstructures, which enables a set of logic gates, proof-of-principle logic network, and angular motion tracking. [ABSTRACT FROM AUTHOR]

The basic components of modern electronics are primarily fabricated by using semiconductor material in which the movement of charges can be electrically modulated. For metallic material, however, such modulation is almost impossible because of its field‐shielding characteristics, leading to insensitive response toward applied potentials. In this perspective, how to overcome this limitation of bulk metals (here, gold is taken as a particular example) is demonstrated by reducing the size to the nanoscale and functionalizing these nanogolds with charged molecules. The movement of mobile counterions within gold nanoparticle (AuNP) layers can generate charge gradients that feed back and control the motion of electrons which enables to design and fabricate several important components such as the diode, transistor, logic circuits, memristor, and various chemiresistive sensors. The assembly of AuNP electronic components and sensors gives rise to a new class of nanoparticle‐based "chemoelectronic" logic circuits that can sense, process, and ultimately report various chemical signals. The gas sensors are believed to be the most appropriate candidates for such integration as no solvent/solution is required and therefore, in the end, the combination of AuNP gas sensors and memristors is outlooked to achieve all‐gold‐nanoparticle in‐sensor computing for the development of future artificial olfactory. [ABSTRACT FROM AUTHOR]

The all-optical switching phenomena in the non-linear directional coupler using cross-phase modulation (XPM) effect have been proposed. It is designed to generate an all-optical XOR functionality, considering the XOR logic gates as a basic module the design and analysis of an efficient all-optical 4-bit binary to gray code converter and 4-bit even parity checker circuit is proposed. The design methodology includes the switching of a weak continuous-wave (CW) signal, which is controlled by the combination of two controlled pump signals. In this paper, mathematical analysis of the coupled mode theory associated with optical directional couplers has been discussed. The switching characteristics of XPM effect based All-optical directional couplers have been examined for appropriate values of the controlled pump signals. Appropriate values of extinction ratio and corresponding controlled pump signal levels are investigated for an efficient generation of XOR logic gates. Further, the detailed analysis of layout generation and design aspects of All-optical 4-bit binary to gray code converter and 4-bit even parity checker circuits have been carried out. The proposed methodology is verified by the appropriate simulation results, which include the transmittivity, extinction ratio (Xratio) curve variation and dynamic time domain plot associated with proposed units. [ABSTRACT FROM AUTHOR]

We prove that if a Boolean function essentially depends on at least two variables, then it cannot be implemented by a circuit that consists of unreliable gates with at most two inputs each and is self-correcting with respect to at least some faults of an arbitrary number of gates. In view of the previous results, it suffices to establish this fact for linear functions. [ABSTRACT FROM AUTHOR]

The human brain is arguably the most complex "machine" to ever exist. Its detailed functioning is yet to be fully understood, let alone modelled. Neurological processes have logical signal-processing and biophysical aspects, and both affect the brain's structure, functioning and adaptation. Mathematical approaches based on both information and graph theory have been extensively used in an attempt to approximate its biological functioning, along with Artificial Intelligence frameworks inspired by its logical functioning. In this article, an approach to model some aspects of the brain learning and signal processing is presented, mimicking the metastability and backpropagation found in the real brain while also accounting for neuroplasticity. Several simulations are carried out with this model to demonstrate how dynamic neuroplasticity, neural inhibition and neuron migration can reshape the brain's logical connectivity to synchronise signal processing and obtain certain target latencies. This work showcases the importance of dynamic logical and biophysical remodelling in brain plasticity. Combining mathematical (agents, graph theory, topology and backpropagation) and biomedical ingredients (metastability, neuroplasticity and migration), these preliminary results prove complex brain phenomena can be reproduced—under pertinent simplifications—via affordable computations, which can be construed as a starting point for more ambitiously accurate simulations. [ABSTRACT FROM AUTHOR]

Instead of the current method of transmitting voltage or current signals in electronic circuit operation, light offers an alternative to conventional logic, allowing for the implementation of new logic concepts through interaction with light. This manuscript examines the use of light in implementing new logic concepts as an alternative to traditional logic circuits and as a future technology. This article provides an overview of how to implement logic operations using light rather than voltage or current signals using optoelectronic materials such as 2D materials, metal–oxides, carbon structures, polymers, small molecules, and perovskites. This review covers the various technologies and applications of using light to dope devices, implement logic gates, control logic circuits, and generate light as an output signal. Recent research on logic and the use of light to implement new functions is summarized. This review also highlights the potential of optoelectronic logic for future technological advancements. [ABSTRACT FROM AUTHOR]

Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a digital circuit designer. Most of the times, the designer sacrifices power consumption and chip area to decrease delay for a given technology node. To overcome this problem, we propose the ternary threshold logic gate. We have implemented the proposed gate by combining the threshold logic with the ternary logic. Then, we have constructed basic building blocks of a ternary ALU (as ternary logic gates, comparator, and arithmetic circuits) using the proposed ternary threshold logic gate. We have compared these building blocks and implemented with the proposed gate, with the ones implemented using different technologies. Via simulations, we have shown that the proposed gate may be utilized to decrease delay, power consumption, and chip area of ternary circuits. Thus, the proposed ternary threshold logic gate can be used to decrease delay, power consumption, and chip area of ternary circuits. [ABSTRACT FROM AUTHOR]

A bidirectional logic gate has been designed based on the backhopping phenomenon observed in magnetic tunnel junctions (MTJ) at high bias. The magnetization dynamics of each magnetic layer of the MTJ—having materials and geometry of a standard spin-transfer torque magnetic random access memory device—is calculated using the coupled Landau–Lifshitz–Gilbert equation-based theoretical framework. A circuit design interconnecting the MTJs has been proposed to simulate a two-input NAND gate. The results in both forward and reverse directions agree well with those found from the Boltzmann distribution, thereby demonstrating the equiprobability of all valid states. [ABSTRACT FROM AUTHOR]

Utilizing magnetic tunnel junctions (MTJs) for write/read and fast spin-orbit-torque (SOT)-driven domain-wall (DW) motion for propagation, enables non-volatile logic and majority operations, representing a breakthrough in the implementation of nanoscale DW logic devices. Recently, current-driven DW logic gates have been demonstrated via magnetic imaging, where the Dzyaloshinskii-Moriya interaction (DMI) induces chiral coupling between perpendicular magnetic anisotropy (PMA) regions via an in-plane (IP) oriented region. However, full electrical operation of nanoscale DW logic requires electrical write/read operations and a method to pattern PMA and IP regions compatible with the fabrication of PMA MTJs. Here, we study the use of a Hybrid Free Layer (HFL) concept to combine an MTJ stack with DW motion materials, and He+ ion irradiation to convert the stack from PMA to IP. First, we investigate the free layer thickness dependence of 100-nm diameter HFL-MTJ devices and find an optimal CoFeB thickness, from 7 to 10 Å, providing high tunneling magnetoresistance (TMR) readout and efficient spin-transfer torque (STT) writing. We then show that high DMI materials, like Pt/Co, can be integrated into an MTJ stack via interlayer exchange coupling with the CoFeB free layer. In this design, DMI values suitable for SOT-driven DW motion are measured by asymmetric bubble expansion. Finally, we demonstrate that He+ irradiation reliably converts the coupled free layers from PMA to IP. These findings offer a path toward the integration of fully electrically controlled DW logic circuits. [ABSTRACT FROM AUTHOR]

As an emerging nanodevice, Quantum-dot cellular automata (QCA) is a hopeful candidate for conventional complementary metal oxide semiconductor devices. XOR, one of the most vital gates, occupies a significant positon in digital logic circuits. In order to improve the property performance of XOR, a novel five-input majority gate is put forward first. Then, an efficient XOR employing a NAND-NOR-Inverter (NNI) and the proposed five-input majority voter is realized in the paper. Compared with previous counterparts based on gates, the proposed design requires fewer cells, occupies less area, and consumes less average energy consumption. Specifically, it improves by 11.11% in cell count, 2.11% in area, and 9.51% (1.5Ek) in energy consumption when compared to the state-of-the-art design. The clock delay of the XOR in the article keeps the same with the minimum of them. Additionally, the proposed design has the lowest QCA cost, including area-delay cost, QCA-specific cost, and energy-delay cost. Moreover, the design is coplanar, without any crossing types. All these make it an outstanding design. To demonstrate its practicality, n-bit parity generators using the proposed XOR are implemented. The novel 4-bit parity generator excels in cell count, area, and average energy dissipation, achieving optimization of up to 10.6%, 6.0%, and 38.6% (0.5Ek), respectively, compared to previous optimum values. The significance of these optimization results becomes more pronounced as the bit of parity generators increases, indicating a promising future for constructing complex circuits. [ABSTRACT FROM AUTHOR]

The luminescence color of molecule‐based photoactive materials is the key to the applications in lighting and optical communication. Realizing continuous regulation of emission color in molecular systems is highly desirable but still remains a challenge due to the individual emission band of purely organic molecules. Herein, a novel alloy strategy based on molecular co‐crystals is reported. By adjusting the molar ratio of pyrene (Py) and fluorathene (Flu), three types of molecular co‐crystal alloys (MCAs) assemblies are prepared involving Py‐Flu‐OFN‐x%, Py‐Flu‐TFP‐x%, Py‐Flu‐TCNB‐x%. Multiple energy level structure and Förster resonance energy transfer (FRET) process endow materials with tunable full‐spectra emission color in visible region. Impressively, these MCAs and co‐crystals can be successfully applied to low optical loss waveguide and optical logic gate by virtue of all‐color luminescence from blue across green to red, together with smooth surface of one‐dimensional microrods, which show promising applications as continuous light emitters for advance photonics applications. [ABSTRACT FROM AUTHOR]

Recently, many lead‐free metal halides with diverse structures and highly efficient emission have been reported. However, their poor stability and single‐mode emission color severely limit their applications. Herein, three homologous Sb3+‐doped zero‐dimensional (0D) air‐stable Sn(IV)‐based metal halides with different crystal structures were developed by inserting a single organic ligand into SnCl4 lattice, which brings different optical properties. Under photoexcitation, (C25H22P)SnCl5@Sb·CH4O (Sb3+−1) does not emit light, (C25H22P)2SnCl6@Sb‐α (Sb3+−2α) shines bright yellow emission with a photoluminescence quantum yield (PLQY) of 92%, and (C25H22P)2SnCl6@Sb‐β (Sb3+−2β) exhibits intense red emission with a PLQY of 78%. The above three compounds show quite different optical properties should be due to their different crystal structures and the lattice distortions. Particularly, Sb3+−1 can be successfully converted into Sb3+−2α under the treatment of C25H22PCl solution, accompanied by a transition from nonemission to efficient yellow emission, serving as a "turn‐on" photoluminescence (PL) switching. Parallelly, a reversible structure conversion between Sb3+−2α and Sb3+−2β was witnessed after dichloromethane or volatilization treatment, accompanied by yellow and red emission switching. Thereby, a triple‐mode tunable PL switching of off–onI–onII can be constructed in Sb3+‐doped Sn(IV)‐based compounds. Finally, we demonstrated the as‐synthesized compounds in fluorescent anticounterfeiting, information encryption, and optical logic gates. [ABSTRACT FROM AUTHOR]

The ZDJ9 AC five-wire switch control circuits exhibit the phenomena of arcing, burning, and oxidation of the first and second groups of strengthening contacts of the 2DQJ relays, resulting in poor contact of the contacts. Due to the fact that the first group of front contacts and the second group of rear contacts of 2DQJ relays are shared contacts, oxidation of these contacts can lead to loss of indication of a switch ; at the same time, there is a risk of instantaneous starting current striking and damaging outdoor diodes, which can also lead to loss of indication of a switch. The principle of the switch control circuits is analyzed, the circuit logic is adjusted, and the ZDJ9 AC five-wire switch control circuits are optimized to avoid loss of switch indication failure and improve the overall reliability of the switch equipment. [ABSTRACT FROM AUTHOR]

We present an innovative method harnessing multistability within a diode-pumped erbium-doped fiber laser to construct logic gates. Our approach involves manipulating the intensity of external noise to regulate the probability of transitioning among four concurrent attractors. In this manner, we facilitate the realization of OR, AND, NOR, and NAND logic operations, aligning with the coexisting period-1, period-3, period-4, and period-5 orbits. Employing detrended fluctuation analysis, we establish equilibrium in the probability distributions of these states. The obtained results denote a substantial advancement in the field of optical logic gate development, representing a pivotal stride toward the seamless integration of an all-optical logic gate within laser oscillator-based systems. [ABSTRACT FROM AUTHOR]

Coherent perfect absorption (CPA) has been studied in various fields, such as metasurface, photonics, and acoustics, because of its ability to perfectly absorb light at a specific wavelength. However, the narrow bandwidth of CPA makes its application to on-chip photonics challenging. This limitation can be overcome by using a broadband resonator. Here, we demonstrate the coherent perfect loss (CPL) with respect to a single and broadband resonator at photonic crystal nanobeam. By using the finite element method, both cases of the CPL were simulated and optimized for the single and broadband resonators. In the optimized structure, a CPL occurs for both resonators. These results confirm that the perfect loss region for the broadband resonator is wider than that for the single resonator. These results are experimentally verified by fabricating both cases of CPL cases on a silicon-on-insulator by using electron beam lithography. An almost perfect loss of more than 95 % is observed for both single and broadband CPLs. Furthermore, the almost perfect loss region at the broadband resonator broadens more than that at the single resonator. The optimized structure for CPL has the potential for easy applications to on-chip photonics, such as optical switches, modulators, sensors, and logic gates. [ABSTRACT FROM AUTHOR]

Unconventional functions, including activation functions and power functions, are extremely hard-to-realize primarily due to the difficulty in arriving at the hierarchical design. The hierarchical design allows the synthesis tool to map the functionality with that of standard cells employed through the regular ASIC synthesis flow. For conventional functions, the hierarchical design is structured and then supplied to the synthesis flow, whereas, for unconventional functions, the same method is not reliable, since the current synthesis method does not offer any design-space exploration scheme to arrive at an easy-to-realize design entity. The unconventional functions either take a long synthesis run-time or additional efforts are spent in restructuring the hierarchical design for the desired function to synthesizable ones. Cartesian genetic programing (CGP) allows to not only incorporate custom logic gates for synthesizing the hierarchical design but also aids in the design-space exploration for the targeted function through the custom gates. The CGP configuration evolves difficult-to-realize complex functions with multiple solutions, and filtering through desired Pareto-optimal requirements offers a unique hierarchical design. Incorporating CGP-derived hierarchical designs into the traditional synthesis flow is instrumental for implementing and evaluating higher-order designs comprising nonlinear functional constructs. Six activation functions and power functions that fall in the category of unconventional functions are realized by the CGP method using custom cells to demonstrate the capability. Further, the hierarchical design of these unconventional functions is flattened and compared with the same function that is directly synthesized using basic gates. The CGP-derived synthesis method reports 3× less synthesis time for realizing the complex functions at the hierarchical level compared to the synthesis using basic gate cells. Hardware characteristics and error metrics are also investigated for the CGP realized complex functions and are made freely available for further usage to the research and designers' community. [ABSTRACT FROM AUTHOR]

Encoded nanostructures afford an ideal platform carrying multi‐channel signal components for multiplexed assay and information security. However, with the demand on exclusivity and reproducibility of coding signals, precise control on the structure and composition of nanomaterials featuring fully distinguishable signals remains challenging. By using the multiplexing capability of mass spectrometry (MS) and spatial addressability of DNA origami nanostructures, we herein propose a quality control methodology for constructing mass‐encoded nanodevices (namely MNTs‐TDOFs) in the scaffold of compartmented tetrahedral DNA origami frames (TDOFs), in which the arrangement and stoichiometry of four types of mass nanotags (MNTs) can be finely regulated and customized to generate characteristic MS patterns. The programmability of combinatorial MNTs and orthogonality of individual compartments allows further evolution of MNTs‐TDOFs to static tagging agents and dynamic nanoprobes for labeling and sensing of multiple targets. More importantly, structure control at single TDOF level ensures the constancy of prescribed MS outputs, by which a high‐capacity coding system was established for secure information encryption and decryption. In addition to the multiplexed outputs in parallel, the nanodevices could also map logic circuits with interconnected complexity and logic events of c‐Met recognition and dimerization on cell surface for signaling regulation by MS interrogation. [ABSTRACT FROM AUTHOR]

Nano and microfluidic technologies have shown great promise in the development of controlled drug delivery systems and the creation of microfluidic devices with logic-like functionalities. Here, we focused on investigating a droplet-based logic gate that can be used for automating medical diagnostic assays. This logic gate uses viscoelastic fluids, which are particularly relevant since bio-fluids exhibit viscoelastic properties. The operation of the logic gate is determined by evaluating various parameters, including the Weissenberg number, the Capillary number, and geometric factors. To effectively classify the logic gates operational conditions, we employed a deep learning classification to develop a reduced-order model. This approach accelerates the prediction of operating conditions, eliminating the need for complex simulations. Moreover, the deep learning model allows for the combination of different AND/OR branches, further enhancing the versatility of the logic gate. We also found that non-operating regions, where the logic gate does not function properly, can be transformed into operational regions by applying an external force. By utilizing an electrical induction technique, we demonstrated that the application of an electric field can repel or attract droplets, thereby improving the performance of the logic gate. Overall, our research shows the potential of the droplet-based logic gates in the field of medical diagnostics. The integration of deep learning classification algorithms enables rapid evaluation of operational conditions and facilitates the design of complex logic circuits. Additionally, the introduction of external forces and electrical induction techniques opens up new possibilities for enhancing the functionality and reliability of these logic gates. [ABSTRACT FROM AUTHOR]

Reconfigurable logic‐in‐memory device, albeit a promising hardware platform for constructing parallel computing architectures, still suffers from high power‐consumption and low area‐efficiency arising from the circuit redundancy in silicon (Si) based technical path. 2D materials are identified as potential building blocks to significantly reduce the circuit footprints with outstanding power‐efficiency, owing to their atomically thin nature and unique electronic properties. However, the present 2D logic devices are primarily based on single channel materials with homogeneous transport polarities, limiting the device reconfigurability for multi‐functional applications. Here, 2D p–n junction based dual‐gate Gaussian‐type transistors for simplified reconfigurable logic circuits are reported. All fundamental Boolean logic operators are implemented in a single device with electrically driven reconfigurability, giving rise to an ultra‐low transistor consumption down to 13% of the traditional circuits. The device is also demonstrated as a reliable image processing unit for various computing tasks (pixel processing, comparing, and ciphering) by executing the corresponding logic operations. Moreover, in situ memory of the Boolean logics is achieved by engineering the dielectric properties of the transistor without compromising its reconfigurability. These findings provide a potential approach to achieving reconfigurable logic‐in‐memory operations at the hardware level, with significant implications for the advancement of parallel computing. [ABSTRACT FROM AUTHOR]

Ultrasensitive photodetectors with polarization angle recognition have broad applications in both civilian and military domains. The emerging 2D materials with in‐plane anisotropy offer promising platforms for realizing these applications, owing to their intriguing properties. However, the lack of an effective photoconductivity gain mechanism and the low photocurrent anisotropic ratio have made it challenging to achieve digital output of polarization information. Herein, a gate voltage‐dependent phototransistor based on ReSe2/WSe2 out‐of‐plane heterostructure is proposed. Attributed to sophisticated band alignment engineering, the device exhibits remarkable photoresponse characteristics and polarization sensitivity, including an outstanding responsivity of 2.29 × 104 A W−1, an extraordinary detectivity of 5.65 × 1013 Jones, a prompt rise/decay time of 197/182 µs, as well as a high photocurrent anisotropic ratio of 10.9. Based on these features, the device is integrated into a polarization recognition system, which accurately identifies the polarization angle of the incident light and displays it. These results demonstrate the strong potential of the ReSe2/WSe2 device for future applications in polarization optical communication and logic circuits. [ABSTRACT FROM AUTHOR]

This paper proposes a 12-bit SAR ADC capable of calibrating a split capacitor using a binary search technique for bio-signal processing applications. The proposed SAR ADC employs a calibration logic circuit to calibrate a split capacitor vulnerable to process variations and mismatches. The proposed foreground calibration process involves four iterations through the binary search algorithm. In this manner, the calibration speed can be increased by up to 3.75 times compared with that of the linear search calibration. The proposed SAR ADC was implemented with a CMOS 28 nm 1-poly 8-metal process. The effective layout, excluding bonding pads, occupied 939 × 450 μ m. Measurement results illustrated a power consumption of 30.7 μ W (analog power: 16.1 μ W and digital power: 14.6 μ W), INL/DNL of −1.8/1.7 LSB, and −0.7/0.7 LSB, respectively, ENoB of 10.3-bit, and a FoM of 53.7 fJ/step. [ABSTRACT FROM AUTHOR]

Detection of correct oxidation state of a metal ion is important to understand its speciation and redox properties. Some of rhodamine derivatives can identify Al3+, Cr3+ and Fe3+ as the trivalent cations. We have synthesized a rhodamine derivative, HL‐qui, from the reaction of N‐(rhodamine‐6G)lactam‐ethylenediamine with quinoline‐2‐carboxaldehyde for the colorimetric as well as fluorogenic detection of all of metal ions with +3 oxidation state such as Al3+, Cr3+, Fe3+, Ga3+, In3+, Tl3+ and Gd3+. In the presence of these trivalent cations, colorless and nonfluorescent HL‐qui turns pink and strongly fluorescent in HEPES buffer (10 mM) in H2O/ethanol=1/9 (v/v) (pH 7.4) as its spirolactam ring gets open to show the changes in color and fluorescence properties. High sensitivity of the probe towards the cations is reflected from the limit of detection values that are in nM range. To the best of our knowledge, there is no such report where fluorescence sensing has been utilized to determine oxidation state. This multi‐ion sensing feature has been used for fabrication of multi input‐output based logic circuit using Boolean algebraic method. It has been used in imaging of metal ions in living cell (L6 cells). [ABSTRACT FROM AUTHOR]

The low quantum yields (QY) of carbon quantum dots (CQDs) not only limit their sensitivity as sensors, but also hinder their application in fluorescent anti-counterfeiting materials. To develop highly fluorescent CQDs, several factors, like a large conjugated double bond system, a rigid plane structure and electron-donating substituent group incorporation on the aromatic ring need to be considered. With this in mind, herein, highly fluorescent nitrogen-doped CQDs (N-CQDs) were successfully fabricated by a solvothermal method using ammonia, citric acid and phloroglucinol as precursors. The sensing platform based on the obtained N-CQDs was constructed to determine Fe3+ and ascorbic acid (AA) via the "on–off–on" fluorescence principle. The fluorescence of the N-CQDs was effectively quenched upon addition of Fe3+, and then, restored by AA. The detection limits for Fe3+ and AA were determined to be 0.28 μM and 0.81 μM within the respective ranges of 1–10 μM and 30–90 μM. It is worth noting that the proposed strategy was successfully applied to monitor AA in fruit samples with satisfactory results. In addition, we successfully applied N-CQDs to information anti-counterfeiting and molecular logic gate operations, which confirmed their great potential application prospects. [ABSTRACT FROM AUTHOR]

A poly (3,6‐bis(thiophen‐2‐yl)−2,5‐bis(2‐decyltetradecyl)−2,5‐dihydropyrrolo[3,4‐c]pyrrole‐1,4‐dione‐co‐(2,3‐bis(phenyl)acrylonitrile)) (PDPADPP) copolymer, composed of diketopyrrolopyrrole (DPP) and a cyano (nitrile) group with a vinylene spacer linking two benzene rings, is synthesized via a palladium‐catalyzed Suzuki coupling reaction. The electrical performance of PDPADPP in organic field‐effect transistors (OFETs) and circuits is investigated. The OFETs based on PDPADPP exhibit typical ambipolar transport characteristics, with the as‐cast OFETs demonstrating low field‐effect hole and electron mobility values of 0.016 and 0.004 cm2 V−1 s−1, respectively. However, after thermal annealing at 240 °C, the OFETs exhibit improved transport characteristics with highly balanced ambipolar transport, showing average hole and electron mobility values of 0.065 and 0.116 cm2 V−1 s−1, respectively. To verify the application of the PDPADPP OFETs in high‐voltage logic circuits, compact modeling using the industry‐standard small‐signal Berkeley short‐channel IGFET model (BSIM) is performed, and the logic application characteristics are evaluated. The circuit simulation results demonstrate excellent logic application performance of the PDPADPP‐based ambipolar transistor and illustrate that the device annealed at 240 °C exhibits ideal circuit characteristics. [ABSTRACT FROM AUTHOR]

The arithmetic and logic unit (ALU) is a key element of complex circuits and an intrinsic part of the most widely recognized complex circuits in digital signal processing. Also, recent attention has been brought to reversible logic and quantum-dot cellular automata (QCA) because of their intrinsic capacity to decrease energy dissipation, which is a crucial need for low-power digital circuits. QCA will be the preferred technology for developing the subsequent generation of digital systems. These technologies played a substantial role in the design of the ALU for operations such as multiplication, subtraction, and division. In developing reversible logic and QCA technologies, the ALU is frequently studied as a central unit. Implementing an efficient ALU with low quantum cost and a small number of cells based on an efficient reversible block can solve all previous issues. Therefore, this research constructs a Feynman gate, a Fredkin gate, and full adder circuits using reversible logic and QCA technology. Using all of the specified circuits, a 20-operation ALU is constructed. The power consumption of the proposed ALU under various energy ranges demonstrated significant improvements over earlier designs. [ABSTRACT FROM AUTHOR]

We consider the problem of finding nearly optimal solutions of optimization problems with random objective functions. Such problems arise widely in the theory of random graphs, theoretical computer science, and statistical physics. Two concrete problems we consider are (a) optimizing the Hamiltonian of a spherical or Ising p-spin glass model and (b) finding a large independent set in a sparse Erd\H os-Renyi graph. The following families of algorithms are considered: (a) low-degree polynomials of the input-a general framework that captures many prior algorithms; (b) low-depth Boolean circuits; (c) the Langevin dynamics algorithm, a canonical Monte Carlo analogue of the gradient descent algorithm. We show that these families of algorithms cannot have high success probability. For the case of Boolean circuits, our results improve the state-of-the-art bounds known in circuit complexity theory (although we consider the search problem as opposed to the decision problem). Our proof uses the fact that these models are known to exhibit a variant of the overlap gap property (OGP) of near-optimal solutions. Specifically, for both models, every two solutions whose objectives are above a certain threshold are either close to or far from each other. The crux of our proof is that the classes of algorithms we consider exhibit a form of stability (noise-insensitivity): a small perturbation of the input induces a small perturbation of the output. We show by an interpolation argument that stable algorithms cannot overcome the OGP barrier. The stability of Langevin dynamics is an immediate consequence of the well-posedness of stochastic differential equations. The stability of low-degree polynomials and Boolean circuits is established using tools from Gaussian and Boolean analysis-namely hypercontractivity and total influence, as well as a novel lower bound for random walks avoiding certain subsets, which we expect to be of independent interest. In the case of Boolean circuits, the result also makes use of Linial--Mansour--Nisan's classical theorem. Our techniques apply more broadly to low influence functions, and we expect that they may apply more generally. [ABSTRACT FROM AUTHOR]

Logic gates are an indispensable part of digital circuits, and therefore such devices with fast operating speeds and simple designs are vital for all kinds of electronic applications. This paper proposes simple Y‐shaped designs of all‐optical AND, OR, and NOT logic gates in two dimensions that are operational in both TE and TM modes. These gates are designed using silicon slab waveguides, which makes them relatively easy to fabricate. The logic gates are designed, analyzed, and optimized at 1.55 µm using the finite difference time domain method. The truth tables of the proposed all‐optical logic gates are realized for every input case. The propagation delay time is determined to be of the order of femtoseconds (10−15 s), which is very fast compared to the response time of the currently reported all‐optical logic gates (10−9 ‐ 10−12 s). [ABSTRACT FROM AUTHOR]

Optical computers, leveraging the advantages of light characteristics, hold the potential to outperform electronic computers significantly. The role of all‐optical logic gates is pivotal in realizing such high‐performance computing systems. This research introduces a streamlined design for an all‐optical NOR logic gate utilizing a semiconductor optical amplifier. The proposed gate operates at a remarkable data rate of 40 Gbps, achieving an excellent extinction ratio of 20.285 dB. Notably, the design exhibits very low dispersion (−0.029 × 10+006 ps/nm) and an impressively low bit error rate of 4.27 × 10−26. [ABSTRACT FROM AUTHOR]

Hybrid magnetic tunnel junction (MTJ)/CMOS circuits based on the computation-in-memory (CIM) architecture are contemplated as the future generation of digital integrated circuits. It overcomes the limitations of von-Neumann architecture by offering solutions to problems such as memory wall and standby power dissipation. In this work, we have developed hybrid logic gates, such as AND/NAND, OR/NOR, and XOR/XNOR, for CIM architecture by integrating three terminal spin-Hall effect assisted spin transfer torque (SHE + STT) MTJs with standard CMOS. To write the MTJs an auto-write-stopping (AWS) circuit is adopted, whereas to perform the logic operations and produce the corresponding outputs, an improved sense amplifier circuit (ISA) is employed. All the hybrid logic gates are investigated for key performance indicators such as power, delay, device count, and power delay product (PDP). The results are compared with their conventional counterparts. The comparison reveals that the ISA + AWS-based hybrid gates dissipate 50.52% lower total power. The worst-case read delay of ISA + AWS hybrid AND/NAND, OR/NOR, and XOR/XNOR gates are 27.41%, 13.4%, and 21.28% lower. Meanwhile, the reduction of read PDP (write PDP) is 47.64% (37.09%), 25.78% (36.29%), and 39.31% (35.48%) observed with ISA + AWS hybrid AND/NAND, OR/NOR, and XOR/XNOR gates in comparison with the conventional counterparts. Hence the ISA + AWS gates are superior in terms of total power dissipation, worst read delay, and read/write PDP. Further, we have conducted Monte-Carlo simulations on all the logic circuits to study the parameter variations during fabrication. [ABSTRACT FROM AUTHOR]