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A 12-Bit SAR ADC with Binary Search Calibration Algorithm for a Split Capacitor.

Authors :
Yang, Je-I
Yoon, Kwang Sub
Lim, Hongki
Source :
Electronics (2079-9292); Jan2024, Vol. 13 Issue 2, p414, 15p
Publication Year :
2024

Abstract

This paper proposes a 12-bit SAR ADC capable of calibrating a split capacitor using a binary search technique for bio-signal processing applications. The proposed SAR ADC employs a calibration logic circuit to calibrate a split capacitor vulnerable to process variations and mismatches. The proposed foreground calibration process involves four iterations through the binary search algorithm. In this manner, the calibration speed can be increased by up to 3.75 times compared with that of the linear search calibration. The proposed SAR ADC was implemented with a CMOS 28 nm 1-poly 8-metal process. The effective layout, excluding bonding pads, occupied 939 × 450 μ m. Measurement results illustrated a power consumption of 30.7 μ W (analog power: 16.1 μ W and digital power: 14.6 μ W), INL/DNL of −1.8/1.7 LSB, and −0.7/0.7 LSB, respectively, ENoB of 10.3-bit, and a FoM of 53.7 fJ/step. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
20799292
Volume :
13
Issue :
2
Database :
Complementary Index
Journal :
Electronics (2079-9292)
Publication Type :
Academic Journal
Accession number :
175059108
Full Text :
https://doi.org/10.3390/electronics13020414