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Memory-centric computing with on-chip non-volatile memories provides unique opportunities for native and local information processing in an energy-efficient manner. Design and modeling methodology based on resistive random access memory (RRAM) is presented in this paper. A hierarchical RRAM SPICE model having different levels of physics realism is described, where the incorporated stochasticity provides a more accurate representation of RRAM operations. Three in-memory operation schemes are developed and experimentally verified for reconfigurable in-memory logic, using RRAM built in 3-D vertical structure (i.e., 3-D RRAM). As a case study for RRAM-centric computing systems, we evaluate the Please note that there were discrepancies between the accepted pdf [TCAS_R1_combined.pdf] and the [TCAS_RRAM-centric computing_hli_FINAL_submit.docx] in the lines 12 and 70. We have followed [TCAS_RRAM-centric computing_hli_FINAL_submit.docx]. use of 3-D RRAMs for a language recognition system using the hyperdimensional (HD) computing model. Utilizing the inherent properties of 3-D RRAM, we demonstrate, using fabricated 3-D RRAM integrated with FinFET, the essential kernels for HD operations: multiplication, addition, and permutation (MAP). RRAM-centric HD systems exhibit strong resilience to hard errors induced by RRAM endurance failures, making a promising case for using various types of RRAM for memory-centric HD systems.

We proposed an ultrafast accelerated retention test methodology for resistive random access memory (RRAM) using micro thermal stage (MTS). For accelerated retention test using chuck heating, the two major factors that limit the test speed are the attainable temperature range and thermal time constant. To extend these limits, we built MTS with extended temperature range (~800 °C) and short thermal time constant ( $\sim 10\mu \text{s}$ ). Using high resistance state retention failure of HfOx-based RRAM as an example, we demonstrated that the proposed methodology can reduce accelerated retention test time to

Emerging non-volatile memory technologies are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, material engineering, three-dimension (3D) integration, and bottom-up fabrication. The device operation, physical mechanisms for resistive switching, reliability metrics, and memory cell selector candidates are summarized from the recent advancement in both industry and academia. Options for 3D memory array architectures are presented for the mass storage application. Finally, the potential application of bottom-up fabrication approaches for effective manufacturing is introduced.

Conducting bridge random access memory (CBRAM) is one of the most promising candidates for future nonvolatile memories. It is important to understand the scalability and retention of CBRAM cells to realize better memory performance. Here, we directly observe the switching dynamics of Cu tip/SiO2/W cells with various active electrode sizes using in situ transmission electron microscopy. Conducting filaments (CFs) grow from the active electrode (Cu tip) to inert electrode (W) during the SET operations. The size of the Cu tip affects the electric-field distribution, the amount of the cation injection into electrolyte, and the dimension of the CF. This study provides helpful understanding on the relationship between power consumption and retention of CBRAM cells. We also construct a theoretical model to explain the electrode-size-dependent CF growth in SET operations, showing good agreement with our experimental results.

We present a robust method to fabricate a polydimethylsiloxane (PDMS) microfluidic device with critical channel features located near the periphery. The fabricated device has a window cutout, allowing close placement and integration of the channel with solid state circuits and devices. The flow characteristics of the fabricated device are shown to closely follow that of theoretical behavior, making it an appropriate alternative to a monolithic, cast-molded device. As an illustration of the use of this method, a novel integrated microfluidic-electronic system is demonstrated with the microfluidic channel bonded directly onto the surface of an integrated circuit while leaving access to probe pads on the chip's surface. This fabrication process has important implications in furthering the development of next generation microfluidic-based lab on chip systems.

As the physical dimensions of a transistor gate continue to shrink to a few atoms, performance can be increasingly determined by the limited electronic density of states (DOS) in the gate and the gate quantum capacitance (CQ). We demonstrate the impact of gate CQ and the dimensionality of the gate electrode on the performance of nanoscale transistors through analytical electrostatics modeling. For low-dimensional gates, the gate charge can limit the channel charge, and the transfer characteristics of the device become dependent on the gate DOS. We experimentally observe for the first time, room-temperature gate quantization features in the transfer characteristics of single-walled carbon nanotube (CNT)-gated ultrathin silicon-on-insulator (SOI) channel transistors; features which can be attributed to the Van Hove singularities in the one-dimensional DOS of the CNT gate. In addition to being an important aspect of future transistor design, potential applications of this phenomenon include multilevel transistors with suitable transfer characteristics obtained via engineered gate DOS.

Modern cognitive computing workloads require computing systems tailored to the applications, where the underlying hardware fabrics should naturally match the characteristics of learning algorithms and compute kernels. With emerging memory technologies (e.g., resistive RAM (RRAM), magnetic RAM (MRAM)), we design neuro-inspired computing systems that exploit technology characteristics such as rich device physics, circuit architecture, and integration capabilities with CMOS and beyond-CMOS technologies. Our methodology is built upon a combination of experimental characterization, cross-stack modeling, and system integration, illustrated by case studies for neural networks and highdimensional (HD) computing. Finally, we discuss the prospects of heterogeneous learning machines that emphasize the integration of compute kernels and learning algorithms, as well as the integration of emerging nanotechnologies.

The recent surge of interest in brain-inspired computing and power-efficient electronics has dramatically bolstered development of computation and communication using neuron-like spiking signals. Devices that can produce rapid and energy-efficient spiking could significantly advance these applications. Here we demonstrate direct current or voltage-driven periodic spiking with sub-20 ns pulse widths from a single device composed of a thin VO

We demonstrate single crystal growth of wafer-scale hexagonal boron nitride (hBN), an insulating atomic thin monolayer, on high-symmetry index surface plane Cu(111). The unidirectional epitaxial growth is guaranteed by large binding energy difference, ~0.23 eV, between A- and B-steps edges on Cu(111) docking with B6N7 clusters, confirmed by density functional theory calculations.

Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS 2 p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS 2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS 2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of ~106, a S.S. of ~97 mV/dec., and nearly zero DIBL.

We present novel growth of the two-dimensional (2D) semiconductor MoS 2 directly on oxide/Si sidewalls as deep as $3\ \mu \mathrm{m}$ , demonstrating the first vertical 2D transistors with $I_{\mathrm{o}\mathrm{n}}/I_{\mathrm{off}} > 10^{7}$ and $I_{\mathrm{o}\mathrm{n}}\approx 30\mu \mathrm{A}/\mu \mathrm{m}$ , showing promise for high-density memory selector applications. We also demonstrate direct growth on high-k AbO 3 , an important step towards realizing VLSI-compatible 2D transistors. Our results show that 2D semiconductors can be implemented on non-planar surfaces with amorphous dielectrics for 3D back-end-of-line (BEOL) integration and high-density vertical memory selectors.

Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for flexible and wearable electronics. However, it usually suffers from low semiconducting tube purity, low device yield, and the mismatch between p- and n-type TFTs. Here, we report low-voltage and high-performance digital and analog CNT TFT circuits based on high-yield (19.9%) and ultrahigh purity (99.997%) polymer-sorted semiconducting CNTs. Using high-uniformity deposition and pseudo-CMOS design, we demonstrated CNT TFTs with good uniformity and high performance at low operation voltage of 3 V. We tested forty-four 2-µm channel 5-stage ring oscillators on the same flexible substrate (1,056 TFTs). All worked as expected with gate delays of 42.7 ± 13.1 ns. With these high-performance TFTs, we demonstrated 8-stage shift registers running at 50 kHz and the first tunable-gain amplifier with 1,000 gain at 20 kHz. These results show great potentials of using solution-processed CNT TFTs for large-scale flexible electronics., Carbon nanotube thin-film transistor is promising for solution-processed, large-scale flexible electronics, but the device yields remain poor to date. Lei et al. show low-voltage flexible digital and analog circuits based on high-purity and high-yield separation of semiconducting carbon nanotubes.

The recent surge of interest in brain-inspired computing and power-efficient electronics has dramatically bolstered development of computation and communication using neuron-like spiking signals. Devices that can produce rapid and energy-efficient spiking could significantly advance these applications. Here we demonstrate direct current or voltage-driven periodic spiking with sub-20 ns pulse widths from a single device composed of a thin VO2 film with a metallic carbon nanotube as a nanoscale heater, without using an external capacitor. Compared with VO2-only devices, adding the nanotube heater dramatically decreases the transient duration and pulse energy, and increases the spiking frequency, by up to 3 orders of magnitude. This is caused by heating and cooling of the VO2 across its insulator-metal transition being localized to a nanoscale conduction channel in an otherwise bulk medium. This result provides an important component of energy-efficient neuromorphic computing systems and a lithography-free technique for energy-scaling of electronic devices that operate via bulk mechanisms.

Phase change memory (PCM) is an emerging data storage technology, however its programming is thermal in nature and typically not energy-efficient. Here we reduce the switching power of PCM through the combined approaches of filamentary contacts and thermal confinement. The filamentary contact is formed through an oxidized TiN layer on the bottom electrode, and thermal confinement is achieved using a monolayer semiconductor interface, three-atom thick MoS2. The former reduces the switching volume of the phase change material and yields a 70% reduction in reset current versus typical 150 nm diameter mushroom cells. The enhanced thermal confinement achieved with the ultra-thin (~6 {\AA}) MoS2 yields an additional 30% reduction in switching current and power. We also use detailed simulations to show that further tailoring the electrical and thermal interfaces of such PCM cells toward their fundamental limits could lead up to a six-fold benefit in power efficiency.

Non-volatility is emerging as an essential on-chip memory characteristic across a wide range of application domains, from edge nodes for the Internet of Things (IoT) to large computing clusters. On-chip non-volatile memory (NVM) is critical for low-energy operation, real-time responses, privacy and security, operation in unpredictable environments, and fault-tolerance [1]. Existing on-chip NVMs (e.g., Flash, FRAM, EEPROM) suffer from high read/write energy/latency, density, and integration challenges [1]. For example, an ideal IoT edge system would employ fine-grained temporal power gating (i.e., shutdown) between active modes. However, existing on-chip Flash can have long latencies (> 23 ms latency for erase followed by write), while inter-sample arrival times can be short (e.g., 2ms in [2]). Accepted version Work supported in part by DARPA, NSF/NRI/GRC E2CDA, and the Stanford SystemX Alliance.

Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of very large scale integration circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon nanotubes. Low-temperature fabrication (e.g.,400 °C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, high contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance, in series with the channel resistance, reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains unstudied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. In this work, we investigate by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact lengths. These CNFET contacts are ∼15 nm shorter than the state-of-the-art Si CMOS "7 nm node" contact length, allowing for multiple generations of future scaling of the transistor-contacted gate pitch. For the 10 nm contacts, we report contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at V

We investigate the valley Hall effect (VHE) in monolayer WSe

We demonstrate by experiment an image storage and compression task by directly storing analog image data onto an analog-valued RRAM array. A joint source-channel coding algorithm is developed with a neural network to encode and retrieve natural images. The encoder and decoder adapt jointly to the statistics of the images and the statistics of the RRAM array in order to minimize distortion. This adaptive joint source-channel coding method is resilient to RRAM array non-idealities such as cycle-to-cycle and device-to-device variations, time-dependent variability, and non-functional storage cells, while achieving a reasonable reconstruction performance of ∼ 20 dB using only 0.1 devices/pixel for the analog image.

The escalating RC delay and diminishing reliability of Cu interconnect present immense challenges for continued integrated circuits performance improvement. This paper reviews the use of single-layer graphene as the diffusion barrier and capping layer to extend scaling of Cu into future generations of interconnects. With graphene barrier/capping layer, processor core simulations predict an 8% speed boost or 12% energy saving, plus higher tolerance for process variations. Single-layer graphene (3.35 A thick) provides 3.3× longer barrier lifetime than 2 nm TaN. Barrier reliability is expected to further improve with transfer-free and single-crystalline graphene. In-situ low-temperature grown graphene ( 3 doping and higher immunity to electromigration. Replacing Cu with multilayer graphene, processor cores achieve 9% higher speed or 16% less energy consumption. Spin-on-glass encapsulated multilayer graphene shows two times longer electromigration lifetime than CoWP capped Cu.

We demonstrate 3D monolithically integrated two-level stacked 1-transistor/1-resistor (1T1R) memory cells, using monolayer MoS 2 transistors and few-layer hBN RRAMs, fabricated at temperatures below 150 °C. The stacking process is scalable to an arbitrarily large number of layers and on any substrate material without foreseeable physical limitations. The 1T1R cells can be switched with programming current $130\ \mu\mathrm{A}$ and voltage 2 transistor has low off-current due to the large band gap of monolayer MoS 2 $(\mathrm{E}_{\mathrm{g}} > 2\ \text{eV})$ . We also show that the linearity of RRAM resistance change is well-controlled by the gate voltage of the transistor.

Two-dimensional (2D) tunnel heterojunctions with an H-shaped energy barrier could serve as ultrathin memory selectors with good symmetry, non-linearity, and high endurance. Atomically thin 2D layered materials can potentially deliver high on-state tunneling current density. We explore the design space for H-shaped memory selectors using heterojunctions of 2D layered materials, using physical modeling and first principles density functional theory (DFT) quantum transport simulations. The difference between simulations and the few existing experiments is also discussed. A selector must be designed to suit the resistive memory (1R) characteristics. We evaluate the H-shaped selector in the one-selector-one-resistor (1S1R) configuration and provide design guidelines for the heterojunction (metal/nL hBN/nL 2D material/nL hBN/metal) design to match with the 1R characteristics.

Neuromorphic visual systems have considerable potential to emulate basic functions of the human visual system even beyond the visible light region. However, the complex circuitry of artificial visual systems based on conventional image sensors, memory and processing units presents serious challenges in terms of device integration and power consumption. Here we show simple two-terminal optoelectronic resistive random access memory (ORRAM) synaptic devices for an efficient neuromorphic visual system that exhibit non-volatile optical resistive switching and light-tunable synaptic behaviours. The ORRAM arrays enable image sensing and memory functions as well as neuromorphic visual pre-processing with an improved processing efficiency and image recognition rate in the subsequent processing tasks. The proof-of-concept device provides the potential to simplify the circuitry of a neuromorphic visual system and contribute to the development of applications in edge computing and the internet of things.

The priority of synaptic device researches has been given to prove the device potential for the emulation of synaptic dynamics and not to functionalize further synaptic devices for more complex learning. Here, we demonstrate an optic-neural synaptic device by implementing synaptic and optical-sensing functions together on h-BN/WSe2 heterostructure. This device mimics the colored and color-mixed pattern recognition capabilities of the human vision system when arranged in an optic-neural network. Our synaptic device demonstrates a close to linear weight update trajectory while providing a large number of stable conduction states with less than 1% variation per state. The device operates with low voltage spikes of 0.3 V and consumes only 66 fJ per spike. This consequently facilitates the demonstration of accurate and energy efficient colored and color-mixed pattern recognition. The work will be an important step toward neural networks that comprise neural sensing and training functions for more complex pattern recognition., Artificial neural networks can emulate the human vision because of their spike-based operation by employing memristors as synapses. Here, Seo et al. integrate synaptic and optical sensing functions in a single heterostructure, which enables accurate and energy-efficient recognition of colored patterns.

The silicon semiconductor industry has chugged along for more than 50 years. Like a steamroller, it has trundled over bumps and holes, while defying repeated warnings that it was running out of fuel or was about to be overtaken by flashier competitors.

The central theme of the “Internet of Things” is a societal and technological movement towards ubiquitous, abundant-data computing. Such transformation requires real-time analytics on enormous quantities of data collected by a vast network of sensors and other autonomous sources feeding into the data cloud. Current computing technology, however, cannot satisfy such applications with the required throughput and necessary energy efficiency. The next technology frontier will be monolithically integrated chips with 3-dimensionally interleaved memory and logic for unprecedented data bandwidth with reduced energy consumption. In this work, we exploit the atomically thin nature of the graphene plane to assemble a resistive memory stacked in a vertical 3D structure. Compared to the same architecture that uses conventional metal (Pt) as an RRAM electrode, the atomically thin graphene edge electrode was able to reduce power consumption by ×300 while producing a highly localized electrical field for oxygen anion migration. The switching energy of this device is one of the lowest reported compared to existing alternative memory technologies. Importantly, circuit analysis of the 3D architecture using experimentally measured device properties show higher storage potential for graphene devices compared that of metal based devices.

© 2004-2012 IEEE. The evolution of electronics towards compact and highly energy-efficient systems requires joint efforts in developing both innovative system architectures and novel devices. Recent developments show that time-based sensor interfaces yield highly-digital architectures, which are compatible with advanced silicon CMOS at highly-scaled technology nodes. Advancements in CMOS time-based sensor interfaces show that new circuit techniques can help to increase performance and robustness. Furthermore, these architectures have successfully been implemented in carbon nanotube technology, a promising technology to further reduce the energy consumption in electronics. In addition, CNTs are excellent candidates to be functionalized as sensors, and can potentially improve the energy efficiency of sensors and sensor interfaces for future autonomy-demanding applications. This paper presents an overview of time-based sensor interfaces implemented in CMOS and CNT technologies, allowing for scalable and robust designs. Several CMOS and VLSI-compatible CNFET-based sensor interface circuits have been fabricated and validated through measurements, demonstrating the feasibility of these solutions. ispartof: IEEE Transactions on Circuits and Systems 1, Regular Papers vol:63 issue:5 pages:577-586 ispartof: location:Lisbon: PORTUGAL status: published

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array.

A record high current density of 580 μA/μm is achieved for long-channel, few-layer black phosphorus transistors with scandium contacts after 400 K vacuum annealing. The annealing effectively improves the on-state current and Ion/Ioff ratio by 1 order of magnitude and the subthreshold swing by ∼2.5×, whereas Al2O3 capping significantly degrades transistor performances, resulting in 5× lower on-state current and 3× lower Ion/Ioff ratio. The influences of moisture on black phosphorus metal contacts are elucidated by analyzing the hysteresis of 3-20 nm thick black phosphorus transistors with scandium and gold contacts under different conditions: as-fabricated, after vacuum annealing, and after Al2O3 capping. The optimal black phosphorus film thickness for transistors with scandium contacts is found to be ∼10 nm. Moreover, p-type performance is shown in all transistors with scandium contacts, suggesting that the Fermi level is pinned closer to the valence band regardless of the flake thickness.

Carbon nanotubes (CNTs) have great potential for future high-performance and energy-efficient transistor technology. To realize this potential, methods to dope the CNTs need to be developed to achieve low parasitic resistance of the transistor. Two key issues present themselves: (a) understanding the doping mechanism of the various methods and (b) stability of the doping method. For instance, although studies on molybdenum oxide (MoOx) demonstrate its ability to heavily dope nanomaterials, the interaction between MoOx and the CNT is unclear. Here, we observe an unstable effect of MoOx on the CNT and demonstrate dielectric passivation as a means to preserve the doping strength. The semiconducting CNTs exhibit greater than 103× reduction in resistance after stably doped with MoOx. By exploiting the instability of MoOx, we delve deeper into clarifying the doping mechanism. The relationship between the time-dependent material property of MoOx and the change in the electrical measurements of CNT devices is investigated to study the role of work function in doping the CNTs. We conclude that the doping mechanism of MoOx on the CNT is due to bandgap modulation by charge transfer, which occurs due to the difference in work function between MoOx and the CNT.

While the relentless scaling of silicon-based field-effect transistors (FETs) has improved digital system performance for decades, the benefits moving forward are suffering from diminishing returns. How then can digital computing systems meet future energy efficiency requirements, for example, for future Internet-of-Everything (IoE) and abundant-data applications? To answer this outstanding question, a wide range of emerging nanotechnologies are currently being explored to replace silicon as the channel material for future transistors. In particular, carbon nanotube (CNT) FETs (CNFETs) are a highly promising candidate to continue to improve energy efficiency of digital VLSI circuits, as high-performance/energy-efficient CNFETs have been experimentally demonstrated, and larger-scale CNFET circuits and systems integrating millions of CNFETs have been experimentally demonstrated as well. In this chapter, we discuss the benefits of CNFET for VLSI circuits, and describe combined processing and design techniques to transform CNTs from a promising technology into highly energy-efficient digital circuits. Furthermore, CNFETs offer a unique opportunity to realize entirely new three-dimensional (3D) computing architectures, in which multiple layers of CNFET circuits can be densely integrated on top of each other over the same starting substrate, along with layers of memory, truly embodying computation immersed in memory. We provide an overview of the resulting 3D systems, that is, 3D nanosystems, and demonstrate that they offer EDP benefits in the range of 1000× for next-generation abundant-data applications.

The energy efficiency demands of future abundant-data applications, e.g., those which use inference-based techniques to classify large amounts of data, exceed the capabilities of digital systems today. Field-effect transistors (FETs) built using nanotechnologies, such as carbon nanotubes (CNTs), can improve energy efficiency significantly. However, carbon nanotube FETs (CNFETs) are subject to process variations inherent to CNTs: variations in CNT type (semiconductor or metallic), CNT density, or CNT diameter, to name a few. These CNT variations can degrade CNFET benefits at advanced technology nodes. One path to overcome CNT variations is to co-optimize CNT processing and CNFET circuit design; however, the required CNT process advancements have not been achieved experimentally. We present a new design approach (TRIG, Technique for Reducing errors using Iterative Gray code) to overcome process variations in hardware accelerators targeting inference-based applications that use serial matrix operations (serial: accumulated over at least 2 clock cycles). We demonstrate that TRIG can retain the major energy efficiency benefits (quantified using Energy Delay Product or EDP) of CNFETs despite CNT variations that exist in today's CNFET fabrication - without requiring further CNT processing improvements to overcome CNT variations. As a case study, we analyze the effectiveness of TRIG for a binary neural network hardware accelerator that classifies images. Despite CNT variations that exist today, TRIG can maintain 99% (90%) of projected EDP benefits of CNFET digital circuits for 90% (99%) image classification accuracy target. We also demonstrate experimentally fabricated CNFET circuits to compute scalar product (a common matrix operation, also called dot product), with and without TRIG: TRIG reduces the mean difference between the expected result (no errors) and the experimentally computed result by 30 × in the presence of CNT variations, shown experimentally.

Vanadium dioxide (VO 2 ) is attractive for a variety of applications in optics and electronics, due to its abrupt insulator-metal transition (IMT) with $> 10^{3}\times$ change in resistance near room temperature. Use of VO 2 in devices will require low power switching, with knowledge of the transition mechanism and behaviour down to nanoscale dimensions. To address this challenge, we use metallic carbon nanotubes (CNTs) with diameter ~1 nm [1] to probe nanoscale IMT in VO 2 for the first time. We find that a single CNT locally switches the VO 2 at less than half the voltage and power otherwise required. Furthermore, to understand the nanoscale IMT we use scanning probe microscopy (SPM) techniques to study devices during operation.

Selector requirements for tera-bit class, ultra-high-density 3D vertical resistive random access memory (VRRAM) are presented, including practical design considerations such as array efficiency (AE), pillar driver transistors (pillar drivers), and wire/metal plane resistances. We design a novel chip architecture that is different from 3D NAND: (a) separated, square and large wordplane (WP) connected by global wordplane connections (WPC) within a block to minimize influence of leakage currents, (b) compact staircase. An accurate, computationally efficient resistor network is developed to model the parasitic resistances of the architecture. Through the resistor network simulations, selector requirements for 3D VRRAM are examined. To achieve tera-bit class 3D VRRAM with density higher than the most advanced 3D NAND flash (> 4.3 Gb/mm2), selector nonlinearity (NL) ≥ 102 is required.

Phase change memory (PCM) is an important storage-class memory technology and a promising candidate for neuromorphic applications. PCM is based on the reversible resistance change in chalcogenide glasses, like Ge2Sb 2 Te5 (GST), which can be induced with Joule heating pulses. However, PCM often suffers from large programming energy during the reset (amorphization) process which requires heating the chalcogenide above its melting temperature $(T_{\mathrm{m}}\sim 600^{\circ}\mathrm{C})$ . Recently, significant reductions in reset energy were achieved by scaling down cell dimensions thanks to the non-filamentary nature of PCM [1].

Resistive cross-point array can be used to implement vector-matrix multiplication in analog fashion. However, the output is in the form of analog current, and thus requires A/D conversion prior to digital storage. This paper develops and demonstrates a novel in-memory matrix-matrix multiplication method (M2M) that can compute and store the result directly inside the memory itself without requiring A/D conversion. Compared with the conventional approach, M2M provides >10 × improvement in energy and area efficiency, and another 2 orders improvement when matrices are low-rank and sparse.

As two-dimensional scaling of Si CMOS crosses the nanometer threshold, from 7 nm, 5 nm, 3 nm, toward 1 nm technology nodes, will it continue to provide the energy efficiency required of future computing systems? A scalable, fast, and energy-efficient computation platform that may provide another 1,000× in computing energy efficiency (energy-execution time product) will have massive on-chip memory co-located with highly energy-efficient computing logic, enabled by 3D integration (e.g., monolithic) with ultra-dense and fine-grained connectivity. There will be multiple layers of memories interleaved with computing logic, sensors, and application-specific devices. We call this technology platform N3XT, Nano-engineered Computing Systems Technology. In this paper, we give an overview of the nanoscale memory and logic technologies that enable N3XT.

Carbon nanomaterials have greatly advanced non-volatile memory technology. In this Review, applications of various carbon nanomaterials as memory electrodes, interfacial engineering layers, memory selectors and resistive-switching media are discussed in the context of emerging non-volatile memory devices.

We provide an encoding and decoding strategy for efficient storage of analog data onto an array of Phase-Change Memory (PCM) devices. The PCM array is treated as an analog channel, with the stochastic relationship between write voltage and read resistance for each device determining its theoretical capacity. The encoder and decoder are implemented as neural networks with parameters that are trained end-to-end to minimize distortion for a fixed number of devices. To minimize distortion, the encoder and decoder must adapt jointly to the statistics of images and the statistics of the channel. Similar to Balle et al. (2017), we find that incorporating divisive normalization in the encoder, paired with de-normalization in the decoder, improves model performance. We show that the autoencoder achieves a rate-distortion performance above that achieved by a separate JPEG source coding and binary channel coding scheme. These results demonstrate the feasibility of exploiting the full analog dynamic range of PCM or other emerging memory devices for efficient storage of analog image data.

We demonstrate an end-to-end brain-inspired hyperdimensional (HD) computing nanosystem, effective for cognitive tasks such as language recognition, using heterogeneous integration of multiple emerging nanotechnologies. It uses monolithic 3D integration of carbon nanotube field-effect transistors (CNFETs, an emerging logic technology with significant energy-delay product (EDP) benefit vs. silicon CMOS [1]) and Resistive RAM (RRAM, an emerging memory that promises dense non-volatile and analog storage [2]). Due to their low fabrication temperature ( 20,000 sentences (6.4 million characters) per language pair. 2. One-shot learning (i.e., learning from few examples) using one text sample (∼100,000 characters) per language. 3. Resilient operation (98% accuracy) despite 78% hardware errors (circuit outputs stuck at 0 or 1). Our HD nanosystem consists of 1,952 CNFETs integrated with 224 RRAM cells.

Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and time-consuming data movement that plagues current designs. Here we review the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, their resistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing. This Review Article examines the development of in-memory computing using resistive switching devices.

The Collaborative Innovation Center of Suzhou Nano Science & Technology, the Jiangsu Key Laboratory for Carbon-Based Functional Materials & Devices, and the Priority Academic Program Development of Jiangsu Higher Education Institutions are also acknowledged. Stanford co-authors acknowledge support from the Non-volatile Memory Technology Research Initiative (NMTRI). An Chen from IBM is acknowledged for revision of section 5. Alok Ranjan from Singapore University of Technology and Design is acknowledged for useful discussion on section 3.5., Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, being electronic non-volatile memories those that have received most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. In this manuscript we describe the most recommendable methodologies for the fabrication, characterization and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology., This work has been supported by the Young 1000 Global Talent Recruitment Program of the Ministry of Education of China, the National Natural Science Foundation of China (grants no. 61502326, 41550110223, 11661131002), the Jiangsu Government (grant no. BK20150343), and the Ministry of Finance of China (grant no. SX21400213).

Incredibly thin transistors could deliver even more powerful computers if three research challenges can be solved, argue Ming-Yang Li and colleagues. Incredibly thin transistors could deliver even more powerful computers if three research challenges can be solved, argue Ming-Yang Li and colleagues.

This paper highlights the feasible routes of using resistive memory (RRAM) for accelerating online training of deep neural networks (DNNs). A high degree of asymmetric nonlinearity in analog RRAMs could be tolerated when weight update algorithms are optimized with reduced training noise. Hybrid-weight Net (HW-Net), a modified multilayer perceptron (MLP) algorithm that utilizes hybrid internal analog and external binary weights is also proposed. Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.

We demonstrate the first 1-transistor-1-resistor (1T1R) memory cell using the atomically thin molybdenum disulfide (MoS2) field-effect transistor (FET) and resistive random access memory (RRAM). This 1T1R demonstration realizes a key milestone for tight integration of memory with logic in a monolithic 3D integrated chip. The monolayer MoS2 is grown by chemical vapor deposition (CVD), suitable for wafer-scale fabrication. The MoS 2 FETs have ON-state current of 190 μA/μm at V d = 2.5 V, showing strong driving capability for RRAM. Metal-oxide RRAMs are fabricated at low process temperature, compatible with MoS 2 FET fabrication. 1T1R measurements show higher resistances, and less resistance and voltage variation compared with measurements using only the RRAM. The multiple resistance states obtained for pulsed reset measurements show promise for in-memory computing and neuromorphic computing applications.

We present the first fabrication of electronic synapses using two dimensional (2D) hexagonal boron nitride (A-BN) as active switching layer. The main advantage of these devices compared to the transition metal oxide (TMO) based counterparts is that multilayer A-BN stacks show both volatile and non-volatile resistive switching (RS) depending on the programming stresses applied, which allows implementing short-term (STP) and long-term plasticity (LTP) rules using a single device and without the need of complex architectures.

A resistive random access memory (RRAM) device with a tunable switching window is demonstrated for the first time. The SET voltage can be continuously tuned from 0.27 to 4.5 V by electrical gating from -10 to +35 V. The gate-controlled bilayer graphene-electrode RRAM can function as 1D1R and potentially increase the RRAM density.