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Selective energy transfer from triplet states of the fluorescent blue emission layer to a red phosphorescent dye in a neighbored triplet harvesting layer has been achieved, which has provided improved efficiency with emissions from fluorescent and phosphorescent dyes. First of all, it is crucial to find a wide band gap host for a fluorescent blue emission layer which has larger triplet state band gap than green or red phosphorescent dye. It was found that TcTa is a good wide band gap host for fluorescent blue dopant(BD) and a efficient blue device was obtained. A phosphorescent red dopant (RD) was introduced into a neighboring electron transporting layer to harvest triplet states in the fluorescent blue emission layer and by optimizing the distance between the blue emission layer and the red triplet harvesting layer, we have succeeded in obtaining the balanced emission of the blue and the red emissions with high efficiency from the device structure of NPB/TcTa:BD/BAlq/BAlq:RD/BAlq/LiF/Al. The device showed maximum external quantum efficiency of 16 % at 0.1 mA/cm2 and 13 % of external quantum efficiency, (0.29, 0.23) of CIE coordinates and 920 cd/m2 at 10 mA/cm2. To realize RGB WOLED, a fluorescent green dopant was introduced into the blue emission layer. The RGB WOLED was successfully obtained through optimization of doping concentration for green dopant and it showed 10 % of external quantum efficiency, (0.36, 0.36) of CIE coordinates and 1400 cd/m2 at 10 mA/cm2.

We successfully demonstrate a 1.89-inch SLMoG (spatial light modulator on glass) driven by oxide BCE (back channel etch) TFTs (thin-film transistor). It is necessary for SLM to have very fine pixel pitch and large panel size for realizing high display quality of digital holography. To confirm such technical demands, we fabricate 1.89-inch SLMoG with 20-μm pixel pitch, and apply ECB (electrically controlled birefringence) LC (liquid crystal) mode for light phase modulation. In this article, we report the results of demonstration and discuss technical issues of SLMoG technology.

In this work, we report reflective colored organic light-emitting diodes (OLEDs) integrated with color-selective reflective filter (CSRF) and transparent OLEDs functioning as the reflective and emissive mode. To fabricate transparent OLEDs with low-reflective anode, the dry bonding technology of graphene anode was developed.

The poly(ethylene naphthalate) (PEN) substrates have two sides of bare PEN and primer-coated surfaces treated to provide slip property for film production. Although the primer surface showed porous and inhomogeneous morphologies, a hybrid inorganic/organic double-layered barrier layer can effectively improve the surface roughness and permeability. The fabricated amorphous In-Ga-Zn-O thin-film transistors on the PEN substrates with hybrid barrier showed good performances and did not experience any degradation under the mechanical bending situation at a curvature radius of 3.3 mm. The variation in the threshold voltage was evaluated to be approximately −0.1/1.6 V under the negative/positive bias stress tests, respectively.

In this paper, we present the architecture of oxide TFT selected from diverse TFT structures for the application to the high resolution mobile display. Due to the selection of proper materials and process, we can achieve highly stable BCE TFT and show the promise of vertical oxide TFT with the smallest TFT footprint.

Fully transparent amorphous-InGaZnO thin-film transistors (TFTs) with double-gate (DG) configuration were fabricated. Both top-gate and bottom-gate (BG) TFT fabricated with a single gate-stack structure were found to exhibit sound device characteristics with μsat of 17.0 and 18.1 cm2 V−1 s−1, respectively. Confirmed benefits of DG configuration include improved current drivability and threshold voltage tunability. Further, controlling the fixed voltage bias to the BG was observed to enhance device stability under negative-bias-illumination-stress conditions.

An analytical solution of the electric potential and field for the wedge-shaped gate-oxide, which is formed inevitably in recessed-LOCOS structure, is proposed. This abnormal geometry includes an apex, which brings about an electrical failure during the gate-bias test. First, we show that the apex angles change according to the thickness of the sidewall nitride spacer by process simulation and physical arguments. We model the wedge-shaped gate-oxide in a simple geometry and calculate the electric potential and field with the various apex angles. We calculate the resultant tunneling current using the Fowler-Nordheim model. As the result of the calculation, we prove that above a certain spacer thickness, the breakdown voltage fluctuates from site to site within a wafer in gate-bias test with the memory cell array pattern. We predict that this breakdown phenomenon occurs regardless of the gate-oxide thickness and also suggest the presence of the limiting apex angle to maintain the gate-oxide reliability.

We fabricated field emitter arrays on thin-metal electrodes by using carbon nanotube (CNT). The turn-on fields of CNT emitters patterned by photolithography and lift-off process were 4.2 V//spl mu/m and 2.2 V//spl mu/m, respectively. The lower turn-on field for the latter was due to the thinner residue covering the surface of CNT emitters after final heat treatment.

A novel method is proposed for simulating free space field propagation from a source plane to a destination plane that is applicable for both small and large propagation distances. The angular spectrum method (ASM) was widely used for simulating near field propagation, but it caused a numerical error when the propagation distance was large because of aliasing due to under sampling. Band limited ASM satisfied the Nyquist condition on sampling by limiting a bandwidth of a propagation field to avoid an aliasing error so that it could extend the applicable propagation distance of the ASM. However, the band limited ASM also made an error due to the decrease of an effective sampling number in a Fourier space when the propagation distance was large. In the proposed wide range ASM, we use a non-uniform sampling in a Fourier space to keep a constant effective sampling number even though the propagation distance is large. As a result, the wide range ASM can produce simulation results with high accuracy for both far and near field propagation. For non-paraxial wave propagation, we applied the wide range ASM to a shifted destination plane as well.

Multilayered ZnO-SnO2 heterostructure thin films were produced using pulsed laser ablation of pie-shaped ZnO-SnO2 oxides target, and their structural and field effect electronic transport properties were investigated as a function of the thickness of the ZnO and SnO2 layers. The films have an amorphous multilayered heterostructure composed of the periodic stacking of the ZnO and SnO2 layers. The field effect electronic properties of amorphous multilayered ZnO-SnO2 heterostructure thin film transistors (TFTs) are highly dependent on the thickness of the ZnO and SnO2 layers. The highest electron mobility of 37 cm2/V s, a low subthreshold swing of a 0.19 V/decade, a threshold voltage of 0.13 V, and a high drain current on-to-off ratio of ∼1010 obtained for the amorphous multilayered ZnO(1.5 nm)-SnO2(1.5 nm) heterostructure TFTs. These results are presumed to be due to the unique electronic structure of an amorphous multilayered ZnO-SnO2 heterostructure film consisting of ZnO, SnO2, and ZnO-SnO2 interface layers.

High resolution display are considered to need oxide TFTs with higher mobility than 30 cm2/V.s and less parasitic capacitance. Until recently, many active materials for high mobility TFT such as ZITO1, AZITO2, IGO3, In rich IGZO4, and ZnON 5 have been reported. The proper device structure with less parasitic capacitance is known to be self-aligned top gate TFT. In designing high performance high mobility oxide TFT gate insulator deposition is very critical process especially in top gate TFT due to the difficulty in controlling the carrier amounts of high mobility oxide semiconductor. PECVD process of SiO2 induces not only H incorporation into the below layer but result in SiO2 with large amounts of H. O-H in dielectric layer is thought to be the origin of hole trapping site. Besides it causes negative Vth shift after annealing of TFT. Therefore it is very important to deposit SiO2gate dielectric film with less H without inducing H incorporation into the active layer. As the preliminary structure of top gate self-aligned TFT, we fabricate top gate staggered TFT with ITO as SD electrode, IGZO as active layer, SiO2 grown by PEALD at 250oC as the first gate insulator, SiO2 deposited by PECVD at 350oC as the main gate insulator, and Mo as the gate electrode. While the TFT annealed at 250oC showed the mobility, Vth, and S.S to be 35.5 cm2/V.s, 0V, and 0.27 V/dec., respectively, those annealed at 300oC were 39.9 cm2/V.s, -1V, and 0.32 V/dec., respectively. The annealing TFT at higher temperature than the deposition temperature of first gate insulator induced negative Vth shift from 0V to -1V with increase of mobility. A noteworthy is the stability behavior under positive/temperature stress. IGZO TFT annealed at 250oC showed positive Vth shift of 3.28V under 20V at 60oC for 10K seconds. Meanwhile that annealed at 300oC was shifted by 0.28V after same condition without change of S.S value. Positive shift of Vth under positive bias stress was mostly blamed on the defect generation at the interface and it can be alleviated by thermal annealing. However, we could not identify the origin of defects and curing mechanism by thermal annealing. After several investigations on the interface defects and annealing process, we suggest that the main origins of bias instability are oxygen interstitial as well as the weak bond formation at the interface from the plasma process during GI or active deposition. In addition, these defects can be cured by H passivation which can be incorporated during the annealing process. Therefore H in the adjacent film of active layer can be not only a bad player in terms of carrier generation but good player in a view point of passivation of defects in active layer and interface of oxide TFT. Reference [1] M. K. Ryu, S. Yang, S.-H. K. Park, C.-S. Hwang, and J. K. Jeong, IEEE Electron Device Letters, 31 (2), 144 (2010) [2] S. Yang, D. H. Cho, M. K. Ryu, S. H. Ko Park, C. S. Hwang, J. Jang, and J. K. Jeong, IEEE Electron Dev. Lett. 31, 144 (2010) [3] K. Ebata, S. Tomai, Y. Tsuruma, T. Iitsuka, S. Matsuzaki, and K. Yano, Applied Physics Express 5, 011102 (2012) [4] T. Arai and T. Sasaoka, SID Int. Symp. Digest Tech. Papers, 710 (2011). [5] Y. Ye, R. Lim, and J. M. White, JOURNAL OF APPLIED PHYSICS 106, 074512 (2009)

We proposed a bilayered etch-stop layer (BiESL) composed of Al2O3/SiO2 for the high-mobility oxide thin-film transistor (TFT) fabricated with low-resistivity Cu electrodes. The In–Ga–Zn–O TFT employing the BiESL showed no marked degradation in its high mobility and transfer characteristics even after the conventional passivation process using SiN x film, which causes hydrogen incorporation into the active channel. Excellent barrier properties of atomic-layer-deposited Al2O3 film could provide the feasibility for the direct deposition of organic planarization film without the need for an extra passivation layer. The proposed BiESL structure was also suggested to be compatible with the simple patterning process of Cu electrodes.

The optimization of the passivation process for oxide thin film transistors with high carrier mobility was investigated. Hydrogen incorporation into oxide channels during the deposition of SiNx could degrade device stability and uniformity, especially for high-mobility devices. A novel double-layered passivation film structure composed of Al2O3/SiNx was proposed, in which thin and dense Al2O3 film prepared by atomic layer deposition was introduced underneath the SiNx layer. In-Ga-Zn-O TFT passivated with the proposed double-layered films showed no significant negative shift in turn-on voltage, even after passivation. The field-effect mobility and subthreshold swing were typically measured as 27.7 cm2 V−1 s−1 and 0.11 V/dec, respectively. Hydrogen doping was effectively protected by the introduction of Al2O3 as thin as 15 nm.

In-Ga-Zn-O (IGZO)-channel oxide thin-film transistors (TFTs) were fabricated on flexible polyethylene naphthalate (PEN) substrates. A lamination and delamination procedure was established that allowed easy handling of the PEN substrate during fabrication. In order to fabricate high-performance flexible IGZO TFTs at lower than normal process temperatures, a 2:1:2 (In:Ga:Zn) IGZO channel composition was proposed. The field-effect mobility, threshold voltage, and subthreshold swing of the fabricated IGZO TFTs were found to be approximately 7.83 cm2 V−1 s−1, 1.93 V, and 0.24 V/decade, respectively, even when a final heat treatment was conducted at a temperature as low as 150 °C. The stability characteristics of the devices were also examined under gate bias stress and constant current stress conditions.

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This study examined the effect of oxygen plasma treatment on light-enhanced bias instability in Zn-Sn-O (ZTO) thin film transistors (TFTs). The treated ZTO TFT exhibited only a threshold voltage (Vth) shift of −2.05 V under negative bias illumination stress (NBIS) conditions, whereas the pristine device suffered from a negative Vth shift of 3.76 V under identical conditions. X-ray photoelectron spectroscopic analysis revealed that the oxygen vacancy defect density was diminished via the oxygen plasma treatment. This suggests the Vth degradation under NBIS is due to photo-transition of oxygen vacancy defects.

A novel strategy to enhance the bias and illumination stress stability of oxide thin-film transistors (TFTs) is presented. The ultrathin positive charge barrier is employed to block the movement of photo-generated charges toward the interface between gate insulator and semiconductor under negative gate bias and illumination. This method can break through the limitation in stability enhancement caused by the inevitable oxygen vacancy and facilitates the fabrication of highly stable oxide TFTs at low process temperature.

We have fabricated fully patterned transparent oxide/organic hybrid transistors on glass substrates that contain In-Ga-Zn-O as the active layer and a poly(4-vinyl phenol-comethyl methacrylate) copolymer as the dielectric layer. These devices exhibit a saturation mobility of 6.04 cm2/V s, a threshold voltage value of 3.53 V, a subthreshold slope of 360 mV/decade, and an on-off ratio of 1.0×109 at a maximum processing temperature of 200 °C. We found that the bias stability characteristics of the hybrid transistors are dependent on the ambient conditions, but can also be dramatically improved by applying a hydrophobic organic passivation layer to the gate insulator.

Two inverter architectures are proposed to be integrated on panels for flat panel display applications using only n-type amorphous indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The proposed cross-coupled (CC) inverter uses the positive feedback effect of its CC structure to reduce the static current and increase the output voltage swing when using depletion mode n-type amorphous IGZO TFTs. The other proposed cross-coupled and bootstrapping (CCB) inverter also uses the cross-coupled structure and includes a capacitor for the bootstrapping effect to increase the operating frequency. The measured results show that the output voltage swing of the proposed CC inverter is from 0 to 14.50 V and that of the CCB inverter is from 0.15 to 14.57 V when V DD is 15 V at 20 kHz and the load capacitance is 103.0 pF. The power consumption of the CC and CCB inverters are 1.4 and 2.5 mW, respectively, which are 29.3 and 53.4% of the power consumption of the ratioed inverter.

The light stability of top gate indium gallium zinc oxide (IGZO) thin film transistor (TFT) has been investigated under gate bias and constant current stress to explore the possibility of active matrix display applications. While the halogen lamp irradiation onto the device under positive gate bias stress caused just -0.18 V of threshold voltage shift (ΔV th), it resulted in -15.1 V shift under negative gate bias stress. When the white light extracted from the halogen lamp of 100 µW/cm2 power illuminated the device under constant current stress, operation voltage shifted just -0.05 V for 21 h. The result shows good promise for the application of highly stable IGZO TFT to active matrix organic light emitting diodes (AMOLEDs).

Organic–inorganic hybrid-type nonvolatile memory thin-film transistors using an organic ferroelectric gate insulator and an oxide semiconducting active channel are a very promising solution to the memory devices having both features of low-cost and high-performance, which are embeddable into the next-generation flexible and transparent electronics. In this paper, we discuss some important issues for this proposed device, such as device structure design, process optimization and memory array integration. Promising feasible applications and remaining technology issues to solve were also discussed.

The gate bias dependence on the negative bias instability under illumination was examined. As the gate bias got more negative, dominant mechanism was changed from simple charge trapping to that accompanied by generation of subgap states. Degree of threshold voltage shift was not monotonously dependent on the magnitude of negative gate bias. It is strongly related with the corresponding instability modes for different gate bias regimes. The transition of instability mechanism depends on how much the gate bias stabilizes ionized oxygen vacancy states.

We investigated the visible photon accelerated negative bias instability (NBI) in amorphous In–Ga–Zn–O (a-IGZO) thin film transistor (TFT). As reported in previous works, the rigid shift in transfer curves with insignificant changes in field-effect mobility and subthreshold swing was observed. On the other hand, there is substantial change in capacitance-voltage characteristics caused by created subgap states. The suggested nature of created states is the ionized oxygen vacancy (VO2+) by the combination of visible light and negative bias. The generated VO2+ states enhance the NBI under illumination as increased deep hole trapping centers. Furthermore, the photoexcitation of VO to stable VO2+ yields excess free carriers in conduction band. The increased carrier density also enhances the negative shift in turn-on voltage of a-IGZO TFT.

P-type thin-film transistors (TFTs) using room temperature sputtered SnOx (x

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This study examined the impact of the passivation layer on the light-enhanced bias instability of Al–Sn–Zn–In–O (AT–ZIO) thin film transistors. The suitably passivated device exhibited only a threshold voltage (Vth) shift of 0.72 V under light-illuminated negative-thermal stress conditions, whereas the device without a passivation layer suffered from a huge negative Vth shift of >11.5 V under identical conditions. The photocreated hole trapping model could not itself explain this behavior. Instead, the light-enhanced Vth instability of the unpassivated device would result mainly from the photodesorption of adsorbed oxygen ions after exposing the AT–ZIO back-surface in an ambient atmosphere.

This work was funded by the Portuguese Science Foundation (FCT-MCTES) through projects PTDC/CTM/73943/2006, PTDC/EEA-ELC/64975/2006, ERC 2008 Advanced Grant (INVISIBLE Contract No. 228144) and IT R&D program of MKE (Contract No. 2006-S079-03, Smart window with transparent electronic devices) from ETRI Korea. We thank K. Nomura for the Seebeck measurements and N. Franco for the XRD analysis. Copper oxide (Cu2 O) thin films were used to produce bottom gate p-type transparent thin-film transistors (TFTs). Cu2 O was deposited by reactive rf magnetron sputtering at room temperature and the films exhibit a polycrystalline structure with a strongest orientation along (111) plane. The TFTs exhibit improved electrical performance such as a field-effect mobility of 3.9 cm2 /V s and an on/off ratio of 2× 102. publishersversion published

The combination of a ferroelectric polymer and an oxide semiconductor is a very promising solution to realize embeddable nonvolatile memory thin-film transistors (TFTs) for novel electronic devices. Memory TFTs with a gate structure of Al/80 nm-poly(vinylidene fluoride–trifluoroethylene) [P(VDF–TrFE)]/4 nm Al2O3/5 nm ZnO were fabricated and their programming characteristics were investigated. Good performances in memory and transistor behaviors were successfully confirmed. When the voltage pulses of ± 15 V and 990 ms were employed, a memory on/off ratio of 4400 was obtained. It was found that the initial memory on/off ratio was closely related to the applied programming conditions such as pulse amplitude and width of programming voltage signals. Retention behaviors were also sensitively affected by the programming conditions. The initial memory on/off ratio of approximately 300 decreased to 3.4 after a lapse of 104 s when the programming voltage, pulse duration, and gate bias during the retention period were set to be ± 18 V, 500 ms, and open, respectively.

DC–DC converters integrated into a panel are proposed for mobile display applications using indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The proposed positive DC–DC converter uses cross-coupled and diode-connected structures for a high output voltage and a high power efficiency, while the proposed negative DC–DC converter uses also a cross-coupled structure but with separated pumping capacitors for a negative output voltage and a high power efficiency. The simulated results show that the output voltage and power efficiency are 21.3 V and 69.5% for the positive DC–DC converter and -5.1 V and 56.1% for the negative DC–DC converter, respectively, at a supply voltage of 10 V and a load current of 250 µA. The measured results show that the output voltage and power efficiency of the proposed positive DC–DC converter are 20.8 V and 66.6%, respectively, under the same conditions as those for the simulated results.

Solution-Processed Zinc Indium Oxide Transparent Nonvolatile Memory Thin-Film Transistors with Polymeric Ferroelectric Gate Insulator Sung-Min Yoon, Shin-Hyuk Yang, Soon-Won Jung, Chun-Won Byun, Sang-Hee Ko Park, Chi-Sun Hwang, and Hiroshi Ishiwara* Tokyo Institute of Technology, Yokohama 226-8502, Japan Convergence Components and Material Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon 305-700, Korea

The nonvolatile memory thin film transistors (MTFTs) using a solution-processed zinc indium oxide (ZIO) active channel and a poly(vinylidene fluoride-trifluoroethylene) ferroelectric gate insulator was proposed and characterized. The spin-coated ZIO films showed good transmittance (~90%) in the visible range. The crystalline phases are essentially amorphous even after the annealing at 400°C. All fabricated MTFTs exhibited memory behaviors based on the ferroelectric field effect in their transfer characteristics. The on/off ratio, the off current level, and the field-effect mobility were markedly varied with the changes in the annealing temperature and film composition. These differences may originate from the variations in conduction mechanism. The best device performances were obtained for the MTFT using the 83/17 mol % ZIO channel annealed at 400°C. The memory window at the V G sweep of ± 15 V, field-effect mobility, subthreshold swing, and on/off ratio were obtained to be 9.6 V, 3.3 cm 2 V -1 s -1 , 0.86 V/dec, and 8.4 × 10 6 , respectively. The memory on/off ratio of more than 500 was retained after a lapse of 10 h.

We have prepared ZnO TFT driving color AMEPD using nano-scale electrophoretic ink particles made by invented modified emulsion process. New concept of color filter using silver halide technology — similar with photographic technology-which is suitable for reflective EPD application was adapted to develop color filters. To get rid of align process for color filters and TFT arrays, transparent ZnO TFT with low temperature process was fabricated. In case of monochrome EPD, the contrast ratio was 23:1 at operating voltage of ± 10V. Zone color prototype AMEPD was fabricated with silver halide color filter.

— The stability of oxide TFTs has been the main focus of this research and is probably the most crucial requirement for the successful application to flat-panel displays. Although the high Fermi level of oxide semiconductors makes TFTs basically stable under electrical stress, the device reliability under diverse variations of electrical stress is affected by materials such as active semiconductors and gate insulators, processes for the formation of back/front channels and passivation layers, and device configurations among other things. How these factors affect the device reliability have been investigated and a review of the stability is presented. In addition, several categories of the light instability of oxide TFTs is presented and the origin is discussed.

To improve the bias stress stability of ZnO thin film transistors (TFTs), a double-layered Al 2 O 3 gate insulator (GI) prepared by atomic layer deposition was proposed for forming high quality interface and suppressing interdiffusion. The protection layer deposited using water vapor, which also acts as a first GI, plays an important role in improving the bias stability. We obtained excellent characteristics of the ZnO TFT, in which the threshold voltage of 0.65 V and the mobility of 5.87 cm 2 V ―1 s ―1 did not show any changes at the stress field of 1.7 MV/cm even after 51,000 s.

We investigated the effect of the light-induced bias instability of indium-gallium-zinc oxide(IGZO) thin film transistors. The IGZO TFT exhibited the excellent subthreshold gate swing of 0.12V/decade, Vth of −0.5V, and high Ion/off ratio of >109 as well as a high field-effect mobility of 26.7 cm2/Vs. The Vth is not changed after positive bias illumination stress (PBIS) for 10000sec. However, the Vth is −8V after negative bias illumination stress (NBIS)for 10000sec. This phenomenon can be attributed the trapping of the photon-induced charges into the gate dielectric/active interface. We fabricated transparent AM-OLED driven by highly stable bottom gate IGZO TFT array

We have fabricated 3.2″ QVGA transparent AMOLED by integrating photostable top gate IGZO TFT array and highly transparent OLED. The photostability of oxide TFT was investigated under constant gate bias and constant current CC stress to explore the possibility of OLED application. After 40 hours CC stress of 10 μA with halogen lamp illumination, the ΔVth was just − 0.22 V while that obtained under dark was + 0.1 V. with newly designed OLED cathode and transparent getter we increase OLED transmittance up to 80% with keeping resistance of cathode at 6 Ω;/□. Outdoor stability of OLED and oxide TFT make transparent AMOLED viable in the real market.

The electrical characteristics of metal-insulator-semiconductor (MIS) capacitors with Al/Al 2 O 3 /ZnO structures were investigated by capacitance-voltage (C-V) measurements. The ZnO films were prepared by plasma-enhanced atomic layer deposition as a common semiconducting layer. The insulators of Al 2 O 3 were composed of a thin protection layer (PL), a first gate insulator, directly deposited on ZnO, and a main gate insulator by changing the oxygen sources (water vapor, in situ generated O 2 plasma, and ozone) during atomic layer deposition (ALD). When the PL was prepared by water, good electrical behaviors in C-V measurements such as no voltage hysteresis and normal flatband voltage (V FB ) were observed for the capacitors, regardless of the ALD condition for the deposition of the main gate insulator. For the MIS containing a PL deposited with O 2 plasma or ozone, the Al 2 O 3 /ZnO interfaces were markedly degraded, in which large hystereses and positive shifts of V FB were observed.

We investigated the effect of the Sn/Zn ratio in the amorphous Zn-In-Sn-O (ZITO) system on the gate voltage stress-induced stability of the resulting thin film transistors (TFTs). The device stability of the TFTs with a composition channel of Zn:In:Sn=0.35:0.20:0.45 (device C) was dramatically improved, while those of the devices with Zn:In:Sn=0.45:0.20:0.35 and 0.40:0.20:0.40 suffered from deep level trap creation in the channel and charge trapping, respectively. The stability enhancement of device C can be attributed to its having the lowest total trap density, which was corroborated by the superior temperature stability of the subthreshold current region in the temperature range from 298 to 398 K. Therefore, the Sn atoms are believed to act as a stabilizer of the amorphous ZITO network, which is similar to the role of Ga in the In-Ga-Zn-O system.

Ensuring the sound ferroelectric behaviors of the ferroelectric copolymer poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] after various fabrication processes routinely performed for the device integration is very important for the practical nonvolatile memory applications using P(VDF-TrFE). In this work, the changes in the electrical and physical properties of the P(VDF-TrFE) thin film were investigated, assuming that some chemical treatments are involved in the fabrication processes for P(VDF-TrFE)-based memory devices. Although the treatments in the conventional developer and acids fortunately caused no critical damage to the film, it was found that the use of some resist strippers provides harsh conditions to the film. They caused the degradation in the crystallinity and surface roughness, and hence large increases in coercive field and leakage current were observed. Among the chemicals tested in this work, we proposed 1-methoxy-2-propanol as the best resist stripper. Metal–ferroelectric–metal capacitors and metal–ferroelectric–insulator–semiconductor diodes were also fabricated using the proposed patterning methods, in which no critical degradation in ferroelectric memory effects was observed when the size of capacitor decreased to 30 ×30 µm2. We conclude that these experimental studies can give us a useful solution to realizing memory arrays and related integrated circuits by exploiting P(VDF-TrFE)-based nonvolatile memory devices.

We compared the effect of the temperature on the device stability of Al–Zn–Sn–O (AZTO) thin film transistors (TFTs) with top gate and bottom gate architectures. While the bottom gate device without any passivation layer on the AZTO channel layer showed a large threshold voltage (Vth) shift of 1.6 V after heating it from 298 to 398 K, the naturally passivated top gate device exhibited a smaller Vth shift of 0.6 V. This different behavior is discussed based on the concept of the thermal activation energy of the subthreshold drain current. It is proposed that the suitable passivation and lower interfacial trap density for the top gate TFT are responsible for its superior temperature stability compared to the bottom gate device.

Thin film transistors with a channel of Zn–In–Sn–O were fabricated via a combinatorial rf sputtering method. It was found that the role of the In atoms is to enhance the mobility and to shift the threshold voltage (Vth) negatively. On the other hand, the Sn fraction is critical for improving the overall trap density including the density-of-states of the bulk channel layer and the interfacial trap density at the ZnInSnO interface. The optimized transistor was obtained at a compositional ratio of Zn:In:Sn=40:20:40, which exhibited an excellent subthreshold gate swing of 0.12 V/decade, Vth of −0.4 V, and high Ion/off ratio of >109 as well as a high field-effect mobility of 24.6 cm2/V s.

A comparative study was made of the performance and electrical instabilities in amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors with Al2O3 and Al2O3/SiNx gate dielectrics. Steeper subthreshold slope is observed in Al2O3 devices, which shows that the density of trap states at the interface of a-IGZO/Al2O3 is lower than that of a-IGZO/SiNx. Under high bias-stresses, a larger degradation is observed in Al2O3/SiNx devices. The device degradation for both devices are mainly attributed to the charge trapping phenomenon, but the different time dependence of threshold voltage shift shows that trapped electrons are more easily redistributed inside the Al2O3 dielectrics.

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Using a double-layered gate insulator [SiO2 (100 nm)/Al2O3 (10 nm)] and a dry-etching process for the channel layer, we could obtain high mobility top-gate SnO2 and ZnO–SnO2 (ZTO) transparent thin-film transistor (TTFT). After annealing at 300 °C, for 1 h in O2 ambient, the saturated mobility of SnO2 TTFT was 17.4 cm2 s-1 V-1, and that of ZTO TTFT was 50.4 cm2 s-1 V-1. Generally, both devices operated in the enhancement mode with a drain current on-off ratio of ~106.