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In the past, a priori interconnect prediction, based on Rent's rule, has been applied mainly for technology evaluation and roadmap applications. These applications do not require extreme accuracy and generally use typical values of the Rent exponent. Recent work has shown that a very high correlation across predictions for individual circuits can be obtained by using the experimentally measured partitioning Rent characteristic for prediction. Using those new prediction techniques, a priori interconnect prediction has become more usable for design space exploration early in the design cycle. However, the measurement of a Rent characteristic, i.e., a full recursive circuit partitioning, can take a lot of time. In this paper, we propose a model for the partitioning Rent characteristic that allows an accurate estimation of the Rent characteristic by performing only three levels of recursive partitioning.

It is our goal to demonstrate the viability of massively parallel optical interconnects between electronic VLSI chips. This is done through the development of the technology necessary for the realisation of such interconnections, and the definition and realisation of a systems architecture in which these interconnections play a meaningful role. Multi-FPGA systems have been identified as a good candidate for the introduction of low level optoelectronic interconnects, from both the systems and the purely demonstrator related points of view. An optoelectronic FPGA demonstrator along these lines is currently being realised. This involves besides the actual CMOS FPGA, the design and implementation of various light sources and detectors, as well as the analogue CMOS interface circuits; the building blocks of the optical pathways, which are based upon plastic optical fibre; and the methodology for hybrid assembly, packaging and passive alignment of all components. The optoelectronic FPGA demonstrator aims at using a smart-pixel like interconnect structure to create a logically 3-dimensional architecture.

In this paper, we address the possible advantages of using optoelectronic area-I/O to realize three-dimensional multi-FPGA architectures. Our approach is based on experimental determination of achievable clock rates when realizing synchronous designs. Our experiments indicate that three-dimensional optoelectronic multi-FPGA architectures exhibit higher performance than traditional two-dimensional electronic FPGAs, provided the optical link latency is sufficiently low. It turns out that with latencies of state of the art optical links the gains can be positive, in particular for large and complex designs.

The authors propose a measurement setup consisting of a number of ultrasonic sensors used in parallel to perform triangulation measurements. The sensor system is based on two ideas. The first idea was to use signal processing techniques borrowed from existing radar and sonar systems. This allows the accurate determination of the position of multiple objects. Processing data in real time demands a fairly powerful processing system. The second idea was to assign a microprocessor to each transducer. To support the use of multiple sensors in the final measurement setup, transputers were used as processing elements as they offer easy scalability because of their serial links. This sensor measured the distance to multiple objects very accurately and with a resolution of 2 cm. It is shown that these techniques could be implemented in a cost-effective manner. >

Recently, several Linda-like parallel extensions of programming languages have been developed. A Linda-based extension consists roughly of a number of sequential agents (processes) communicating with each other by means of a shared associative tuple space or blackboard. The Linda communication paradigm is deemed useful and powerful. The main difficulty in implementing this type of communication is the design of an efficient architecture for the shared blackboard. The challenge is to design a blackboard that can be accessed simultaneously by as many agents as possible, thereby preserving its integrity and correct behavior. This paper describes the architecture of a scalable and efficient implementation of a blackboard for Multi-Prolog, a blackboard-based parallel Prolog. >

To overcome the problems associated with the use of ultrasonic sensors for navigation purposes, the authors propose a measurement system composed of three ultrasonic sensors, one transmitting and three receiving, placed on a moving vehicle. By triangulation, this tri-aural sensor is able to determine the position, both distance and bearing, of the objects in the field of view. However, based on the information from one single snapshot, the sensor cannot distinguish between corners and walls. A statistical test that combines consecutive sightings of the same object to determine whether it is a wall or a corner is derived. This test is formulated as a sequential test which guarantees that the object will be recognized after the minimal number of measurements given a predetermined error probability. Preliminary experimental data show the feasibility of the approach. >

Important layout properties of electronic designs include space requirements and interconnection lengths. A reliable interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor /spl delta//spl ap/2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.

A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from the start. An efficient test compaction method leads to a very compact test set, while retaining a maximum of diagnostic power and a 100% fault coverage for non-fanout circuits. An extension for fanout circuits is also presented.

The term smart-pixel architectures usually refers to systems that consist of optically connected electronic planes, having a regular two-dimensional structure, and in which the electronics form a high-performance array processing structure. We use the term smart-pixel interconnect to designate an optical interconnect that consists of a massive number of light sources or detectors placed on a two-dimensional grid, that interconnect to a similar array located on the surface of a neighboring chip. We do not imply any dedicated nature of the underlying electronics. Such smart-pixel interconnects are being considered as a possible way to solve or alleviate the rapidly worsening interconnect problems of VLSI.

The performance of future generation data processing systems will be set by interconnect limitations rather than by IC performance. The main reason for this expected I/O-bottleneck is the projected increase in CMOS IC-complexity, in terms of chip size, number of I/O pads and clock frequency. Problems inherently associated with closely packed electrical interconnections (such as cross-talk, signal distortion EMI) will lead to bandwidth limitations, in turn resulting in a mismatch between silicon processing capabilities and interconnect performance. Optical I/O over the entire chip area is pursued as a solution to these interconnection problems in the European Community funded ESPRIT project OIIC ("Optically Interconnected Integrated Circuits"). In this approach, data transfer from the whole chip area is facilitated through two dimensional arrays (array pitch: 250 /spl mu/m) of optical channels, consisting of opto-electronic components flip-chip mounted on CMOS circuitry and aligned to passive optical pathways. Data rate objectives are 0.5-1 Gb/s per channel. As a principal choice in this project, a 2D array of small diameter (125 /spl mu/m) Plastic Optical Fibres is used as a flexible transmission medium. The large numerical aperture of this fibre (typically NA=0.5) and its flexibility allow for compact assembly (and hence low head room modules) and relatively coarse alignment.

Designs targeted for FPGAs are becoming increasingly larger and more complex. The need for I/O often surpasses the number of I/O pads that can be provided at the perimeter of the FPGA chip. As a result, these designs have to be implemented in larger FPGAs, the size of which is fired by the number of I/O pads and not by the logic needed, reducing the performance of the implementation. Providing FPGA chips with I/O pads that are spread out across the whole chip area drastically reduces this problem. In this paper, we present a quantitative analysis of the impact of area-I/O in FPGAs.

Besides the actual optical link delay, the mere presence of the optical interconnect also has its impact on the on-chip electrical routing delays. We quantify these delays for a real (small scale) optoelectronic FPGA prototype. Our results indicate that future designs must consider this impact to achieve optimal performance.

Summary form only given. The increasing CMOS-IC complexity in terms of chip size, number of I/O pads and clock frequency poses more and more stringent problems for the system designer to solve, among which the interconnection problems, latency issues and power dissipation of the chips. Optical I/O over the entire chip area is pursued as a possible solution to the interconnection problems in the European Community funded ESPRIT project OIIC (optically interconnected integrated circuits). In this approach, data transfer from the whole chip area is facilitated through two-dimensional arrays of optical channels, consisting of opto-electronic components flip-chip mounted on CMOS circuitry and aligned to passive optical pathways.

Parallel optical interconnects between chips need compact, high-speed, reliable, cheap and efficient components. RCLEDs have been proposed as a light source in such links. Standard drivers for interconnects consist of a switched current source. However, this switching results in slow responses, especially at low current densities. It was found that the current driven RCLEDs need a very large current density to achieve the desired operation speed. This is incompatible with the power budget constraints. Voltage driven RCLEDs had shorter rise and fall times compared to the current driven RCLEDs, which is explained by the peaked current, which fills up the active layer much faster compared to the current driven RCLEDs. In this paper, three different driver designs based on this current peaking principle will be presented. The key feature of the drivers is their ability to generate a peaked current pulse, both at the on-switching and off-switching.

The central issue of optically interconnected integrated circuits (OIIC) concerns the area optical interconnect approach to the interconnect bottleneck encountered in advanced VLSI-CMOS designs. The envisaged route to solving this problem offers throughput data interconnects on inter-chip and MCM level, facilitating implementation of new digital architectures and systems. The OIIC project is aimed towards the realisation of three demonstrators: a system demonstrator, implementing state-of-the-art technology, and two link demonstrators, aiming at a high speed approach with 16 channels (Gigalink), and a low power, high density approach on 100 pm pitch with 100 channels (Photonlink). In the paper, progress and results in the project on architecture, components, optical pathways and mounting techniques for the system demonstrator will be highlighted. This system demonstrator aims at using a smart-pixel like interconnect structure to create a logically 3-D architecture, conceptually consisting of a number of electronic planes (electrical FPGAs), that are interconnected bidirectionally along a regular pattern that runs across the chip surface. The full-custom CMOS FPGA circuit is an 8/spl times/8 array of simple configurable logic blocks (a 4-bit function table, one flip-flop), interconnected by a programmable 6-6 switch matrix fabric, including the access to off-chip optical interconnections. The optical components consist of two 8/spl times/8 source arrays (either LEDs or VCSELs) and two 8/spl times/8 InP detector arrays, which are flip-chip bonded to the CMOS circuit and actually overlay part of the CMOS circuits. Electronic driving and receiving circuits are realised in CMOS, and are intermixed with the digital circuits. Each of the 256 optical channels is designed to operate at an information rate of 80 Mbit/s. To ensure reliable communication over so many parallel channels in a noisy digital environment, AC-coupled communication with Manchester coded data is used in the design. The optical pathways between the central chip and its two neighbours consists of removable 8/spl times/16 POF ribbons. Preliminary tests of the CMOS functionality have been completed with good results. A methodology for hybrid assembly, packaging and passive alignment of all components has been implemented. The hybridisation and packaging steps of the CMOS chips and the optical components, final assembly and measurements are discussed.

In the process of designing complex chips and systems, the use of benchmark designs is often necessary. However, the existing benchmark suites are not sufficient for the evaluation of new architectures and EDA tools; synthetic benchmark circuits are a viable alternative. In this paper, a systematic approach for the generation and evaluation of synthetic benchmark circuits is presented. A number of existing benchmark generation methods are examined using direct validation of size and topological parameters. This exposes certain features and drawbacks of the different methods.

Though it has become one of the most popular techniques for a priori wirelength estimation, Donath's method is heavily constrained by the underlying circuit and architecture models. In this paper, we propose analytical and numerical extensions to this model to overcome some of these constraints. It turns out that, with our extensions, Donath's model correlates very well with experimental data. This makes it particularly well suited for, among others, the parametric exploration of placement options.

A priori wirelength estimates are based on a terminal-gate relationship known as Rent's rule. Conventional models apply Rent's rule in 2D on square or diamond-shaped regions. However, more advanced applications of wirelength estimation require the use of Rent's rule on layout regions with different shapes. In this paper, we systematically study the layout Rent parameters of rectangular regions in a 2D layout medium. For this purpose, we derive a theoretical model for the pin versus gate relationship for layout regions of any given shape. Using this model to find an estimation of the layout Rent parameters of rectangular regions with a given aspect ratio, we show that there is a significant dependency of the Rent coefficient on that aspect ratio. We experimentally verify these results with synthetic, as well as industrial benchmark circuits.Furthermore, our model relates the layout Rent parameters of a circuit to its intrinsic partitioning properties. This leads to a fundamental limit on the value of the layout Rent exponent for circuits, embedded in a 2D layout medium.

The design and fabrication of a digital system demonstrator implementing 2D optical interconnect via a POF ribbon are discussed. This demonstrator implements 256 optical I/O channels per chip. Each chip, a custom FPGA CMOS design, implements digital and analogue functionality.

In this chapter, we address the performance advantage of using optoelectronic area-I/O to realize three-dimensional multi-FPGA architectures. The performance of such architectures strongly depends on the latency of the optoelectronic components used. Determining the optical link latency that is required to benefit from the promised advantage is far from trivial. We present first estimates of the impact of optical interconnect latency on system performance, for a particular class of OE multi-FPGA architectures. Our approach is based on experimental determination of achievable clock rates when realizing synchronous designs. Our experiments indicate that with latencies of state of the art optical links the gains can be positive.

When designing a new micro-architecture, it is difficult to estimate the influence of the architectural parameters on clock period and chip area. In this paper, we use automatic synthesis to investigate the implementation of a novel processor architecture, namely a block structured instruction set architecture (BSA). In a BSA, instructions are statically grouped into fixed-length blocks by the compiler and the execution policy within a block is data-flow. The use of automatic synthesis is forced by the fact that a broad design space is investigated in an early design stage. The three parameters that we specifically focus on are blocksize, instruction selection window size and issue width. Various pipeline configurations are investigated. Moreover, we investigate the effect of technology scaling on the selection of the best architecture and pipeline configuration; we consider both a 0.8 /spl mu/m 2-metal layer CMOS technology and a more advanced 0.25 /spl mu/m 6-metal layer CMOS technology. From this paper we can conclude that a BSA has several implementational benefits over traditional architectures due to the partitioned design and the reduced wiring delays.

In this paper, we give an overview of the capabilities of GART (Generic Architecture Research Tool). This tool enables the user to research the effect of architectural parameters on the implementation of designs in different FPGA architectures. It allows the definition of, and the placement and routing of designs in a broad range of FPGA architectures. The graphical input format used for defining the target FPGA architecture and the associated placement and routing algorithms ensure a flexibility that surpasses comparable tools [1,2] by allowing (among others) direct connects, segmented routing structures, area-I/O and 3-D architectures. A preliminary evaluation of some example architectures containing direct connects is given to demonstrate the usefulness and the versatility of GART. The full paper will contain a more elaborate set of experiments.

We present a rigorous comparison between Si ring modulators based on interdigitated and lateral p-n junctions. A detailed Si ring modulator model is derived, which is used to fit and benchmark the measured modulation performance of both ring modulators. At 10 Gb/s and 1 Vpp drive swing, the interdigitated ring modulator is found to exhibit a superior extinction ratio at low insertion loss as compared to the lateral ring modulator, at the expense of a higher capacitive load. Design improvements are proposed to obtain 25-Gb/s operation with similar extinction ratio and low insertion loss in future devices. Such devices are attractive to enable power-efficient scaling of optical interconnects to 400 Gb/s and beyond.

A surface-illuminated photoconductive detector based on Ge0.91Sn0.09 quantum wells with Ge barriers grown on a silicon substrate is demonstrated. Photodetection up to 2.2µm is achieved with a responsivity of 0.1 A/W for 5V bias. The spectral absorption characteristics are analyzed as a function of the GeSn/Ge heterostructure parameters. This work demonstrates that GeSn/Ge heterostructures can be used to developed SOI waveguide integrated photodetectors for short-wave infrared applications.

As the availability at low cost of array components is of crucial importance for the large-scale application of a number of parallel optical interconnect schemes, considerable research effort has been spent to design and model source-arrays offering properly shaped, collimated beams.1,2 In this framework, LED-arrays with diffractive lenses etched into the rear substrate side were fabricated for a board-to-board (a few mm) highly parallel (pitch 250 µm to 500 µm) free-space optical interconnect application (Fig. 1). The diffractive lenses were designed to image the LEDs at a distance of 2.5 mm behind the lens plane.

The algorithm presented in this paper constructs a geometric model of the environment using ultrasonic sensors. To do this in a reliable way, it has to take different error sources into account. Unlike other approaches, where a low-level, pixel based, probabilistic model is constructed to represent the uncertainty arising from false measurements, a high level, geometric, model is constructed. It is shown that a high level model, besides being faster to construct, is more appropriate for taking into account the typical characteristics of ultrasonic sensors. The algorithm detects and eliminates inconsistent measurements by combining evidence gathered from different points of view. This is made possible by extracting from the measurements not only information concerning the position of obstacles, but also information about regions that must be empty when seen from a certain angle. To conclude, some examples of the behaviour of this algorithm in real-world situations are presented.

A compact, electrically driven light source integrated on silicon is a key component for large-scale integration of electronic and photonic integrated circuits. Here we demonstrate electrically injected continuous-wave lasing in InP-based microdisk lasers coupled to a sub-micron silicon wire waveguide, fabricated through heterogeneous integration of InP on silicon-on-insulator (SOI). The InP-based microdisk has a diameter of 7.5 mum and a thickness of 1 mum. A tunnel junction was incorporated to efficiently contact the p-side of the pn-junction. The laser emits at 1.6 mum, with a threshold current as low as 0.5 mA under continuous-wave operation at room temperature, and a threshold voltage of 1.65 V. The SOI-coupled laser slope efficiency was estimated to be 30 muW/mA, with a maximum unidirectional output power of 10 muW.

A new approach for an electrically driven microlaser based on a microdisk transferred onto Silicon is proposed. The structure is based on a quaternary InGaAsP p-i-n junction including three InAsP quantum wells, on a thin membrane transferred onto silicon by molecular bonding. A p++/n++ tunnel junction is used as the p-type contact. The technological procedure is described and first experimental results show a laser emission in pulsed regime at room temperature, with a threshold current near 1.5 mA.

For the compact integration of photonic circuits, wavelength-scale structures with a high index contrast are a key requirement. We developed a fabrication process for these nanophotonic structures in Silicon-on-insulator using CMOS processing techniques based on deep UV lithography. We have fabricated both photonic wires and photonic crystal waveguides and show that, with the same fabrication technique, photonic wires have much less propagation loss than photonic crystal waveguides. Measurements show losses of 0.24dB/mm for photonic wires, and 7.5dB/mm for photonic crystal waveguides. To tackle the coupling to fiber, we studied and fabricated vertical fiber couplers with coupling efficiencies of over 21%. In addition, we demonstrate integrated compact spot-size converters with a mode-to-mode coupling efficiency of over 70%.

Pituitary responses to 100 mcg. of luteinizing hormone-releasing hormone (LH-RH) administered subcutaneously were studied in 34 cases of amenorrhea or anovulatory oligomenorrhea associated with galactorrhea. Twenty-six patients had pituitary prolactin-secreting tumors (group I); eight patients had a normal sella turcica and remission of the syndrome either spontaneously or after thyroid replacement therapy (group 2). Follicle-stimulating hormone (FSH) and luteinizing hormone (LH) responses to LH-RH were variable in each group of patients, ranging from poor to exaggerated, and no statistically significant difference could be observed between the groups. A positive correlation was found between FSH pituitary responses and basal FSH levels (r=0.50; P less than 0.01). No positive correlation was observed between either LH responses and basal LH levels or the gonadotropin responses and plasma estradiol levels, serum prolactin concentrations, duration of amenorrhea, or size of the tumor.

It is well-known that maximum entropy distributions, subject to appropriate moment constraints, arise in physics and mathematics. In an attempt to find a physical reason for the appearance of maximum entropy distributions, the following theorem is offered. The conditional distribution of X_{l} given the empirical observation (1/n)\sum^{n}_{i}=_{l}h(X_{i})=\alpha , where X_{1},X_{2}, \cdots are independent identically distributed random variables with common density g converges to f_{\lambda}(x)=e^{\lambda^{t}h(X)}g(x) (Suitably normalized), where \lambda is chosen to satisfy \int f_{lambda}(x)h(x)dx= \alpha . Thus the conditional distribution of a given random variable X is the (normalized) product of the maximum entropy distribution and the initial distribution. This distribution is the maximum entropy distribution when g is uniform. The proof of this and related results relies heavily on the work of Zabell and Lanford.

A piezoelectric pulsed drop jet device has been developed to produce deposits for nuclear measurements. Details are given concerning the construction and performance of the drop generator, the construction of a positioning mechanism and the developement of a steering system (based on a TRS 80 microcomputer). The complete system can produce rectangular and circular deposits of various dimensions and thicknesses. 235 U acetate deposits have been prepared in thicknesses varying from 10 μg/cm 2 to 2 mg/cm 2 and their quality is evaluated.

Real-time control applications pose particular implementation difficulties, caused by the required low latency to external events, the highly concurrent nature of the application software, and the reliability requirements usually associated with control. The implementation of concurrent real-time software is typically done at the machine language level, which is difficult, costly and non-portable. In this paper, we propose a shared-memory multiprocessor realisation of Modula-2 as a possible high-level language environment for real-time control applications. The implementation is well suited to support dynamic processor allocation and quick runtime response to external events.

Twenty-five cases of congenital absence of the vagina have been reviewed. The clinical syndromes encountered include simple absence of the vagina, male pseudohermaphroditism., and Rokitansky-Kuster-Hauser synrdrome. Complete physical and laparotomy data are detailed in 14 cases. The surgical procedures and their results are evaluated in 19 cases. The McIndoe procedure and its modification by Counseller are the procedures of choice in vaginal reconstruction. Laparotomy should be a routine procedure prior to vaginal reconstruction.

Numerous studies involving the administration of natural or synthetic HL-RH to normal subjects and to patients with various endocrinopathies have been published in the past few years. A recent review summarizes some of the available data (Yen, 1975).

We have given danazol to 25 women with mammary dysplasia. Clinical, cytologic and radiographic examinations were made before, during and after this treatment. In 23 patients breast pain disappeared completely. Danazol produced such a decrease in breast volume and density that on the mammogram the parenchyma was much more easily visualized. We suggest that danazol might be given before mammography to high risk women having dense dysplasic breasts, in order to ensure easier and more accurate interpretation.

The histologic pattern of the endometrium was studied in 38 patients, 19 to 44 years old, with primary hypoestrogenic amenorrhea treated by estrogen replacement therapy. At the time of endometrial biopsy 3 patients were receiving estrogens only and 35 patients were taking 1 of the following cyclic estrogen-progestogen combinations: 1) conjugated estrogens, 1.25 or 2.5 mg per day, combined with medroxyprogesterone, 5 or 10 mg for the last 5 to 10 days; 2) ethinyl estradiol, 50 microgram per day, combined with medroxyprogesterone, 5 mg per day for the last 5 days; or 3) mestranol, 40 microgram per day, in combination with norethindrone, 0.5 mg for the last 7 days. Evidence of endometrial hyperplasia was found in 3 patients. Two of them were taking unopposed estrogens and developed cystic hyperplasia; the other patient, treated with norethindrone in addition to mestranol, disclosed focal cystic glandular hyperplasia. This study and the review of the available data reported in the literature on the endometrial response to estrogen therapy in patients with gonadal dysgenesis stress the importance of appropriate estrogen and progestogen dosage to avoid the hazards of abnormal endometrial pattern in young patients receiving estrogen replacement therapy.

Plasma prostaglandins F2 alpha and E (PGF2 alpha, PGE) and urinary PGE were measured in 10 women treated with human gonadotropins (HMG) and subsequently with human chorionic gonadotropins (HCG). Five women became pregnant (6 pregnancies). There was no correlation between concentrations of plasma PGF2 alpha or PGE and plasma estradiol or progesterone. Urinary PGE concentrations showed a positive correlation with estradiol before HCG and a negative correlation with progesterone after HCG, only in women who subsequently became pregnant. Higher urinary PGE concentrations before HCG suggest that either HMG or rising estradiol levels stimulate PGE renal production. The significant negative correlation between urinary PGE and progesterone concentrations, after HCG, in those patients who became pregnant suggests that ovarian production of progesterone may decrease renal production of PGE.

Fifteen patients, 11 female and four male, with primary selective pituitary deficiency in gonadotropins were submitted to the subcutaneous administration of 100 to 400 mcg. of luteinizing hormone-releasing hormone (LH-RH). When compared to the effect of LH-RH in eight normal female subjects, two types of responses were observed: there were either small increments in both luteinizing hormone (LH) and follicle-stimulating hormone (FSH) or increases comparable to those observed in normal subjects. Five patients received 100 mcg. of LH-RH daily over four consecutive days. No additive nor depleting effects could be observed. The responses in seven patients given 400 mcg. were not significantly different from those obtained with 100 mcg. Our results indicate two possible etiologies of primary hypogonadotropic hypogonadism. A normal response in LH and FSH after administration of LH-RH assesses a selective hypothalamic deficit in releasing hormones, whereas a negative or low response suggests a dysfunction of the pituitary gonadotropic cell.

Thirty-seven infertile patients with ovulatory defects have been treated with cisclomiphene at dosages varying from 10 to 140 mg. per day. The over-all ovulatory rate was 78.1 per cent with a pregnancy rate of 51.3 per cent. The results of our investigation with cisclomiphene are presented in detail and are compared with our previous experience with clomiphene. It seems that the ovulatory rate is similar for the two compounds but that the pregnancy rate is much higher with cisclomiphene. The dosage of 10 mg. of cisclomiphene is effective but might have to be increased according to the patient's response. It appears that 10 and 20 mg. of cisclomiphene, respectively, are as effective as 50 and 100 mg. of clomiphene citrate.