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Hierarchical test generation with built-in fault diagnosis
- Source :
- Asian Test Symposium
- Publication Year :
- 2002
- Publisher :
- IEEE Comput. Soc. Press, 2002.
-
Abstract
- A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from the start. An efficient test compaction method leads to a very compact test set, while retaining a maximum of diagnostic power and a 100% fault coverage for non-fanout circuits. An extension for fanout circuits is also presented.
- Subjects :
- Combinational logic
Engineering
business.industry
Test compression
Hardware_PERFORMANCEANDRELIABILITY
Automatic test pattern generation
Fault (power engineering)
Reliability engineering
Stuck-at fault
Application-specific integrated circuit
Test set
Fault coverage
Hardware_INTEGRATEDCIRCUITS
business
Hardware_LOGICDESIGN
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- Proceedings of the Fifth Asian Test Symposium (ATS'96)
- Accession number :
- edsair.doi...........41139d1d8cf52d9476034c961d5de166