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In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility ($\mu _{\text {eff}}$) of 160 cm2/ $\text {V} \cdot \text {s}$ was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher ${V}_{\text {th}}$ tunability and improvement of $\mu _{\text {eff}}$ by bottom-gate biasing. [ABSTRACT FROM AUTHOR]

High-gain millimeter-wave monolithic integrated circuit (MMIC) amplifiers have been developed, based on a planar metamorphic 20-nm gate length InGaAs metal–oxide–semiconductor high-electron-mobility transistor (MOSHEMT) technology on Si. Therefore, an Al2O3/HfO2 layer stack was deposited as a gate dielectric directly on top of an In0.8Ga0.2As channel by atomic layer deposition. The III–V heterostructure was epitaxial grown on a GaAs wafer and subsequently direct wafer bonded to a Si substrate, leading to a high-quality III–V channel formation on Si. The gate layout was optimized for millimeter-wave and submillimeter-wave integrated circuit applications using T-gates and wet chemical recess etching to minimize the parasitic gate capacitances. For a $2 \times 10 \,\,\mu \text{m}$ gate width transistor, a transit frequency $\text{f}_{\textrm {T}}$ of 200 GHz and a record maximum oscillation frequency $\text{f}_{\textrm {max}}$ of 640 GHz were extrapolated. A realized three-stage cascode amplifier circuit demonstrated a maximum gain of 21 dB at 278 GHz and a small-signal gain of more than 17 dB between 222 and 284 GHz. The total chip size of the millimeter-wave amplifier MMIC was only $0.5\,\,\times \,\,1.2$ mm2. To verify the RF performance of the III–V MOSHEMT on Si technology, all devices and circuits have been reproduced using an InGaAs MOSHEMT on GaAs technology, which has been processed simultaneously within the same wafer batch and achieved almost identical results. [ABSTRACT FROM AUTHOR]

The concept of hydrogel-mediated semiconductor wafer bonding was proposed and demonstrated in this work. The unique property of hydrogels was utilized to simultaneously realize high mechanical stability, electrical conductivity, and optical transparency in semiconductor interfaces. The high applicability of this method for rough surfaces to be bonded was also demonstrated, owing to the soft, deformable interfacial contact agent to be solidified in the bonding process. Furthermore, the bonding experiments were carried out in ambient air at room temperature, which, therefore, provides cost and throughput advantages in device production. In addition, the developed bonding technique was used for demonstrating the fabrication and operation of solar cell devices, with current paths across the bonded interfaces, which verified the method's practical applicability. Our semiconductor bonding and interfacial engineering scheme are expected to open up a pathway for simple, handy, and low-cost, but flexible and high-performance optoelectronic material integration. [ABSTRACT FROM AUTHOR]

Wafer bonding can be substituted for heteroepitaxy when manufacturing specific heterojunction-based devices. Devices manufactured using wafer bonding include multijunction solar cells, integrated sensors, heterogeneously integrated photonic devices on Si (such as high-performance laser diodes), Mach-Zehnder modulators, photodetectors, optical filters, and surface acoustic wave devices. In these devices, creating heterointerfaces between different semiconductors with heavily mismatched lattice constants and/or significant thermal expansion mismatch presents significant challenges for heteroepitaxial growth. High costs and poor yields in heavily mismatched heteroepitaxy can be addressed by wafer bonding in these optoelectronic devices and sensors, including the LiTaO3/Si and LiTaO3/SiO2 heterostructures. In the present work, heterostructure formation between piezoelectric LiTaO3 (100) and Si (100) and α-quartz SiO2 (100) is investigated via wafer bonding. Direct bonding is selected instead of heteroepitaxy due to a significant thermal expansion mismatch between LiTaO3 and Si-based materials. The coefficient of thermal expansion (CTE) of LiTaO3 is 18.3 × 10−6/K. This is 1 order of magnitude larger than the CTE for Si, 2.6–2.77 × 10−6/K and 25–30 times larger than the CTE for fused SiO2 and quartz (which ranges 0.54–0.76 × 10−6/K). Thus, even at 200 °C, a 4 in. LiTaO3/Si bonded pair would delaminate with LiTaO3 expanding 300 μm in length while Si would expand only by 40 μm. Therefore, direct wafer bonding of LiTaO3/Si and LiTaO3/SiO2 is investigated with low temperature (T < 500 K) Nano-Bonding™, which uses surface energy engineering (SEE). SEE is guided by fast, high statistics surface energy measurements using three liquid contact angle analysis, the van Oss/van Oss–Chaudhury–Good theory, and a new, fast Drop Reflection Operative Program analysis algorithm. Bonding hydrophobic LiTaO3 to hydrophilic Si or SiO2 is found to be more effective than hydrophilic LiTaO3 to hydrophobic Si or SiO2 temperatures for processing LiTaO3 are limited by thermal decomposition LiTaO3 into Ta2O5 at T ≥ 180 °C due to Li out-diffusion as much as by LiTaO3 fractures due to thermal mismatch. [ABSTRACT FROM AUTHOR]

Monolithic two‐terminal III‐V on Si dual‐junction solar cells, designed for low concentration applications, were fabricated by means of surface‐activated direct wafer bonding. The III‐V top cell is a heterojunction formed by an n‐Ga0.5In0.5P emitter and a p‐Al0.2Ga0.8As base. An efficiency of 21.1 ± 1.5% at one sun and 23.7 ± 1.7% at 10 suns is demonstrated, which to our knowledge is the best dual‐junction two‐terminal III‐V on Si tandem cell efficiency reported to date under verified reference conditions. The I‐V characterization of these 1‐cm2 tandem cells under concentration required the development of a new method using a single‐source multiflash solar simulator and not perfectly matched component cells, also known as pseudo‐isotypes, formed by Si single‐junction cells and optical filters. In addition, the spectrum of the pulsed solar simulator was measured using a high‐speed CMOS spectrometer, allowing the calculation of the spectral mismatch correction factor. Merging these two techniques results in the hybrid corrected pseudo‐isotype (HCPI) characterization method, which shows a fast and accurate performance with a simplified procedure based on a single‐source solar simulator. Pseudo‐isotypes are easily adaptable to new cell designs by simply using a different filter, hence allowing the characterization of new multijunction solar cell architectures. [ABSTRACT FROM AUTHOR]

In this paper we reported the electrical and spectral properties of 1 MeV electron and 3 MeV proton irradiated In0.53Ga0.47As single junction solar cell, which is used as the fourth subcell of wafer bonded GaInP/GaAs//InGaAsP/InGaAs four-junction full spectra solar cell. The equivalent displacement damage dose model was applied to study the radiation effects of solar cell. The results show that the electrical parameters of the solar cell degrade seriously with the increase of irradiation fluences, the reduction of minority carrier life-time and changes of series and shunt resistance caused by irradiation-induced displacement damage are the main reason for the degradation of cell performance. Degradation of spectral response mainly occurred in the long wavelength region of solar cell due to the bigger displacement damage in the base layer of solar cell. Degradation properties of solar cell by electron and proton irradiation can be predicted by electron to proton damage equivalency factor Rep. [ABSTRACT FROM AUTHOR]

With the rise of hybrid bonding as a solution for fine pitch 3-D integration, new methods are required to evaluate the bonding quality at a wafer level. Contact resistance is widely used for process control but measurements can be corrupted by the 3-D stack complexity and the misalignment of wafers. In order to measure the specific contact resistivity of dual-damascene interconnects and evaluate the Cu/Cu bonding interface, 3-D cross Kelvin resistors (3-D CKRs) have been specially designed. Electrical characterizations and complementary simulations demonstrate that test structures are functional if the specific contact resistivity is higher than $10^{-{8}}\,\,\Omega \cdot \textsf {cm}^{{2}}$. Despite bonding defects evidenced by morphological characterization, the specific contact resistivity remained below the measurement limit. The good reconstruction of Cu/Cu interface does not allow contact resistance measurement. [ABSTRACT FROM AUTHOR]

Inverted metamorphic (IMM) multijunction solar cells represent a promising material platform for ultrahigh efficiency photovoltaic systems (UHPVs) with a clear pathway to beyond 50% efficiency. The conventional device processing of IMM solar cells, however, typically involves wafer bonding of a centimeter‐scale die and destructive substrate removal, thereby imposing severe restrictions in achievable cell size, type of module substrate, spatial layout, as well as cost effectiveness. Here, we report material design and fabrication strategies for microscale triple‐junction IMM (3J IMM) Ga0.51In0.49P/GaAs/In0.26Ga0.74As solar cells that can overcome these difficulties. Specialized schemes of delineation and undercut etching enable the defect‐free release of microscale IMM solar cells and printed assemblies on a glass substrate in a manner that preserves the growth substrate, where efficiencies of 27.3% and 33.9% are demonstrated at simulated AM1.5D one‐ and 351 sun illumination, respectively. A composite carrier substrate where released IMM microcells are formed in fully functional, print‐ready configurations allows high‐throughput transfer printing of individual IMM microcells in a programmable spatial layout on versatile choices of module substrate, all desired for CPV applications. [ABSTRACT FROM AUTHOR]

The grating coupled GaAs/AlGaAs quantum well infrared photodetectors (QWIPs) are integrated onto Si substrates using metal wafer bonding and epitaxial lift-off process. The 1 μm depth of hexagonal hole structure of grating was formed. The energy-dispersive x-ray spectroscopy results confirmed that the grating coupled QWIP is successfully mounted on an Si substrate. By evaluating the Raman spectra, PL, and surface roughness of bonded QWIP samples, the authors found that the grating does not induce any change in the optical or structural characteristics of actual QWIP layers. The dark current–voltage characteristics show a nearly identical dark current level between grating coupled QWIP and nongrating QWIP. The photocurrent spectrum shows that the peak photocurrent intensity of grating coupled QWIP is about 16 times higher than that of nongrating QWIP. This indicates that the grating effectively contributes to an increase in the light absorption of QWIP, showing large room for improvement of QWIP performance by further optimization of a grating structure. [ABSTRACT FROM AUTHOR]

We report a potential method for the fabrication of Si-based Ge film with low threading dislocation (TD) density (<105 cm−2) based on a low-temperature Ge/Si wafer bonding and smart cut technique. This method may replace the traditional epitaxial growth to solve the problems related to the TDs, high temperature, and high vacuum. A near-bubble-free Ge/Si bonded interface is achieved for the fabrication of Ge/Si p-i-n photodiodes. The insertion of amorphous Ge (a-Ge) has crystallized after Ge layer exfoliation, achieving a small FWHMXRD (96 arcsec) of the Ge peak. This determines the low dark current density (5.97 mA/cm2) and low ideality factor (1.19) of the Ge/Si p-i-n photodiode. The exfoliated Ge film suffers from in-plane compression strain due to the expansion of the H2 gas during the blistering process. Interestingly, the in-plane compression strain turns into tensile strain after high-temperature postannealing due to the faster shrinkage rate of Ge during cooling. The in-plane tensile strain leads to the increase in the responsivity of the photodiode. The responsivity of the photodiode at 1310 nm increases from 0.505 to 0.71 A/W and that at 1550 nm increases from 0.244 to 0.524 A/W after postannealing. More importantly, the redshift of the absorption edge of the Ge/Si photodiode (0.1 A/W at 1630 nm) is also observed. This implies that the wafer-bonded Ge/Si p-i-n photodiode can be comparable with the epitaxial one and can be used for optical communication in all wavelength division multiplexing bands, including the ${L}$ -band (1565–1625 nm) and entire ${C}$ -band (1530–1565 nm). [ABSTRACT FROM AUTHOR]

This paper presents a low-temperature process to transfer devices on ultrathin silicon layers from a parent substrate to a foreign substrate or stack. MOS devices were fabricated on silicon-on-insulator (SOI) wafer. The device wafer was then temporarily bonded on a carrier wafer. The handle layer was etched and the remaining ultrathin silicon device layer of ~1.4 $\mu \text{m}$ was transferred to a foreign substrate using permanent bonding. Here, we explored two different bonding approaches, namely, 1) the gold–indium (Au–In) transient liquid phase (TLP) bonding and 2) the epoxy bonding. We demonstrate the advantages of epoxy bonding method over the TLP method. The unique characteristic of this epoxy bonding approach is its capability to vertically stack multiple thin silicon layers. Furthermore, we demonstrate three-layer stacking of the ultrathin silicon layers with functional metal–oxide–semiconductor field-effect transistors in each layer. Electrical characterization results of nMOS/pMOS devices in each layer is presented and compared for before and after transfer. Changes in measured device performance before and after stacking are studied using simulations. The maximum process temperature in this approach is 150 °C, which is considerably lower than those reported in the literature. This result demonstrates the feasibility of multilayer low-temperature stacking. [ABSTRACT FROM AUTHOR]

We propose a new simple and low-cost alignment method utilizing electric contact for die stacking on an interposer or a printed circuit board. Without any expensive aligning/bonding equipment assisted by microscopy, we successfully stacked and bonded two silicon dies on a printed circuit board achieving alignment accuracy of $20~\mu \text{m}$ by utilizing only cheap equipment: manual micropositioners, a stage, a stand, a heat gun, a hot plate, and a power supply. In the proposed method, conductive alignment marks are fabricated on the bonding surfaces, and the electric contact between them are used to characterize misalignment. Therefore, the proposed method does not require any expensive complex microscopy equipment for alignment. In addition, alignment can be quickly and simply examined in situ by detecting electrical conduction during bonding. In experiment, alignment accuracy better than $20~\mu \text{m}$ and 100% bonding yield was measured in testing of 1800 bonds connecting two silicon interposer dies which were stacked on a printed circuit board by the proposed method. [ABSTRACT FROM AUTHOR]

Wafer bonding is an established technology for the manufacturing of silicon-on-insulator (SOI) substrates, micro-electromechanical systems (MEMS) and microfluidic devices. Low temperature direct bonding techniques can be of particular interest for the fabrication of monolithic radiation sensors. Such techniques allow the joining of various absorbers on the backside of thinned CMOS circuity without intermediate layers or through vias. This paper presents a method for the electrical characterization of such bonded interfaces based on the Transient Current Technique (TCT). This method can be extended to the investigation of any type of solid-state devices. [ABSTRACT FROM AUTHOR]

In this brief, a low-cost and high-yield bulk under thin-film (BUT) MEMS technique for the volume production of flow sensors is proposed and developed. The IC-foundry-compatible process is conducted only from the front side of (111) silicon wafers, without double-sided alignment exposure, wafer bonding, cavity silicon on insulator, and double-sided polished wafers needed. With the single-wafer-based BUT structure, the thermopile consisting of 21 pairs of single-crystalline Si/Al thermocouples that show significantly higher Seebeck coefficient and lower noise compared to the traditional poly-Si/Al thermocouples is employed to construct the gas flow sensor, and the fabricated sensor chip size is as small as ${0.65}\,\,\text {mm} \times {0.65}$ mm that facilitates low-cost high-throughput IC-foundry batch fabrication. The fabricated sensor shows a high normalized sensitivity of $199~\mu \text{V}$ /(SLM)/mW for nitrogen gas flow, which is 1 order of magnitude higher than that of the reported thermopile-based gas flow sensor, and a short response time of 3.5 ms could be achieved. With the new technique, the proposed sensors are promising in automotive and process control system applications. [ABSTRACT FROM AUTHOR]

In this paper, a high-thermoresistant temporary bonding/debonding system using spin-on glass (SOG) and hydrogenated amorphous silicon layers is proposed for the multichip-to-wafer (MCtW) 3-D integration based on a via-last/backside-via through-silicon via (TSV) approach. The shear strengths of chips bonded to wafers through the SOG layers are evaluated. In addition, the debonding performance of the chips from the wafers is investigated by using the KrF excimer laser irradiation. Finally, a via-last/backside-via MCtW 3-D integration process using the temporary bonding/debonding system is demonstrated to show the high feasibility with the successful interconnect formation of a Cu-TSVs daisy chain (10 $\mu \text{m}$ in diameter and 50 $\mu \text{m}$ in depth) with a SiO2 liner dielectric deposited by O3-tetraethylorthosilicate chemical vapor deposition at 350 °C. [ABSTRACT FROM AUTHOR]

The hydrophilicity of surfaces and the bonding energy of silicon and sapphire wafers at the temperature of joining 50°C are studied. It is established that heating of the Si and Al2O3 wafers to 50°C is accompanied by an increase in the degree of hydrophilicity of the wafer surfaces. The effect is attributed to improvement in the surface purity due to the desorption of impurity atoms into vacuum and to an increase in the density of dangling bonds. It is found that the bonding energy of silicon and sapphire wafers joined at a temperature of 50°C and upon further heating in the range 100–250°C is higher compared to the bonding energy of wafers joined at room temperature. The activation energy of the growth of the bonding energy is determined. It is found that this activation energy is 0.57 eV. [ABSTRACT FROM AUTHOR]

We have investigated the crystal quality of a 4-inch GaN wafer by X-ray diffraction topography. GaN (112̅4) diffraction images at various incident angles were obtained to determine the image of maximum intensity and full-width at half-maximum (FWHM). The images reconstructed from the maximum intensity at each detector pixel position indicated that the inhomogeneous crystal quality of the wafer originated from seed crystals during wafer manufacturing. The evaluated FWHM distribution tended to increase and become broader from the center to the edge of the wafer. The q-vector components evaluated from the two rocking-curve images at different azimuthal angles combined with the rotation matrix revealed that the overall lattice planes bowed towards the diagonal direction. A histogram on the tilting angle of the wafer showed that the most frequently observed angle was about 0.03°. We expect that our findings could be applied to wafer quality estimation. [ABSTRACT FROM AUTHOR]

Optimization of the mass sensitivity of wafer bonded resonant gravimetric capacitive micromachined ultrasonic transducers (CMUTs) is presented. Gas phase sensors based on resonant gravimetric CMUTs have previously been demonstrated. An important figure of merit of these sensors is the sensitivity which, for typical CMUT geometries, is increased by decreasing the radius of the CMUT cell. This paper investigates how to minimize the radius of CMUT cells fabricated using the wafer bonding process. The design and process parameters affecting the radius of the CMUT and hereby the sensitivity are studied through numerical simulations and atomic force microscopy measurements. An excellent fit was obtained between the simulations and measured profiles with a low relative error of $\leq 5 \%$ , thus validating the simulation model. Two types of CMUTs are designed and fabricated using the design and process rules determined herein, with experimentally determined mass sensitivities of 0.46 Hz/ag and 0.44 Hz/ag, respectively. The two CMUT devices have cavities made using the local oxidation of silicon (LOCOS) and reactive ion etching (RIE) process. For the LOCOS process, it was found that the smallest radius can be obtained by choosing a Si3N4oxidation mask and lowering the pad SiO2thickness, vacuum gap height, and Si bump height. For the RIE process, the vertical dimensions do not influence the horizontal dimensions and consequently, equivalent rules do not exist. [2018-0135] [ABSTRACT FROM AUTHOR]

Hydrogenation-induced cracking in Si/B-doped Si0.70Ge0.30/Si heterostructure with ultralow dose hydrogen implantation (3 × 1016/cm2) is demonstrated. The thickness of the Si0.70Ge0.30 interlayer, embedded between a 240 nm thick Si capping layer and the Si substrate, is 15 nm. After hydrogen implantation, long range H migration and trapping occurred in the Si0.70Ge0.30 interlayer are observed. Moreover, the crack is found to be closely correlated to the concentration of B atoms doped in the buried Si0.70Ge0.30 layer. With increasing B concentrations, the trapped H increases, leading to a smooth cracking confined in the Si0.70Ge0.30/Si interface, and fewer defects are found in the Si capping layer. In conjunction with plasma activation and wafer bonding, the as-transferred Si-on-insulator possesses a rather smooth surface (0.24 nm) and low threading dislocation density (4.4 × 105 cm−2). [ABSTRACT FROM AUTHOR]

A low-temperature wafer-level hybrid bonding process using micro Cu pillar solder bumps and photopatternable dry film adhesive is developed and investigated, where the microbumps and dry film adhesive are simultaneously bonded at a low temperature of 240 °C. The proposed hybrid bonding method has been applied to an 8-in wafer-to-wafer bonding. The effects of two kinds of bonding profiles, i.e., conventional bonding profile and optimized step applying force bonding profile, on post-bonding misalignment are evaluated, and the results show that a misalignment below $5~\mu \text{m}$ is achieved using optimized step applying force bonding profile. In addition, by optimizing the total thickness difference between the bump part and the dry film adhesive part and by increasing the bonding force to 13 KN, a seam-free hybrid bonding interface can be achieved, which shows an average shear strength of about 21.3 MPa. Herein, the proposed method is highly cost-effective and promising for wafer-level low-temperature hybrid bonding aimed at the future 3-D integrated circuit integration. [ABSTRACT FROM AUTHOR]

Metal wafer bonding is being investigated in industry and research fields due to the relatively low process temperatures (T < 500 °C) and, at the same time, to obtain a metallic junction able to offer greater reliability compared with other materials. In this work, electrodeposition of eutectic Sn-Cu alloy, suitable for wafer bonding, was studied using ethylene glycol (EG) as a solvent. The resulting organic electrolyte was used for its promising properties, such as a wider electrochemical window than traditional aqueous electroplating baths. Ethylene glycol solutions containing copper(II) and tin(II) chloride salts were characterised electrochemically by means of cyclic voltammetry (CV) and linear sweep voltammetry (LSV). Deposition was performed both under direct (DC) and pulsed (PC) current conditions and the advantages of the latter are discussed, also in terms of surface morphology as observed by scanning electron microscope (SEM). Wafer bonding was successfully achieved and the interdiffusion of copper and tin species in the bonding region is discussed. [ABSTRACT FROM AUTHOR]

We demonstrate the fabrication of ∼1.08 μm deep microfluidic cavities with characteristic size as large as 7 mm × 11 mm or 11 mm diameter, using a silicon-glass anodic bonding technique that does not require posts to act as separators to define cavity height. Since the phase diagram of 3He is significantly altered under confinement, posts might act as pinning centers for phase boundaries. The previous generation of cavities relied on full wafer-bonding which is more prone to failure and requires dicing post-bonding, whereas these cavities are made by bonding a pre-cut piece of Hoya SD-2 glass to a patterned piece of silicon in which the cavity is defined by etching. Anodic bonding was carried out at 425 °C with 200 V, and we observe that pressurizing the cavity to failure (>30 bars pressure) results in glass breaking, rather than the glass-silicon bond separation. In this article, we discuss the detailed fabrication of the cavity, its edges, and details of the junction between the coin silver fill line and the silicon base of the cavity that enables a low internal-friction joint. This feature is important for mass coupling torsional oscillator experimental assays of the superfluid inertial contribution where a high quality factor (Q) improves frequency resolution. The surface preparation that yields well-characterized smooth surfaces to eliminate pinning sites, the use of transparent glass as a cover permitting optical access, low temperature capability, and attachment of pressure-capable ports for fluid access may be features that are important in other applications. [ABSTRACT FROM AUTHOR]

Micro-electromechanical systems (MEMS) have been developed for sensors and other systems since 1971 at Tohoku University. Ion-sensitive FET (ISFET) probes made by micromachining were commercialized for pH and PCO2 catheters. Special attention was paid to packaging and wafer-level packaging based on glass-to-Si anodic bonding was applied for integrated capacitive pressure sensors, capacitive diaphragm vacuum gauges, MEMS switches, and other devices. Process equipment for not only MEMS but also integrated circuits (ICs) has been made in house because it is important for flexible prototyping and fabrication of novel devices. Equipment for deep reactive ion etching (RIE) of Si was developed and applied for an electrostatically levitated rotational gyroscope and other devices. Heterogeneous integration as MEMS on LSI has been made possible by the transfer of MEMS on a carrier wafer to an LSI wafer or by stacking a MEMS wafer on an LSI wafer using electrical interconnection with a through Si via (TSV). A piezoelectric MEMS switch on an LSI chip, surface acoustic wave (SAW) filters on an LSI chip, a tactile sensor network, and an active matrix electron emitter array are shown as examples of these technologies. [ABSTRACT FROM AUTHOR]

The effect of NH4OH treatment on InP/Al2O3/SOI direct wafer bonding is investigated. The atomic force microscope (AFM) and water contact angle (CA) results reveal a decrease in root-mean-square (RMS) surface roughness and CA of the NH4OH-treated InP wafer. X-ray photoelectron spectroscopy (XPS) analysis is carried out to ascertain the chemical composition of the bonding surfaces. It is found that NH4OH treatment followed by plasma activation increases the content of oxides on the surface of InP wafer. Based on these results, it is concluded that NH4OH treatment helps increase hydrophilicity and contact area of the bonding surface, thus contributing to the success of plasma-assisted InP/Al2O3/SOI wafer bonding. [ABSTRACT FROM AUTHOR]

Impact ionization has been seen to effect pinchoff in wafer-bonded aperture vertical electron transistors (BAVETs) comprising an InGaAs channel wafer-bonded to a III-nitride (III-N) drift region. The InGaAs-III-N junction is referred to as the wafer-bonded interface (WBI). Field plating can work well to manage the peak field and related impact ionization; however, it comes with a tradeoff of increased on resistance. In this paper, another control knob to breakdown is explored in the critical field (ξCRIT_IMPCT) of a BAVET. Investigation focuses on the characteristics of devices that differ in their InAlAs doping profile, namely p-type, unintentional, or a combination of both. These devices are tested for the role of field plate, built-in voltage, and trap behavior on pinchoff. It is shown that the change of doping causes a dramatic change to the trap activity at WBI. These traps ionize and determine ξCRIT_IMPCT as ionization of traps that leads to an early onset of impact ionization in the channel, which weakens pinchoff in a BAVET. Passivating traps is proposed to be a method to improving pinchoff. Trap passivation of WBI is demonstrated if InAlAs is doped p-type rather than unintentionally. A consequent enhancement in pinchoff and breakdown voltage of a BAVET is also reported. [ABSTRACT FROM AUTHOR]

In this brief, we fabricated Ge (110)-oninsulator (-OI) structures on Si substrates via wafer bonding and epitaxial lift-off (ELO) process using Ge layer grown on GaAs for low-temperature layer stacking toward monolithic 3-D integration. We also systematically investigated the lateral etching behaviors of AlAs, which was used as a sacrificial layer in the ELO process, on GaAs (110) substrates. Fabricated Ge (110)-OI was analyzed by surface atomic force microscopy, X-ray diffraction, Raman shift, and transmission electron microscope analyses. We found that the 40-nm-thick ultrathin-body Ge (110)-OI has very high crystal quality, indicating our Ge stacking process is very stable. [ABSTRACT FROM AUTHOR]

The effect of NH4OH treatment on InP/Al2O3/SOI direct wafer bonding is investigated. The atomic force microscope (AFM) and water contact angle (CA) results reveal a decrease in root‐mean‐square (RMS) surface roughness and CA of the NH4OH‐treated InP wafer. X‐ray photoelectron spectroscopy (XPS) analysis is carried out to ascertain the chemical composition of the bonding surfaces. It is found that NH4OH treatment followed by plasma activation increases the content of oxides on the surface of InP wafer. Based on these results, it is concluded that NH4OH treatment helps increase hydrophilicity and contact area of the bonding surface, thus contributing to the success of plasma‐assisted InP/Al2O3/SOI wafer bonding. [ABSTRACT FROM AUTHOR]

Although chip-level heterogeneous integration has high yield for production, low-throughput issue of chip-to-wafer bonding is necessary to be improved. Due to the uneven topography and small chip size, handling issue and alignment accuracy are important factors that impact the difficulty in heterogeneous integration. Self-assembly technology has a high potential to be applied in 3-D heterogeneous integration. By using hydrophobic film to define the stacking area, hydrophilic chips can be assembled to realize alignment process on these areas through wafer surface tension in a very short time. With this concept, double-self-assembly technology is accomplished to resolve both handling and alignment issues for uneven-topography-chip integration. In this paper, different chip sizes of $\mu $ -pillar are simulated to investigate the optimal water volume for double-self-assembly process. High alignment accuracy of misalignment measurement can be accomplished with the optimal water volume. Furthermore, microstructure of Cu/In bonded structures and corresponding electrical analyses are evaluated, while various reliability tests are investigated for bonding quality. Excellent results verify that the double-self-assembly technology could be applied to 3-D heterogeneous integration for uneven-topography-chip integration. [ABSTRACT FROM AUTHOR]

We report a potential low-cost method for low-temperature silicon (Si) and germanium (Ge) wafer bonding based on an intermediate amorphous Ge (a-Ge). The sputtered a-Ge is demonstrated to be extremely flat (RMS = ~0.28 nm) and hydrophilic (contact angle = ~3°). The a-Ge turns to be the polycrystalline phase at the Si/Ge/Si bonded interface, whereas it fully turns to be single-crystal phase at the Ge/Ge/Si bonded interface after annealing. The simulated stress distribution reveals [ABSTRACT FROM AUTHOR]

Integration of heterogeneous materials is crucial for many nanophotonic devices. The integration is often achieved by bonding using polymer adhesives or metals. A much better and cleaner option is direct wafer bonding, but the high annealing temperatures required make it a much less attractive option. Direct wafer bonding relies on a high density of hydroxyl groups on the surfaces, which may be difficult to achieve depending on the materials. Thus, it is a challenge to design a universal wafer bonding process. However, using an intermediate layer between the bonding surfaces reduces the dependence on the bonding materials, and thus, the bonding mechanism essentially remains the same. The authors present a systematic study on the use of Al2O3 as an intermediate layer for bonding of heterogeneous materials. The ability to achieve high hydroxyl group density and well-controlled films makes atomic layer deposited Al2O3 an excellent choice for the intermediate layer. The authors have optimized the bonding process to achieve a high interface energy of 1.7 J/m² for a low temperature annealing of 300 °C. The authors also demonstrate wafer bonding of InP to SiO2 on Si and GaAs to sapphire using the Al2O3 interlayer. [ABSTRACT FROM AUTHOR]

This paper deals with the effect of the silicon bonding temperature with thermoplastic adhesive. The bonding temperature exhibits a significant effect on the morphology and on the adherence energy of the bonded stack. A suitable temperature control leads to an excellent homogeneity of the bonded structure and an optimal total thickness variation (TTV) value. Using Brewer Bsi5150 adhesive material, 275 °C appears as the optimal bonding temperature in order to optimize the TTV from 55 µm down to 5 µm. The adherence of the structure is also increased with high bonding temperatures. Indeed, the adherence energy is above 10 J/m when the temperature is above 250 °C. On the contrary, when the temperature is less than 150 °C, the adherence is only around 1 J/m. Noteworthy, this value is suitable for back side processing and a mechanical debonding of the structure without any need of other specific layer which could lead to a very simple temporary bonding process. [ABSTRACT FROM AUTHOR]

Aluminum-aluminum wafer bonding is becoming increasingly important in the production of CMOS microelectromechanical systems. So far, successful bonding has required extreme processing temperatures of 450 °C or more, because the chemically highly stable oxide layer acts as a diffusion barrier between the two aluminum metallization layers. By using the ComBond system, in which a surface treatment and subsequent wafer bonding are both performed in a high vacuum cluster, for the first time successful Al-Al wafer bonding was possible at a temperature of 150 °C. The bonded interfaces were characterized using C-mode scanning acoustic microscopy and transmission electron microscopy, and featured areas of oxide-free, atomic contact. [ABSTRACT FROM AUTHOR]

A magnetic field pulling-force assisted bonding technology is reported, which is used to bond a mirror plate with a released microactuator using adhesive. This bonding technology is not sensitive to the micromachining process, i.e., any process for microactuator fabrication containing the ferromagnetic structure layer can be used and bonded with a high surface quality mirror plate after released. The conventional wafer bonding technology bonds unreleased actuator with a mirror plate but it limits to the process compatible with the wafer bonding with a releasing step suitable for wafer bonding. Consequently not all processes (such as those mature and commercially available, and those being able to generate large displacement) can be used to fabricate micromirrors. The bonding technology proposed in this paper applies non-touching magnetic field pulling-force, instead of conventional compression mechanical force through touching, to bring the microactutor and a mirror plate in contact for bonding such as to avoid: (1) any plastic deformation or damage to the released micro actuator; and (2) the risk of sticking the actuator moving part to the substrate due to the adhesive squeezed out from the bonding surfaces. The bonding method is introduced and the critical parameters of the bonding method, i.e., distance between the magnet to the actuator is determined through simulations. A bonding mechanism is built and two different designs are bonded. Bonding results are measured, which verifies the bonding method. The bonding is characterized to have a strength of withstanding vibration for a few hours in frequency 20-200 Hz with 2-5 g acceleration and surviving in the temperature of −30 to 80 °C. After bonding a mirror plate with 15.6 m of the curvature radius and 2 nm of the roughness, the bonded micromirror is tested to have a quasi-static displacement of 120 μm. [ABSTRACT FROM AUTHOR]

We analyze the completion time of wafer lots in single-armed cluster tools with parallel processing modules (PMs) by considering the lot switching operation. To effectively assign wafer lots and dispatch overhead hoist transports (OHTs) to manufacturing tools, it is crucial to obtain the completion time of wafer lots. However, estimating the completion time is not straightforward, due to the concurrent processing of two consecutive wafer lots during lot switching operation, which often increases wafer sojourn times in PMs. In this paper, we derive closed-form expressions of the completion time of wafer lots in single-armed cluster tools with parallel PMs. We assume that the robot unloads wafers in the order of their loading sequence. We then experimentally show that the formulas derived can be used even when processing time variation exists or another robot task sequence, which is of first-in first-out (FIFO), is assumed.

Note to Practitioners—Due to the larger wafer size and circuit width reduction, cluster tools often perform the lot switching operation with each pair of consecutive wafer lots. In addition, since most tools are operated with parallel chambers, concurrent processing with two different wafer lots occurs frequently. Such transient periods in operating tools make it hard to estimate the completion time of wafer lots. In this paper, we derive closed-form expressions to obtain the completion time of wafer lots in single-armed cluster tools with parallel chambers. We further show that the formulas can be used with processing time variation or the FIFO rule. With the formulas, OHTs can be sent just-in-time to tools to load or unload wafer cassettes, and wafer lots can be assigned while minimizing the transient periods. In addition, the estimated completion time can be utilized in the planning and scheduling of wafer fabrication processes. [ABSTRACT FROM PUBLISHER]

Defect less semiconductor-on-insulator (-OI) by a cost-effective and low-temperature process is strongly needed for monolithic 3-D integration. Toward this, in this paper, we present a cost-effective fabrication of the indium gallium arsenide-OI structure featuring the direct wafer bonding (DWB) and epitaxial lift-off (ELO) techniques as well as the reuse of the indium phosphide donor wafer. We systematically investigated the effects of the prepatterning of the III–V layer before DWB and surface reforming (hydrophilic) to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. This method provides an excellent crystal quality of In0.53Ga0.47As on Si. Crystal quality of the film was evaluated using Raman spectra, and transmission electron microscope. Finally, we achieved good electrical properties of In0.53Ga0.47As-OI metal-oxide-semiconductor field-effect-transistors fabricated through the proposed DWB and ELO. [ABSTRACT FROM PUBLISHER]

Controllable cracking behaviors are realized in Si with a buried B doped Si0.70Ge0.30 interlayer by tuning the Hþ projected ranges using the traditional H implantation technique. When the projected range is shallower (deeper) than the depth of the buried Si0.70Ge0.30 layer, cracking occurs at the interface between the top Si layer (bottom handle Si wafer) and the Si0.70Ge0.30 interlayer, thus resulting in the formation of continuous sharp crack confined at the Si0.70Ge0.30/Si interfaces. For the case that the H-ion projected range is located at the B-doped Si0.70Ge0.30 buried interlayer, continuous cracking is observed along the interlayer, which is similar to the conventional ion-cut method. We attribute these controlled cracking behaviors to the B doped Si0.70Ge0.30 interlayer, which holds a large amount of B impurities and compressive strain, and H ions can be trapped and confined at the interfaces or within the interlayer (depended on projected ranges) to facilitate the formation of cracks. [ABSTRACT FROM AUTHOR]

The fabrication of a novel class of microgrippers is demonstrated by means of bulk microelectromechanical systems (MEMS) technology using silicon on insulator wafer substrates and deep reactive ion etching. Hard masking is implemented to maximize the selectivity of the bulk etching using sputtered aluminum and aluminum–titanium thin films. The micro-roughness problem related to the use of metal mask is addressed by testing different mask combinations and etching parameters. The O2 flow, SF6 pressure, wafer temperature, and bias power are examined, and the effect of each parameter on micro-masking is assessed. Sidewall damage associated with the use of a metal mask is eliminated by interposing a dielectric layer between silicon substrate and metal mask. Dedicated comb-drive anchors are implemented to etch safely both silicon sides down to the buried oxide, and to preserve the wafer integrity until the final wet release of the completed structures. A first set of complete devices is realized and tested under electrical actuation. [2017-0039] [ABSTRACT FROM PUBLISHER]

The introduction of wafer-bonding technique to capacitive micromachined ultrasonic transducer (CMUT) fabrication offered advantages over the surface micromachining technique, such as simplified fabrication, better membrane uniformity, and increased active area. The conventional wafer-bonding CMUT process employs silicon-on-insulator (SOI) wafers to produce the vibrating membrane layer. However, the use of SOI wafers can lead to poor membrane thickness uniformity despite the high cost. Furthermore, an additional local-oxidation (LOCOS) process should be used for SOI-based wafer bonding process to improve breakdown voltage and reduce parasitic capacitance. This paper reports a nitride-to-oxide bonding process for CMUT fabrication, designed to achieve similar results as the LOCOS-added process reported by Park et al., but without the need for SOIs and fabrication complexity. A fully functional CMUT designed for collapse-mode operation was fabricated and an immersion center frequency was measured to be 4.2 MHz with a 90% bandwidth. [2016-0210] [ABSTRACT FROM PUBLISHER]

Low temperature Ge to SiO wafer bonding based on an intermediate ultra-thin Si layer (1 nm) which is grown on the Ge wafer (Si/Ge) by ultra-high vacuum chemical vapor deposition (UHV/CVD) system is demonstrated in this work. The formation and decomposition of the unstable GeO layer are effectively restrained due to the incomplete oxidation of the covered ultra-thin Si layer after deposition. Therefore, a nearly voids-free bonding interface is observed after post annealing. The hydrophilicity of Si/Ge wafer surface is higher than that of the Ge wafer surface after the treatment of the diluted NHOH solution. The more -OH groups on the Si/Ge wafer surface than that on the Ge wafer surface can be responsible for this feature. As a result, the high bonding strength of 4.39 MPa for the Ge/Si-SiO wafer pairs was achieved due to the formation of more covalent bonds (Si-O-Si) at the bonding interface after post annealing. [ABSTRACT FROM AUTHOR]

A simplified low-temperature wafer-level hybrid bonding process using Cu pillar bumps and photosensitive adhesive was reported, wherein Cu/SnAg/Ni-P micro interconnects were formed to achieve electrical interconnect and the sealing around adhesive played the role of mechanical reinforcement. The proposed hybrid bonding method has been applied to 8 inch wafer to wafer bonding. Two kinds of photosensitive adhesives, i.e., polyimide and dry film, were selected for adhesive bonding. Excess adhesive on the Cu/SnAg micro bumps was properly removed using simple and low cost lithograph process. In order to prevent the adhesive trapping in the metal bonding interface, the height of the Cu/SnAg micro bumps was 2 μm higher than that of the adhesives. Although hybrid bonding using polyimide and dry film can achieve seam free bonding interface, shear test results indicate that bonding strength using dry film is more robust, and dry film is more suitable for hybrid bonding in three-dimensional integration applications. [ABSTRACT FROM AUTHOR]

Iterative phase retrieval has been used to reconstruct the near-field distribution behind tailored X-ray waveguide arrays, by inversion of the measured far-field pattern recorded under fully coherent conditions. It is thereby shown that multi-waveguide interference can be exploited to control the near-field distribution behind the waveguide exit. This can, for example, serve to create a secondary quasi-focal spot outside the waveguide structure. For this proof of concept, an array of seven planar Ni/C waveguides are used, with precisely varied guiding layer thickness and cladding layer thickness, as fabricated by high-precision magnetron sputtering systems. The controlled thickness variations in the range of 0.2 nm results in a desired phase shift of the different waveguide beams. Two kinds of samples, a one-dimensional waveguide array and periodic waveguide multilayers, were fabricated, each consisting of seven C layers as guiding layers and eight Ni layers as cladding layers. These are shown to yield distinctly different near-field patterns. [ABSTRACT FROM AUTHOR]

In order to effectively reduce the thermal stresses of Si/GaAs bonding wafers during their annealing process, first of all, based on E. Suhir’s bimaterial thermal stress theory, the thermal stresses in the wafer bonding interfaces are analyzed and the thermal stress distribution formulas are obtained. Then, the thermal stress distribution curves of Si/GaAs bonding interfaces are investigated by finite element method (FEM) and are compared with the results from E. Suhir’s bimaterial thermal stress theory. Finally, some effective strategies are proposed to reduce the thermal stresses in the bonding interfaces. [ABSTRACT FROM AUTHOR]

We present a varifocal mirror integrated with a comb-drive scanner (varifocal scanner) fabricated by using a wafer bonding technology. An Au-Au thermocompression bonding technology is utilized for the integration. The bonding technology enables fabricating the multiple single crystalline Si layers on a wafer. The varifocal scanner consists of the three Si layers: 1) the fixed comb layer; 2) the scanner frame layer; and 3) the varifocal mirror layer. The 2-mm-diameter and 10-\mu \textm-thick varifocal mirror is fabricated on the 60~\mu \textm thick comb-drive scanner. The focal length modulation range of the varifocal mirror is from −523 to 139 mm at the frequency of 18.3 kHz. The optical angle is 7° at the resonant frequency of 3.59 kHz. The motion couplings between the varifocal mirror and the scanner are also investigated. [2016-0257] [ABSTRACT FROM AUTHOR]

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die-die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance. [ABSTRACT FROM AUTHOR]

The ion-cut technique has been proposed to improve the top Si crystalline quality of the radiation hardened silicon-on-insulator (SOI). Si ion implantation prior to wafer bonding and splitting is performed to reduce the lattice damage induced by direct Si implantation through top Si film. Atomic-resolution transmission electron microscopy studies reveal that the top Si film possesses nearly perfect crystalline quality. Photoluminescence spectroscopy, x-ray photoelectron spectroscopy, and high-resolution transmission electron microscopy have corroborated the existence of the embedded Si nanocrystals. The pseudo-MOS transistors are fabricated on the hardened and unhardened SOI wafers for a quick and effective evaluation on the electrical properties of SOI wafers. The results indicate that the improvement in the total ionizing dose tolerance of the hardened SOI wafer can be attributed to the generation of deep electron and proton traps which reduce the positive charge build-up defects in the buried oxides. [ABSTRACT FROM AUTHOR]

In order to achieve and maintain a high quality factor (high-Q) for the micro resonant pressure sensor, this paper presents a new wafer level package by adopting cross-layer anodic bonding technique of the glass/silicon/silica (GSS) stackable structure and integrated Ti getter. A double-layer structure similar to a silicon-on-insulator (SOI) wafer is formed after the resonant layer and the pressure-sensitive layer are bonded by silicon direct bonding (SDB). In order to form good bonding quality between the pressure-sensitive layer and the glass cap layer, the cross-layer anodic bonding technique is proposed for vacuum package by sputtering Aluminum (Al) on the combination wafer of the pressure-sensitive layer and the resonant layer to achieve electrical interconnection. The model and the bonding effect of this technique are discussed. In addition, in order to enhance the performance of titanium (Ti) getter, the prepared and activation parameters of Ti getter under different sputtering conditions are optimized and discussed. Based on the optimized results, the Ti getter (thickness of 300 nm to 500 nm) is also deposited on the inside of the glass groove by magnetron sputtering to maintain stable quality factor (Q). The Q test of the built testing system shows that the number of resonators with a Q value of more than 10,000 accounts for more than 73% of the total. With an interval of 1.5 years, the Q value of the samples remains almost constant. It proves the proposed cross-layer anodic bonding and getter technique can realize high-Q resonant structure for long-term stable operation. [ABSTRACT FROM AUTHOR]

Advanced wafer-level packaging (WLP) techniques, mainly driven by high-performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology have been widely studied and developed over the last decade for use in various WLP technologies, such as package on package, fan-out integration, and 2.5-D and 3-D integration using throughsilicon- via. Temporary bonding technology enables handling of thinned substrates (<100 µm), which can no longer self-support during backside processing and packaging. Moreover, some applications require the temporary bonding materials to withstand temperatures up to 250°C in high-vacuum conditions, and even up to 350°C or higher during the dopant activation step required for manufacturing power devices. Therefore, a simple yet effective temporary bonding process and material that can survive all the backside processes is highly desired. In this study, a series of formulations based on polar thermoplastics was developed for temporary wafer bonding applications. These materials target high-temperature survivability and improved adhesion to prevent the premature delamination during downstream wafer processing. All these materials provide high thermal stability up to 250°C or higher, and are able to be bonded to carrier wafers treated with release layers, which can be selectively debonded by either mechanical or laser release after backside processing. The material left on device wafer after debonding can be easily cleaned using common industrial solvents. Wafers bonded with these materials demonstrate lower overall stack total thickness variation (<5 μm) after grinding and have successfully passed a 200°C plasma-enhanced chemical vapor deposition (PECVD) process without any delamination during grinding and PECVD processes. [ABSTRACT FROM AUTHOR]