377 results on '"Nourani M"'
Search Results
102. Signal integrity fault analysis using reduced-order modeling
103. Pattern generation and estimation for power supply noise analysis.
104. Ripple-precharge TCAM: a low-power solution for network search engines.
105. High-speed and low-power network search engine using adaptive block-selection scheme.
106. Performance and power analysis of asynchronous pipeline design methods.
107. Efficient prefix cache for network processors.
108. Interconnect test pattern generation algorithm for meeting device and global SSO limits with safe initial vectors.
109. PCAM: a ternary CAM optimized for longest prefix matching tasks.
110. Multiple transition model and enhanced boundary scan architecture to test interconnects for signal integrity.
111. Power-time tradeoff in test scheduling for SoCs.
112. Testing SoC interconnects for signal integrity using boundary scan.
113. TAN: a packet switched network for VLSI testing.
114. HASIL: hardware assisted software-based IP lookup for large routing tables.
115. Power and delay estimation of CMOS inverters using fully analytical approach.
116. A simple yet accurate analytical method for reducing CMOS gates to equivalent inverters.
117. Adiabatic carry look-ahead adder with efficient power clock generator
118. Test pattern generation for signal integrity faults on long interconnects.
119. Testing high-speed SoCs using low-speed ATEs.
120. Signal integrity loss in SoC's interconnects: a diagnosis approach using embedded microprocessor.
121. Reconfigurable memory architecture for scalable IP forwarding engines.
122. Built-in-chip testing of voltage overshoots in high-speed SoCs.
123. Testing interconnects for noise and skew in gigahertz SoCs.
124. Detecting undetectable controller faults using power analysis.
125. Modeling and simulation of real defects using fuzzy logic.
126. Synthesis-for-testability of controller-datapath pairs that use gated clocks.
127. An ILP formulation to optimize test access mechanism in system-on-chip testing.
128. Multi-access integrated memory management for deeply pipelined processors.
129. The effect of gate orientation on fault detection.
130. Stability-based algorithms for high-level synthesis of digital ASICs
131. A multiple clocking scheme for low-power RTL design
132. Microprocessor based testing for core-based system on chip
133. A scheme for integrated controller-datapath fault testing
134. An effective power management scheme for RTL design based on multiple clocks
135. Synthesis of controllers for full testability of integrated datapath-controller pairs.
136. Microprocessor based testing for core-based system on chip.
137. Microprocessor based testing for core-based system on chip.
138. SYNTEST.
139. False path exclusion in delay analysis of RTL-based datapath-controller designs.
140. Parallelism in structural fault testing of embedded cores.
141. A scheme for integrated controller-datapath fault testing.
142. An effective power management scheme for RTL design based on multiple clocks.
143. Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems.
144. Reduced complexity 1-bit high-order digital deltasigma modulator for low-voltage fractional-N frequency synthesis applications.
145. Race-free CMOS pass-gate charge recycling logic (FCPCL) for low power applications.
146. Structural Fault Testing of Embedded Cores Using Pipelining
147. Sulfur mustard induces expression of metallothionein-1A in human airway epithelial cells
148. Effect of TGFβ1 and TIMP2 on disease activity in asthma and COPD
149. Identification of reliable reference genes for quantification of MicroRNAs in serum samples of sulfur mustard-exposed veterans
150. Pre-C mutations of the HBV,Mutants pré-C du VHB
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.