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Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

This paper presents the impact of time dependent dielectric breakdown (TDDB, also called as gate oxide breakdown) failure on nanoscale digital CMOS Circuits. Recently, TDDB for ultra-thin gate oxides has been considered as one of the critical reliability issues which can lead to performance degradation or logic failures in nanoscale CMOS devices. Also, leakage power in the standby mode can be increased significantly. In this paper, TDDB aging effects on large CMOS digital circuits in the 45nm technology are analyzed. Simulation results show that TDDB effect on MOSFET circuits can result in more significant increase of power consumption compared to delay increase.

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method"s accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

Ubiquitous network and wireless sensor networks is being applied in various fields. Located at target areas, node of wireless sensor network uses batteries as a power source. Batteries have a limited energy in sensor network applications. Also, before use, the battery must be charged and It is difficult to replace the battery. Therefore, energy harvesting technology is being researched and being developed for long life of sensor node. Especially, sola energy is being extensively researched. because that can have great amounts of energy than other environmental energy in a short time. In this study, we tested battery charging and recharging, operation of sensor node using Solar Cell. Also, monitoring data gathering and voltage Analysis showed energy harvesting time of Sola Cell battery for sensor node and operation of sensor node.

nanowires were synthesized by a hydrothermal reaction of metallic Y with aqueous solution of LiOH. The morphology and the size of the nanowires changed with varying the volume of the LiOH solution inside the autoclave. nanowires transformed to by a subsequent heat-treatment without morphological change. By a proper control of hydrothermal reaction parameter and heat-treatment, the yield of pure nanowires up to 97% was attained.

This article describes a novel technique for analysing the effects of supply voltage noise on circuit delay for VLSI circuits. Scattering parameters are used to model the supply voltage variation in the frequency domain and to reduce the original power grid and simulation time. The interconnections of the power grid are modelled by RLC passive elements, constant voltage and time-varying current sources. A fast and accurate MOSFET modelling method for a static timing analyser is proposed based on the power grid analysis. A MOSFET logic is modelled in three different regions during transition, and the maximum delay is formulated as a constrained non-linear optimisation problem by considering the power supply noise (inclusive of the IR-drop and the Ldi/dt drop). The proposed technique has been applied to ISCAS85 benchmark circuits redesigned in 45 nm technology. The results are compared to Hspice; they show that the error is within 5% of the Hspice simulation results.

This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIMSOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fanout effect. The proposed timing and leakage power analysis algorithms are implemented in Matlab, Hspice, and C language. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5% compared with random simulation results.

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 M~725 MHz with a multipli-cation range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32㎚ predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440㎒ output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40M~725㎒ with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

GPU (Graphics Processing Unit) is emerging as a key 3D/2D graphics and parallel workload accelerator in various SoC applications. As semiconductor fabrication technology continues to scale, chips (especially those with extremely high transistor counts such as processors) are becoming increasingly vulnerable to faults that could produce unwanted errors in computing. The most severe problem is Silent Data Corruption (SDC) because this fault insidiously generates erroneous outputs without being detected. This paper discusses the characterization of SDC vulnerability of GPU on various GPGPU (General Purpose computing on GPU) workloads.

3D heterogeneous integration (commonly termed as 3DIC) of CPU, GPU and DRAM dies vertically interconnected by a massive number of TSVs (Through-Silicon Vias) is expected to overcome limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability in temperature (i.e., hotspots) is anticipated to result in bit error variation in DRAM die. A novel multi-stage BCH decoder has been proposed to efficiently address this issue in this work. The proposed multi-stage BCH decoder is designed to tolerate upto a certain maximum number of error bits per codeword, which is estimated from the on-line thermal gradient data, to minimize the decoding latency.

Hand detection plays an important role in Human Computer Interaction (HCI). Most of the existing hand detection methods rely on the contour shape of hand after skin color segmentation. Such contour shape based approaches, however, are easily distorted by noises and other skin color segments. In this paper, we present a distance image based approach using CPU-GPU heterogeneous computing. Our experiments demonstrate that our proposed distance image based hand detection is robust and fast, reaching up to 97.32% palm detection rate where 80.36% of cases have more than 3 fingers detected on commodity processors. We also achieved 5.0 times speed-up for 320×240 images, and 17.5 times for 640×480 images.

Internet of Everything (IoE), embedded with microcontrollers and wireless technologies onto a single system on a chip (SoC), are able to be connected with other devices in the cloud. Wearable sensors and RFID are core technologies in IoE. Energy efficiency and miniaturization are the two most critical technical challenges for the hardware implementation of microelectronic systems enabling Internet of Everything. Low-power smart systems on a chip are the key enabling solutions. In this paper, we outline the key hardware components and design challenges of BSN.

This paper presents low power and low jitter phase locked loop (PLL) design using supply regulation and active loop filter (ALF) on 110nm CMOS technology and with 1V supply voltage. The supply voltage is regulated by low-dropout (LDO) regulator. The ALF filters high frequency noise of the VCO control voltage. The LDO regulator provides 0.8V output, −83 dB PSRR with PLL load, 0.578mW power consumption, and 99.8% current efficiency with 40mA load current. The jitter of the PLL without and with LDO regulator is 44.9ps and 4.6ps, respectively.

In this study, condensation heat transfer coefficients (HTCs) were measured on a horizontal plain tube, low fin tube, and Turbo-C tube at the saturated vapor temperature of 39 °C for R22, R407C, and R410A with the wall subcooling of 3–8 °C. R407C, a non-azeotropic refrigerant mixture, exhibited a quite different condensation phenomenon from those of R22 and R410A and its condensation HTCs were up to 50% lower than those of R22. For R407C, as the wall subcooling increased, condensation HTCs decreased on a plain tube while they increased on both low fin and turbo-C tubes. This was due to the lessening effect of the vapor diffusion film with a rapid increase in condensation rate on enhanced tubes. On the other hand, condensation HTCs of R410A, almost an azeotrope, were similar to those of R22. For all refrigerants tested, condensation HTCs of turbo-C tube were the highest among the tubes tested showing a 3–8 times increase as compared to those of a plain tube.

In this work, an efficient hardware architecture of modulo 2n + 1 squarer is proposed and validated. The proposed modulo 2n + 1 squarer use novel compressor designs and sparse tree adders as primitive building blocks for fast low-power operations in three major functional modules including partial products generation module, partial products reduction module and final stage addition module. The resulting modulo 2n + 1 squarer has been implemented in standard CMOS (Complementary Metal-Oxide Semiconductor) cell technology and compared both qualitatively and quantitatively with the existing hardware implementations. The unit gate model analysis and the experimental results show that the proposed implementation is faster and consume less power than existing hardware implementations.

The delay-insensitive Null Convention Logic (NCL) as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level topologies of conventional NCL gates have weakness of logic speed, area overhead or wire complexity. Therefore, this paper proposes a new NCL gates designed at transistor level for high-speed, low area overhead. A 4×4 multiplier using the proposed NCL gates has been compared to the multiplier using conventional NCL gates in terms of delay, area and energy consumption.

In nanometer technology, accurate circuit aging prediction of MOSFET digital circuits caused by aging phenominon is one of the most critical issues for more reliable adaptive tuning system design. This paper proposes a new on-chip aging sensor circuit to predit and detect a circuit failure caused by BTI and HCI aging effects on digital circuits. The proposed circuit is based on timing warning windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur.

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration is proposed for digital controlled DC-DC converters. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

This paper describes technology for diagnosis SoC HDL-models, based on transaction graph. Diagnosis method is focused on decreasing the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. A method for analyzing the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis is given.

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture. The full version of the paper can be found at [1].

This paper presents a CMOS neuron circuit design based on the Hindermarsh-Rose (HR) neuron model. In order to be fabricated in a 0.18㎛ CMOS technology with 1.8V compatible transistors, both time and amplitude scaling of HR neuron model is adopted. This on chip solution also minimizes the power consumption and circuit size, which is ideal for motion control unit of the proposed bio-mimetic micro-robot. Simulation results demonstrate that the proposed CMOS neuron performs the expected waveform with time and amplitude scaled. The chip was fabricated by MagnaChip with an active die area of 1.1㎟ including I/O pads. The experimental results validate the performance of this CMOS neuron.

This paper proposes on-chip process and temperature sensor circuits to find a minimum data retention voltage in nanoscale CMOS systems. The process variation is monitored by the low cost gate tunneling leakage sensor, and the temperature is monitored using a zero temperature coefficient (ZTC) principle. The minimum data-retention voltage of flip-flops for low power operation is generated for different temperature and process corner conditions adaptively using a look-up-table method based on the simple PT monitoring circuits. The proposed circuits are implemented using 45 nm CMOS predictive technology model.

This paper proposes the low-power miniaturized FM transmitter with a built-in antenna for robust short range communications. Recently, short-range wireless communication systems in mobile applications have been researched extensively, and the FM transmitter is one of the most important blocks in the short-range wireless communication systems. The proposed FM transmitter uses FM radio waves to transmit sounds from a mobile system (MP3, PMP, PDA, MP3 Phone et.) to radio or stereo systems within a short distance from the mobile system. The size of the proposed transmitter is 2.6 cm x 2.6 cm x 2.6 cm. The operating voltage of the transmitter is 3.7 V. The proposed system deploys a built-in storage battery and can be operated continuously for 7 hours after fully charging the battery. The transmission frequency of the proposed transmitter is selected as one of three frequencies (88.1 MHz, 88.3 MHz, or 88.5 MHz) depending on utility condition, and the channel separation ability is 40 dB.

For future robotic and prosthetic applications, it is essential to develop a robust and low power artificial skin for detecting the environment through touch. Thus, a sensor interface circuit for the artificial skin also has to be developed to detect the sensor signals and convert them into digital bits. In this paper, a new sensor interface circuit using a 32 nm CNFET technology for an artificial skin sensor is proposed. The artificial skin sensor consists of a nxn matrix using CNFET, and the sensor outputs are connected to a current monitoring circuit proposed as the sensor interface circuit.

Skin sensor is the most critical part for controlling robot sensing behavior. In this paper, we provide circuit implementation and simulation for sensing the pressure in the skin sensor using CMOS and CNFET at 32nm technology node. The proposed scheme can be used as an active matrix like memory element in the skin sensor and it is demonstrated by showing the output image according to the skin sensor's pressure location using Matlab implementation. The circuits are compared with CMOS and CNFET (Carbon Nanotube FET) at different supply voltages to show the feasibility of the scheme. Also, low-leakage circuit technique is applied to the proposed sensing circuit.

This paper proposes a new design of carbon nanotube FETs (CNFETs) based SRAM cell operating in subthreshold region. By using optimum back-gate biasing scheme for each transistor, the proposed SRAM cell achieves the best overall performance considering noise margin, delay and power. Compared with traditional subthreshold CNFET SRAM cell, the proposed SRAM cell increases static voltage noise margin (SVNM) 36%, increases static current noise margin (SINM) 2.5X, and reduces delay 61% with power consumption increasing only 1% for read operation. For write operation, the proposed SRAM cell increases write noise margin (WNM) 2.5X and reduces power consumption and delay 17% and 56% respectively compared with traditional subthreshold CNFET SRAM cell. In terms of total number of nanotubes (area) of CNFET SRAM cell, the proposed subthreshold CNFET SRAM cell can reduce at least half of total number of nanotubes without compromising noise margin, power and delay. New CNFET SRAM cell structure is proposed to dynamically bias each transistor at different operation modes.

This paper presents a novel probability based analysis for leakage power estimation of partially-depleted silicon-on-insulator (PD-SOI) circuits. The proposed leakage power estimation algorithms is implemented in C language, and the proposed methodology is tested by ISCAS85 benchmark circuits designed in 100 nm SOI technology. The results show that the error is within 4% compared with Hspice Monte Carlo simulation results.

PWAM transmitter combines pulse width modulation (PWM) and pulse amplitude modulation (PAM) together to boost the performance of the high speed serial link transceiver. In this paper, two PWAM transmitter architectures are proposed and the performances of them are compared based on the power consumption analysis of the drivers. Bipolar driver is an energy efficient choice for the PWAM scheme. It can save more than half of the driver power consumption. The correct clock scheme for phase selector is also discussed in this work.

This paper presents a novel modeling analysis and simulation of jitter for high speed (several gigabit per second) IO channels in VLSI systems. Jitter components are analyzed and modeled individually. The unique features of the components when they are simultaneously injected are identified through simulation. In this work, the effect of settling time on ISI and the relationship among each jitter component are investigated in depth. The validity of superposition of the jitter components is confirmed.

This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5% difference when comparing to Hspice results.

As technology scales down, it has become one of the most critical issues in aging-tolerant nanoscale MOSFET circuit design to monitor the performance degradation of the circuits under aging stress conditions such as Negative-Bias-Temperature Instability (NBTI) and Hot-Carrier-Injection (HCI). Hence, this paper proposes a novel on-chip circuit to measure the delay degradation of stressed MOSFET digital circuits and digitalize the degradation for aging compensation. A 0.11μm CMOS technology has been used to implement and evaluate the proposed circuits.

Clock grid networks are now common in most high performance microprocessors. This paper presents a new effective modeling and analyzing methodology for clock grid using scattering parameter. It also describes an efficient approach to find the optimum clock gird specification, such as the width and space of the gird metal line. The interconnection of the clock grid is modeled by RC passive elements. The results show that the error is within 10% comparing to Hspice simulation results.

This paper presents a novel statistical characterization methodology for accurate timing analysis for Partially Depleted Silicon-On-Insulator (PD-SOI) digital circuits. The proposed methodology is applied to ISCAS85 benchmarks circuits, and the results show that the error is within 5% comparing to HSpice simulation results.

A method for estimating power consumption of digital CMOS VLSI chips is developed. The method estimates the total power consumption of a chip by analyzing separately for different parts of the chip, which are logic circuit, on chip memory, interconnection, clock distribution, and off chip driving. This method makes it possible to estimate the power consumption of a digital CMOS VLSI chip based on gate count, memory size, and logic circuit. An estimation tool, which is implemented in C language, is created and used to estimate the gate count from Verilog register transfer level (RTL) descriptions