Analysis and Simulation of Jitter for High Speed Channels in VLSI Systems

This paper presents a novel modeling analysis and simulation of jitter for high speed (several gigabit per second) IO channels in VLSI systems. Jitter components are analyzed and modeled individually. The unique features of the components when they are simultaneously injected are identified through simulation. In this work, the effect of settling time on ISI and the relationship among each jitter component are investigated in depth. The validity of superposition of the jitter components is confirmed.