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Spectroscopic ellipsometry (SE) is utilized to measure optical, structural and chemical properties of advanced semiconductor materials. In the case of very thin metal films, the correlation between thickness dependent optical properties and the free electron relaxation time is traced to the change in grain size. Low‐κ dielectric materials were characterized to extract the chemical (molecular bond vibration and carbon content), porous (pore volume fraction and pore size), and mechanical (coefficient of thermal expansion and Young's modulus) properties. SE was also employed to measure the bandgap of high‐κ dielectric thin films and the glass transition temperature of EUV photoresists and under layers. The percentage of curing in adhesive bonding layers used in 3D interconnects and the stress in strain engineered III‐nitride thin films were measured via infrared SE. SE is also an excellent method of measuring thin Silicon on Insulator materials. The shift in transition energies of the critical points in extremely thin silicon‐on‐insulators (ETSOI) were measured using direct space analysis.

High‐resolution X‐ray diffraction (HRXRD) is an established technique for the characterization and metrology of epitaxial thin‐films. However, its use by the silicon semiconductor industry has been limited due to the stringent reliability, spot‐size and throughput requirements for in‐line measurement of product wafers. We have developed a new X‐ray metrology tool (called the JVX 7200) that meets these demands. The tool features a novel HRXRD channel that provides composition, relaxation and thickness information for SiGe and Si:C epitaxial films. It also combines an enhanced X‐ray reflectivity (XRR) channel to provide complementary thickness, density and roughness information on SiGe as well as other front‐end of line (FEOL) films, such as those found in high‐k gate/metal gate (HKMG) stacks. We describe the principles and capabilities of both the HRXRD and XRR channels and provide a comparison with conventional X‐ray systems. Representative data are presented to highlight the capabilities of the new tool.

Extreme ultraviolet (EUV) lithography is the successor to optical lithography and will enable advanced patterning in semiconductor manufacturing processes down to the 8 nm half pitch technology node and beyond. However, before EUV can successfully be inserted into high volume manufacturing a few challenges must be overcome. Central among these remaining challenges is the requirement to produce “defect free” EUV masks. Mask blank defects have been one of the top challenges in the commercialization of extreme ultraviolet (EUV) lithography. To determine defect sources and devise mitigation solutions, detailed characterization of defects is critical. However, small defects pose challenges in metrology scale‐up. SEMATECH has a comprehensive metrology strategy to address any defect larger than a 20 nm core size to obtain solutions for defect‐free EUV mask blanks. SEMATECH's Mask Blank Development Center has been working since 2003 to develop the technology to support defect free EUV mask blanks. Since 2003, EUV mask blank defects have been reduced from 10000 of size greater than 100 nm to about a few tens at size 70 nm. Unfortunately, today's state of the art defect levels are still about 10 to 100 times higher than needed. Closing this gap requires progress in the various processes associated with glass substrate creation and multilayer deposition. That process development improvement in turn relies upon the availability of metrology equipment that can resolve and chemically characterize defects as small as 30 nm. The current defect reduction efforts at SEMATECH have intensively included a focus on inspection and characterization. The facility boasts nearly $100M of metrology hardware, including an FEI Titan TEM, Lasertec M1350 and M7360 tools, an actinic inspection tool, AFM, SPM, and scanning auger capabilities. The newly established Auger tool at SEMATECH can run a standard 6‐inch mask blank and is already providing important information on sub‐100 nm defects on EUV blanks. Complementary to Auger analysis, TEM provides ultimate resolution in the defect imaging of sub‐nanometer structures. Crystalline and phase information generated by this metrology technique also indicates the sources of defects. SEMATECH's TEM capability is further equipped with energy dispersive X‐ray spectroscopy (EDS) and electron energy loss spectroscopy (EELS), which provide higher analytical power than similar techniques in traditional secondary electron microscopy (SEM). This paper will describe SEMATECH's comprehensive effort to develop robust inspection of EUV mask defects. We will discuss the development of hardware and procedures for inspecting particles 70 nm and smaller. This paper will also outline challenges in the metrology of current defects on EUV mask blanks and metrology issues that arise with increasingly smaller defects.

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D through‐silicon‐via (TSV) based technologies are outlined. The paper addresses the growing need in a simulation‐based design verification flow capable to analyze a design of 3D IC stacks and to determine across‐die out‐of‐spec variations in device electrical characteristics caused by the layout and through‐silicon‐via (TSV)/package‐induced mechanical stress. The limited characterization/measurement capabilities for 3D IC stacks and a strict “good die” requirement make this type of analysis critical for the achievement of an acceptable level of functional and parametric yield and reliability. The paper focuses on the development of a design‐for‐manufacturability (DFM) type of methodology for managing mechanical stresses during a sequence of designs of 3D TSV‐based dies, stacks and packages. A set of physics‐based compact models for a multi‐scale simulation to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D TSV technology is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test‐chip devices is presented. A strategy for generation of a simulation feeding data and respective materials characterization approach are proposed, with the goal to generate a database for multi‐scale material parameters of wafer‐level and package‐level structures. For model validation, high‐resolution strain measurements in Si channels of the test‐chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub‐10 nm strain measurements so far.

Si/SiGeC superlattices are used in the construction of new generation devices such as multichannel transistors. The incorporation of C in the SiGe layers allows for a better control of the strain and the Ge content. However the formation of β‐SiC clusters during annealing at high temperature limits the thermal stability of the alloy. It leads to a strong modification of the strain due to the reduction of the substitutional carbon content. Here, we investigated the behavior of Si/SiGeC superlattices that have been annealed using different characterization techniques: dark‐field electron holography for the evaluation of strain; infrared spectroscopy and ToF‐SIMS for the determination of the composition. It was found that after annealing at 1050 °C, the reduction of the substitutional C proportion leads to a recovery of the perpendicular strain in the superlattice. It was also proposed that the local arrangement of C atoms in a third nearest neighbor configuration is an intermediary step during the formation...

The IEC technical committee 113 “Nanotechnology standardization for electrical and electronic products and systems” develops standards to be used in the electrotechnical industry. These standards will address all stages in the life cycle of nano‐enabled electrotechnical products. The focus of the standardization activities is on products whose performance is inherently related to the use of nanomaterials and nanoprocesses. Examples of product groups addressed are nano‐enabled batteries, photovoltaic cells, lightning devices and printed electronics. Currently, the committee concentrates on nanomanufacturing processes and quality management.

In this work, we report a series of Kelvin Force Microscopy (KFM) measurements, suitable to observe the topography and the contact potential difference (CPD) distribution of the following stack: CdTe/CdS/ITO/glass. The sample is prepared by mechanical polishing after cleavage to decrease the roughness. In order to have a better understanding of the charge transport inside the solar cell and to vary the Fermi level pinning effect, different bias are applied to the sample. The CPD variations with different bias on cross‐section in dark condition are presented. We observe the reverse bias widens the CdTe/CdS depletion region. Under illumination, electron and holes are generated near the interface and varies the CPD distribution. Additionally, the chemical composition of each layer has been investigated by nano‐Auger electron spectroscopy (AES). We observe the interdiffusion at the CdTe/CdS interface and determine the composition of the active layers to be CdTe/CdS0.7Te0.3.

This paper collects the results of a study aimed to investigate the impact of organic contamination on the electrical properties of the silicon oxide and of the silicon oxide‐silicon interface. Some wafers were contaminated by immersion in solution of diethylphthalate (DEP) in solvent. The wafers were then oxidized to perform surface recombination velocity measurements by Elymat, and capacitors were fabricated for capacitance vs. voltage and capacitance vs time measurements. In addition, the interface state density was measured by the MOS‐DLTS technique and the gate oxide integrity was evaluated by constant current stress. Elymat measurements of surface recombination velocity show that surface recombination velocity is increased by organic contamination. From the point‐of‐view of the intrinsic properties of the silicon oxide‐silicon interface, MOS‐DLTS showed the most significant effects. These measurements allowed identifying a band of interface states located around Ev +0.1 eV as related to organic cont...

In order to reach high levels of transistor performance, it is desirable to increase electrical conductivity of the device. An efficient way to enhance carrier mobility in the conduction channel is to generate strain in the structure using process‐induced stress. To achieve that, stress engineering of the contact etch stop layer (CESL), an amorphous hydrogenated silicon nitride film deposited by plasma enhanced chemical vapour deposition on top of the metal oxide semiconductor assembly, is widely used since it is a low‐cost technique. Indeed, this film possesses an intrinsic stress that can be set from tensile (σ = 1.6 GPa) to compressive (σ = −3.0 GPa) depending on deposition conditions. From an electrical point of view, strain induced in the silicon channel can lead to an increase of carrier mobility as high as 8–10% which in turn increases Ion/Ioff and decreases switching time of the transistor. Usually, strain induced in the channel is very low (0.1–0.3%), making quantitative measurements challenging....

Scanning Electron Microscopy (SEM) has been a mainstay of critical dimension (CD) metrology since the inception of integrated microelectronics, due to its inherent high resolution capability and relative ease of interpretation. However, as device dimensions continue to shrink, and non‐planar devices become integrated into process flows (e.g., finFETs), the need to identify and develop successor technologies becomes essential. Here, we report progress on the development of two innovative technologies proposed for CD measurement, and assess their viability for high volume manufacturing applications. Finally, we describe recent efforts to extend the life of conventional CD‐SEM.Small Angle X‐ray Scattering (SAXS) also offers Angstrom‐level resolution, is non‐destructive, and requires no additional preparation steps. Performed in either transmission or reflection mode, this method is particularly suitable for arrayed structures and non‐planar devices. Whereas direct imaging methods provide a complete description of a single measurement site, SAXS probes a comparatively large area containing many sites, and effectively provides information on feature dimensions and the statistical variations within the sampled. The chief limitation to implementing CD‐SAXS is throughput, gated by x‐ray source brilliance. Conventional x‐ray tube and rotating anode sources do not have the correct combination of brightness and stability required to obtain rapid, consistent measurements. Recent innovations in x‐ray source technology, including plasma and liquid metal based sources, have shown promise for making CD‐SAXS a viable HVM method.Scatterometry methods offer yet another attractive approach. Advances in the optical components and simulation software enable one to obtain most of the sixteen components of the Mueller Matrix for each wavelength of light instead of the typical Ψ and Δ. This is great importance when measuring highly anisotropic 3D scatterometry test structures.Finally, it is worth considering the efforts to extend the life of CD‐SEM. A series of advances such as drift correct frame averaging and 3D Monte Carlo models that improve metrology for nanoscale features are all under consideration. These improvements push CD‐SEM resolution closer to its theoretical limits. Additionally, the use of contrast transfer functions (CTFs) as an improved means for achieving tool matching and assessing tool performance, is considered. When an image is collected from an ideal test specimen, such as a high resolution Fresnel Zone Plate or a pseudo‐random dot array, the CTF can be used as a measure of the fidelity with which specimen topography is represented in the recorded signal, as a function of spatial frequency. Tuning SEM parameters to manipulate the CTF provides a richer feedback mechanism than simply using nominal resolution and signal‐to‐noise ratio.

The silicidation reaction between a titanium metal film, capped by a TiN layer, and a boron‐implanted silicon substrate has been analyzed by Atom Probe Tomography. Two different thicknesses of titanium metal film were considered to study the process of silicidation and subsequent effects on the redistribution of the dopants. The concentration depth profiles determined by atom probe tomography and secondary ion mass spectrometry depict an additional amorphous TiSix phase for the thicker Ti film in contrast to a fully silicided TiSi2 layer for the thin one. The experimental data shows lower solubility of boron in TiSi2 in comparison to the amorphous TiSix phase. Additionally, boron accumulation at the interface between the TiSi2 and the TiN capping layer is observed. The atom probe study clearly reveals boron precipitates at interfaces between TiSi2 and Si substrate or TiN capping layer. These precipitates can be identified either to a stoichiometric ratio of TiB2 or TiB correlated to the size of the indivi...

The imaging of surfaces using the PhotoElectron Emission Microscopy (PEEM) technique has recently received considerable interest, mainly thanks to the use of high brilliance synchrotron radiation which facilitates the study of surface properties and chemical selectivity. By inserting a transfer lens in the optical column of a high transmission and full energy‐filtering PEEM, it is possible to image the back focal plane, named k‐PEEM imaging mode. Hence, the corresponding image shows the angular distribution of the emitted photoelectrons for a given kinetic energy. By varying the kinetic energy, the complete energy filtering provides full 2D cuts of the band structure in reciprocal space. In this paper, we present the principles and the capabilities of this new imaging mode, and compare it to the standard ARPES technique. Then, we present results obtained on a model sample: Ag(100), and on a technological sample, epitaxial graphene on SiC(0001), highlighting the potential of this new imaging mode for the spatially resolved characterization of the electronic structure of monocrystalline materials in devices.

The measurement of Ag, Pt and Au on wafer surfaces was addressed by a liquid phase chemical collection coupled to ICPMS analysis. Three chemistries were evaluated from intentionally contaminated wafers in the E12 to E15 at/cm2 concentration range. Different modes of voluntary wafer contamination allowed us to consider both the chemical form of the contaminant (i.e. ionic and metal forms) and its localization (i.e. on the surface and included in the oxide layer). Diluted HNO3 was used for Ag collection on the wafer surface allowing a collection efficiency (CE) higher than 90%. Regarding Pt and Au, diluted aqua regia and diluted HF/aqua regia were used. The first solution leads to a good collection of Au and Pt on the wafer surface (CE >90%) and is inefficient for contamination included in the oxide layer while the second one addresses the two cases with collection rates higher than 94%. Finally, detection limits of few E10 at/cm2 were determined showing the relevance of the technique implemented.

The detrimental effects of metallic on certain key electrical parameters of silicon devices mandates the use of state‐of‐the‐art characterization and metrology tools as well as appropriate control plans. Historically, this has been commonly achieved in‐line on monitor wafers through a combination of Total Reflectance X‐Ray Fluorescence (TXRF) and post anneal Surface Photo Voltage (SPV). On the other hand, VPD (Vapor Phase Decomposition) combined with ICP‐MS (Inductively Coupled Mass Spectrometry) or TXRF is known to provide both identification and quantification of surface trace metals at lower detection limits. Based on these considerations the description of an advanced monitoring scheme using SPV, TXRF and automated VPD ICP‐MS is described.

The dielectric constant of dielectric films used in on‐chip interconnect stacks of microelectronic products is controlled by the deposited material for low‐k and by the incorporation of porosity/voids for ultra‐low‐k (ULK) materials. The porosity has a significant and direct influence on the mechanical and interfacial properties of these materials. Pore volume fraction and spatial distribution have a detrimental impact on the material stiffness and fracture toughness, film adhesion, sensitivity to CMP and device mechanical reliability during other processing steps. The nanomechanical testing of low‐k films—namely nanoindentation and nanoscratch measurements—allows an indirect characterization of the porosity of a ULK film. These tests can resolve variations with nanometer scale spatial resolution as well as changes of porosity of the material as a function of film thickness, all of which significantly impact the mechanical reliability of the device.

At the same time as research in 3D TSV technology is advancing quickly, the analytical techniques used in the evaluation of 3D stacks must also advance in capability. Microscopy techniques for which silicon is opaque such as scanning acoustic microscopy (SAM) and confocal infrared (IR) microscopy are capable of inspecting the interface between bonded wafer pairs, while high resolution X‐ray computed tomography (XCT) is used to detect voids in TSVs. With nano‐XCT, voids in copper TSVs with sub‐100 nm size can be visualized. For more detailed failure characterization, a target Focused Ion Beam (FIB) cross‐section through the localized region of interest (defect) and subsequent scanning electron microscopy (SEM) imaging is proposed. Currently, the most important requirement is to reduce the so‐called time‐to‐data, e. g. for defect localization using nano‐XCT and for cross‐section characterization.

Supported by the European Commission and EURAMET, a consortium of 10 participants from national metrology institutes, universities and companies has started a joint research project with the aim of overcoming current challenges in optical scatterometry for traceable linewidth metrology. Both experimental and modelling methods will be enhanced and different methods will be compared with each other and with specially adapted atomic force microscopy (AFM) and scanning electron microscopy (SEM) measurement systems in measurement comparisons. Additionally novel methods for sophisticated data analysis will be developed and investigated to reach significant reductions of the measurement uncertainties in critical dimension (CD) metrology. One final goal will be the realisation of a wafer based reference standard material for calibration of scatterometers.

We have demonstrated high resolution focused ion beams based on a magneto‐optical trap ion source (MOTIS), which takes advantage of the ultra cold temperatures of laser cooled atoms to produce high brightness, low emittance ion beams. We have created focused beams of both Cr+ and Li+ and present secondary electron micrographs obtained with these beams, demonstrating a focal spot size as low as 27 nm at a beam energy of 2 keV. This work shows that the MOTIS can be a useful source for focused ion beams that will open new opportunities for applications in materials characterization and metrology.

Through‐focus scanning optical microscopy (TSOM) is a relatively new method that transforms conventional optical microscopes into truly three‐dimensional metrology tools for nanoscale to microscale dimensional analysis. TSOM achieves this by acquiring and analyzing a set of optical images collected at various focus positions going through focus (from above‐focus to under‐focus). The measurement resolution is comparable to what is possible with typical light scatterometry, scanning electron microscopy (SEM) and atomic force microscopy (AFM). TSOM method is able to identify nanometer scale difference, type of the difference and magnitude of the difference between two nano/micro scale targets using a conventional optical microscope with visible wavelength illumination. Numerous industries could benefit from the TSOM method—such as the semiconductor industry, MEMS, NEMS, biotechnology, nanomanufacturing, data storage, and photonics. The method is relatively simple and inexpensive, has a high throughput, provides nanoscale sensitivity for 3D measurements and could enable significant savings and yield improvements in nanometrology and nanomanufacturing. Potential applications are demonstrated using experiments and simulations.

The recent advance in lithography process leads to microelectronics compound size reduction. As a direct consequence, micro roughness should not be negligible compared to critical dimension. That is why a novel approach has been developed using an angle resolved scatterometer to quantify roughness value.In order to compare and validate results from scattering measurement, a multiscale analysis will be performed with AFM measurement. Based on theory and numerical models, validation of this technique is performed.

Today 3D integration based on TSV's is a well accepted approach to further improve Integrated Circuits in terms of miniaturization, performance, power consumption and heterogeneous integration. However, 3D integration comes with the introduction of many new processes and materials that may affect behavior and reliability of the overall system. Therefore, there is a strong demand for physical characterization and failure analysis and more explicitly, also for tools and techniques that allow for easy chip access and navigation to the site of interest and that can provide physical information at the nanometer scale within a large field of view.In the framework of the European project JEMSIP‐3D, a novel plasma‐FIB platform has been developed and evaluated by the project partners. This new platform has been characterized in terms of mill rates, resolution and ion assisted CVD kinetics and effective methods have been developed to suppress the curtaining that may appear on X‐sections due to variations in materia...

Backside sample preparation is a well known method to help circumvent undesired effects and artifacts in the analysis of a sample or device structure. However it remains challenging in the case of thin layers analysis since only a fraction of the original sample must remain while removing all of the substrate and maintaining a smooth and flat surface suitable for analysis. Here we present a method adapted to the preparation of ultra thin layers grown on pure Si substrates. It consists in a mechanical polishing up to a few remaining microns, followed by a dedicated wet etch. This method can be operated in a routine fashion and yields an extremely flat and smooth surface, without any remaining Si from substrate. It therefore allows precise analysis of the layers of interests with various characterization techniques.

Silicon's intersection with biology is a premise inherent in Moore's prediction. Distinct from biologically inspired molecular logic and storage devices (more Moore) are the integration of solid state electronic devices with the soft condensed state of the body (more than Moore). Developments in biomolecular recognition events per sq. cm parallel those of Moore's Law. However, challenges continue in the area of “More than Moore”. Two grand challenge problems must be addressed—the biocompatibility of synthetic materials with the myriad of tissue types within the human body and the interfacing of solid state micro‐ and nano‐electronic devices with the electronics of biological systems. Electroconductive hydrogels have been developed as soft, condensed, biomimetic but otherwise inherently electronically conductive materials to address the challenge of interfacing solid state devices with the electronics of the body, which is predominantly ionic. Nano‐templated interfaces via the oriented immobilization of si...

For the analysis of certified semiconducting Al0.7Ga0.3As/GaAs superlattices and photovoltaic samples, we used new generations Auger nano‐probes such as the JEOL JAMP‐9500F Field emission Microprobe and the PHI‐700 Xi system. These nano‐probes are generally used for the chemical analysis of complex nano‐structures at the deca‐nanometric scale. In this paper, we first used both systems for the determination of the surface composition of an Al0.7Ga0.3As/GaAs reference sample. In that, we studied the impact of surface topography on the Auger analysis. Secondly, we used both systems for chemical analysis of photovoltaic samples. Here, we investigated the in‐depth chemical composition, in particular the a‐Si:H (n)/ZnO/Al and ITO/a‐Si:H (p) interfaces, after a specific cross‐section preparation. However, limitations such as image drift due to acoustic vibration and heating effects due to continuous bombardment of energetic electrons at the same point are still a big challenge for quick, routine analysis.

Directed self‐assembly (DSA) of block copolymers (BCPs) is a technology that combines lithographically defined physical or chemical features to guide self‐assembled polymers to create features smaller than those possible with conventional lithography. To the semiconductor industry DSA represents a possible lithography solution below 22–16 nm node where the targeted line edge roughness (LER) is 1.4 nm or less. This LER requirement presents a challenge for DSA to become a viable lithography solution. Hitherto the LER of DSA block copolymers was measured mostly using SEM and AFM, hence the results represent only the top surface characteristics. In addition, the observed LER using SEM or AFM is often greater than 1.3 nm. The purpose of this work is to demonstrate the use of transmission X‐ray scattering to quantify LER as well as the critical dimensions in BCP patterns created with the DSA technique. Experimental results from poly(styrene‐b‐methyl methacrylate) copolymer line gratings with 23 nm half pitch will be presented and the theoretical developments needed to extract LER from X‐ray scattering will also be discussed.

The CD-SEM has been the tool of choice for the imaging and metrology of semiconductor devices for the past three decades but now, with critical dimensions at the nanometer scale, electron beam instruments can no longer deliver adequate performance. A scanning microscope using a He+ ion beam offers superior resolution and depth of field, and provides enhanced imaging contrast. Device metrology performed using ion beam imaging produces data which is comparable to or better than that from a conventional CD-SEM although there are significant differences in the experimental conditions required and in the details of image formation. The charging generated by a He+ beam, and the sample damage that it can cause, require care in operation but are not major problems.

A vertical nanowire tunnel field effect transistor (TFET) and a bit cost scalable (BICS) flash memory are characterized by electron tomography. The optimum measurement conditions are investigated by comparison of the 3D reconstructions obtained with different specimen geometries and different image modes. The few nm thick layers of both devices are clearly observed on the 3D reconstructions, showing the high resolution of this technique and its importance for the analysis of nanodevices.

The shrinking trend in semiconductor technologies is challenging the available instrumentation for mechanical characterization of thin films. Colored Picosecond Acoustics (APiC), a non‐destructive and non‐contact laser technology, enables the measurements of mechanical parameters of complex thin films stacks. In this paper we present the technology and report on results obtained on standard materials.

In this paper three electrical methods for SiC resistivity measurement are discussed. The primary method is based on the Elastic Material Probe (EM‐Probe) or Elastic Probe CV (ECV). Also we discuss the specifics of the advanced Mercury CV (MCV) and Spreading Resistance (SRP) techniques. Measurement results of 4H‐SiC Epitaxial samples are presented, showing a good correlation between various methods.

Resistive switching memory (also known as RRAM for resistive random access memory) is considered a promising candidate for the next‐generation nonvolatile memories. This paper summarizes the electrical characterization methodologies for RRAM performance evaluation and the investigation of resistive switching mechanisms. Some unique issues in RRAM measurements are discussed, including polarity, forming, and switching control. Product‐oriented RRAM characterization needs to consider yield, failure mechanisms, and reliability issues, which has only began to be addressed by the RRAM research community.

We used azimuthally‐resolved spectroscopic Mueller matrix ellipsometry to study a periodic silicon line structure with and without artificially‐generated line edge roughness (LER). Grating profiles were determined from multiple azimuthal configurations, focusing the incident beam into a 60 μm spot. We used rigorous numerical modeling, taking into account the finite numerical aperture and determining the profile shape using a four trapezoid model for the line profile. Data obtained from the perturbed and unperturbed gratings were fit using the same model, and the resulting root‐mean‐square error (RMSE) values were compared. The comparison shows an increase in RMSE values for the perturbed grating that can be attributed to the effects of LER.

In this paper, we present a spectroscopic Mueller matrix ellipsometry measurement of a silicon line grating with nominal pitch of 600 nm and line width 100 nm. An uncertainty analysis is performed on the measurement results. The results are compared to critical dimension atomic force microscopy (CD‐AFM) measurements. Except for one of the gratings, the CD‐AFM and scatterometry measurements lie within each other's uncertainties.

The measurement accuracy is becoming one of the major components that have to be controlled in order to guarantee sufficient production yield. Already at the R&D level, we have to come up with the accurate measurements of sub‐40 nm dense trenches and contact holes coming from 193 immersion lithography or E‐Beam lithography. Current production CD (Critical Dimension) metrology techniques such as CD‐SEM (CD‐Scanning Electron Microscope) and OCD (Optical Critical Dimension) are limited in relative accuracy for various reasons (i.e electron proximity effect, outputs parameters correlation, stack influence, electron interaction with materials…). Therefore, time for R&D is increasing, process windows degrade and finally production yield can decrease because you cannot manufactured correctly if you are unable to measure correctly. A new high volume manufacturing (HVM) CD metrology solution has to be found in order to improve the relative accuracy of production environment otherwise current CD Metrology solution ...

Nowadays the orientation maps of polycrystalline material are necessary for a better understanding of, for example, the formation of voids in the interconnects of modern electronic devices. As new generation of devices has dramatically reduced in size, new tools are required to meet these spatial resolution specifications. In this work two electron microscopy techniques are used to study the voids nucleation sites. Orientation maps were acquired with Electron BackScattered Diffraction (EBSD) technique and with NanoBeam Electron Diffraction (NBED) coupled with the ASTAR technique [1]. Experiments were performed on a Zeiss LEO1530 Scanning Electron Microscope (SEM) and on a JEOL 2010 FEF Transmission Electron Microscope (TEM), both equipped with a FEG (Field Emission Gun). The orientation maps were acquired with a probe size of 15 nm for EBSD and 2.7 nm for NBED. The present study is carried out on polycrystalline copper interconnections as used in the 45 nm technological node. The orientation maps were acquired on the same cross-section sample allowing a precise comparison of the EBSD and ASTAR techniques. This study confirms the localization of the voids nucleation sites (along the Cu/dielectric interface and grain boundaries) and gives new information concerning the orientation in the neighborhood of the voids. © 2011 American Institute of Physics.

EUPS (EUV excited photoelectron spectroscopy) is a novel photoelectron spectroscopy technique, in which a sample is excited with 4.86 nm (255 eV), 3‐ns pulse EUV light emitted from a laser‐produced plasma and the resulting electron spectrum is analyzed with a time‐of‐flight (TOF) analyzer. EUPS gives information of the topmost atoms because the escape depth of photo‐electrons excited by 4.86 nm light is only 0.5 nm. EUPS can evaluate band‐bending because the peak density of the excitation light on the sample is extremely high, so that bent electronic bands in semiconductors can be flattened. Secondary electron spectra, from which the vacuum level of the material surface can be determined, are obtained very quickly owing to the use of a TOF analyzer, The metal gate related issues are one of the most challenging topics facing CMOS technology. This paper demonstrates EUPS as a powerful method for characterizing high‐k/metal interfaces by showing data from direct observations of interfacial dipoles.

As the microelectronics industry enters the “nano”‐era new challenges emerge. Traditional scaling of the MOS transistor faces major obstacles in fulfilling “Moore's law”. New features like strain and new materials (e.g. high k—metal gate stack) are introduced in order to sustain performance increases. For a better electrostatic control, devices will use the third dimension, e.g., in gate‐all‐around nanowire structures. Due to the escalating cost and complexity of sub‐28 nm technologies fewer industrial players can afford the development and production of advanced CMOS processes and many companies acknowledge the fact that the value in products can also be obtained in using more diversified non‐digital technologies (the so‐called “More‐than‐Moore” domain). This evolving landscape brings new requirements—discussed in this paper—in terms of physical characterization of technologies and devices.

In order to continue scaling metal oxide semiconductor field effect transistors (MOSFETs) with HfO2 gate oxides, efforts are being made to further improve the deposited high‐k film properties. Recently, a process whereby an HfO2 film is deposited through a series of depositions and anneals (so‐called DADA process) has been shown to result in films that give rise to MOS capacitors (MOSCAPs) which are electrically scaled compared to MOSCAPs with HfO2 films that only received post deposition anneals (PDA) or no anneals. We have measured as‐deposited, DADA and PDA HfO2 films using four measurement techniques, all of which are non‐destructive and capable of being used for in‐line processing, to evaluate their crystallinity and crystalline phases. Grazing incidence in‐plane X‐ray diffraction was used to determine the crystalline phases of the HfO2 films. We observed the crystalline phases of these films to be process dependent. Additionally, X‐ray and UV photoelectron spectroscopy were used to show the presence...

Different milling strategies for the structural analysis of through‐silicon‐vias with a dualbeam focused ion beam/scanning electron microscope are discussed. Particular attention is given to methods to reduce the analysis time and to minimize the curtaining artifacts.

Electrical scanning probe microscopes (SPMs), such as the scanning capacitance microscope for two dimensional dopant profiling, scanning Kelvin force microscope for surface potential measurements, and the tunneling atomic force microscope for dielectric integrity measurements, are important tools for the characterization of CMOS and nanoelectronic devices. A significant limitation of all these techniques is the stray capacitance from the shank of the tip and cantilever, which causes signal averaging over an area much wider than expected from the terminal tip dimensions. We have used conventional SPM tips terminated with a welded carbon nanotube (CNT) to overcome this limitation. We have examined with scanning capacitance microscopy and scanning Kelvin force microscopy, using both conventional and CNT terminated tips, ultra‐shallow junctions, high‐κ gate stacks, low‐κ intermetal dielectrics, and FINFET devices in cross‐section. We have also measured the electrical properties of the CNT terminated tips. Substantial improvement in the spatial resolution was observed with the CNT terminated tips as compared to the conventional tips, but additional artifacts could also be introduced by the CNT tips. CNT terminated tips provided enhanced spatial resolution when used for electrical characterization measurements useful for nanoelectronics.

As device dimensions decrease below 500 nm, transistors require a gate oxide thickness of

Graphene is a single layer of carbon atoms arranged in a hexagonal lattice. The high carrier mobility and mechanical robustness of single layer graphene make it an attractive material for “beyond CMOS” devices. The current work investigates through high-resolution transmission electron microscopy (HRTEM) image simulation the sensitivity of aberration-corrected HRTEM to the different graphene stacking configurations AAA/ABA/ABC as well as bilayers with rotational misorientations between the individual layers. High-angle annular dark field–scanning transmission electron microscopy simulation is also explored. Images calculated using the multislice approximation show discernable differences between the stacking sequences when simulated with realistic operating parameters in the presence of low random noise.

Wafer bonding using benzocyclobutene (BCB) has been discussed in the past for three-dimensional (3D) integration. This paper reports the development and characterization of a manufacturable BCB bonding process for 300 mm wafers using standard 300 mm tools. A systematic optimization approach has been developed to characterize the bulk properties of the BCB film that can be applied to various integration schemes. We specifically discuss one such application—handle wafer bonding. BCB bonding for a range of cross-linking levels has been investigated. The cross-linking level of BCB before bonding is determined using an infrared (IR) variable angle spectroscopic ellipsometer (VASE) technique. The impact of the BCB film preparation and bonding condition on bond quality is characterized using scanning acoustic microscopy (SAM) , IR microscopy, a razor blade test, and four-point bend methods. Based on the results, an optimum cross-linking level for BCB film before bonding was determined for 300 mm wafers to obtain void-free and dendrite-free bonds. Wafers bonded using the optimized BCB process conditions have successfully sustained backgrinding, dry thinning, and standard BEOL metallization steps.

The semiconductor industry's ability to follow Moore's law to continue to increase the number of components on integrated circuits is increasingly difficult. One way to improve the product performance even at decreased footprint is the use of 3D interconnects which stacks multiple chips in a single package. This new technology for connecting chips overcomes some of the limitations of 2D interconnects. For example, 3D interconnects significantly reduce interconnect delay and improve clock distribution. At the same time that research into 3D technology such as Through Silicon Vias (TSVs) is advancing quickly, the microscopy techniques used in the evaluation of TSV must also advance in capability. Void inspection after copper plating, defect detection and overlay measurements after wafer bonding are challenging. Microscopy techniques for which silicon is opaque such as scanning acoustic microscope (SAM) and confocal infrared microscope (IR) are capable of inspecting the interface between bonded wafer pairs, while high resolution X‐Ray techniques are used to detect voids in TSVs. Initial work was done to determine the limitation of these techniques. Four pairs of bonded wafers were prepared at different thicknesses (100, 200, 300 and 400 μm) to evaluate the effects of wafer thinning using acoustic and infrared microscopy techniques. SAM was able to resolve the 20 μm alignment structure with 300 MHz transducer on 300 mm wafer pair, while IR has sub‐micron resolution for all bonded wafers. This paper discusses the current status of SAM, IR microscopy and XRM in terms of their application to process metrology for 3D interconnects.

We report a preliminary investigation of surface analytical methods used to evaluate trace metal contaminants on silicon wafer surfaces. The methods discussed include sputter induced postionization methods, backscattering spectrometry, total reflection x‐ray fluorescence, and a sample preparation method known as vapor phase decomposition. In order to initiate the evaluation, a series of silicon wafers was dosed with transition metal contaminants Cu and Fe and then analyzed with total reflection x‐ray fluorescence, sputter induced resonant ionization spectroscopy, and heavy ion backscattering spectroscopy. One wafer with low concentrations of Fe was analyzed by time of flight secondary ion mass spectrometry. As a result of this study, we are pursuing improved capability in several areas including standards. Heavy ion backscattering spectrometry is suggested as a means of verifying surface dosed silicon wafer standard.

The 2009 International Technology Roadmap for Semiconductors (ITRS) will be published in late 2009. The 2009 ITRS includes the Metrology Roadmap which is based on the Front End Processes, Interconnect, Lithography, and Process Integration Roadmaps. For the past several years, the Metrology Roadmap has also covered the research and development needs for Emerging Research Materials and Emerging Research Devices. This presentation will review the near and longer term research and development needs for metrology.

An automated technique for the mapping of nanocrystal phases and orientations in a transmission electron microscope (TEM) is described. It is based on the projected reciprocal lattice geometry that is extracted from electron diffraction spot patterns. The required hardware allows for a scanning‐precession movement of the primary electron beam on the crystalline sample and can be interfaced to any newer or older TEM. The software that goes with this hardware is flexible in its intake of raw data so that it can also create orientation and phase maps of nanocrystal from high resolution TEM (HRTEM) images. When the nanocrystals possess a structure with a small to medium sized unit cell, e.g. noble metals or minerals that possess the halite structural prototype, an objective‐lens aberration corrected microscope needs to be utilize for the recording of the HRTEM images that are to be processed by this software. Experimentally obtained crystal phase and orientation maps are shown for iron oxide and clausthalite ...

Grazing Incidence X‐Ray Fluorescence (GIXRF) analysis in the soft X‐ray range provides excellent conditions for exciting B‐K and As‐Liii,ii shells. The X‐ray Standing Wave field (XSW) associated with GIXRF on flat samples is used as a tunable sensor to gain information about the implantation profile in the nm range due to the in‐depth changes of the XSW intensity dependent on the angle between the sample surface and the primary beam. This technique is very sensitive to near surface layers. It is therefore well suited for the study of ultra shallow dopant distributions. Arsenic implanted (100) Si wafers with nominal fluence between 1.0 1014 cm−2 and 5.0 1015 cm−2 and implantation energies between 0.5 keV and 5.0 keV and Boron implanted (100) Si wafers with nominal fluence of 1.0 1014 cm−2 and 5.0 1015 cm−2 and implantation energies between 0.2 keV and 3.0 keV have been used to compare SIMS analysis with synchrotron radiation induced GIXRF analysis in the soft X‐ray range. The measurements have been carried...

The analysis of the Work Function measurements, of different materials, using the Kelvin Force Microscopy technique (KFM) is not trivial. Various artifacts can alter the interpretation of KFM results. Thus a good understanding of experimental conditions effects, involved in a measurement procedure, is essential to provide a reliable interpretation and avoid false conclusions. In this paper, we present an experimental study of the most relevant parameters influencing KFM measurements performed alternatively under air and nitrogen conditions. We investigate the effects of the tip‐sample separation, the tip shape, the relative humidity and the modulation signal applied to the probe. We provide arguments and discussions in order to explain experimentally observed behaviors. We also propose experimental settings and protocols by providing the most convenient conditions for reliable KFM results.

Porous ultra low‐κ (ULK) dielectrics are used to reduce resistance‐capacitance delay for advanced CMOS interconnects. Since the porosity leads to an increased sensitivity of the material to cleaning, etching and ashing plasmas, new characterization techniques are needed to assess the ULK properties during its integration. We show that ellipsometric porosimetry (EP), especially with the combination of several solvents, can be successfully used to characterize porous SiOCH films after different plasma treatments, using reducing and oxidizing chemistries (NH3, H2, CH4 or O2). The characterization of the plasma modified layer is presented and discussed in terms of thickness, hydrophobicity (EP and water contact angle) and κ value. In addition, infrared spectroscopy is used to quantify the methyl (Si‐CH3) depletion. Finally the plasma sealing efficiency is quantified by studying the solvent penetration kinetics.