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Ultimate Backside Sample Preparation For Ultra Thin High-k∕Metal Gate Stack Characterization

Authors :
M. Py
M. Veillerot
E. Martinez
J. M. Fabbri
R. Boujamaa
J. P. Barnes
F. Bertin
David G. Seiler
Alain C. Diebold
Robert McDonald
Amal Chabli
Erik M. Secula
Source :
AIP Conference Proceedings.
Publication Year :
2011
Publisher :
AIP, 2011.

Abstract

Backside sample preparation is a well known method to help circumvent undesired effects and artifacts in the analysis of a sample or device structure. However it remains challenging in the case of thin layers analysis since only a fraction of the original sample must remain while removing all of the substrate and maintaining a smooth and flat surface suitable for analysis. Here we present a method adapted to the preparation of ultra thin layers grown on pure Si substrates. It consists in a mechanical polishing up to a few remaining microns, followed by a dedicated wet etch. This method can be operated in a routine fashion and yields an extremely flat and smooth surface, without any remaining Si from substrate. It therefore allows precise analysis of the layers of interests with various characterization techniques.

Details

ISSN :
0094243X
Database :
OpenAIRE
Journal :
AIP Conference Proceedings
Accession number :
edsair.doi...........4bda4ce3b70d8533b5717339d6eac4fc