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This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller area per channel. Time-multiplexed registers are utilized in the detector for dynamic power reduction. Finally, an ultralow-voltage 8T static random access memory (SRAM) is developed to reduce area and leakage consumption when compared to D flip-flop -based memory. The proposed SSP, fabricated in 65-nm CMOS process technology, consumes only 0.175 $\mu \text{W}$ /channel when processing 128 input channels at 3.2 MHz and 0.54 V, which is the lowest among the compared state-of-the-art SSPs. The proposed SSP also occupies 0.003 mm2/channel, which allows 333 channels/mm2.

Background Pancreatic ductal adenocarcinoma (PDAC) has a high recurrence rate and poor outcome. Lymph node (LN) metastasis, especially para-aortic LN (PALN), is an important prognostic factor. PALN assessment through sampling with frozen-section analysis is a validated method. Our aim was to evaluate the prognostic impact of PALN on overall survival (OS) in patients who underwent standard pancreaticoduodenectomy, lymphadenectomy with PALN sampling, as well as to identify other prognostic factors for survival. Methods Our retrospective study included 89 PDAC patients undergoing radical resection with PALN sampling. The patients were classified into PALN(+) (n = 11) and PALN(−) (n = 78). Univariate and multivariate analyses of 1-year and 3-year OS and Kaplan-Meier model were used. Results OS after 1-year for PALN(+) and PALN(−) was 18.2 and 56.4%, after 3-year was 15.4% and 0%, respectively. Tumor differentiation, LN metastasis (LN(−), LN(+) PALN(−), LN(+) PALN(+)) were significant prognostic factors in both univariate and multivariate analyses for 1-year OS, and neural invasion (PN) was the solely significant factor for 3-year OS (p 0.05). Conclusion PDAC had a poor outcome despite treatment with radical resection. Further follow-up should be conducted to determine the role of surgery in PALN(+)and PN invasion., Highlights • PDAC had poor OS, with 3- and 5-year OS of 13.5% and 5.7%, respectively. • No patients with positive PALN(+) survived after 3 years since radical resection. • PALN and PN invasion are two significant prognostic factors for survival.

High performance but computationally expensive Convolutional Neural Networks (CNNs) require both algorithmic and custom hardware improvement to reduce model size and to improve energy efficiency for edge computing applications. Recent CNN architectures employ depthwise separable convolution to reduce the total number of weights and MAC operations. However, depthwise separable convolution workload does not run efficiently in existing CNN accelerators. This paper proposes an energy-efficient CONV unit for pointwise and depthwise operation. The CONV unit utilizes weight stationary to enable high efficiency. The row partial sum reduction is engaged to increase parallelism in pointwise convolution thereby lightening the memory requirements on output partial sums. Our design achieves a maximum efficiency of 3.17 TOPS/W at 0.85V/40nm CMOS which is well-suited for energy constrained edge computing applications. Accepted version

Background: Nanocovax is a recombinant severe acute respiratory syndrome coronavirus 2 subunit vaccine composed of full-length prefusion stabilized recombinant SARS-CoV-2 spike glycoproteins (S-2P) and aluminum hydroxide adjuvant. Methods: We conducted a dose-escalation, open label trial (phase 1) and a randomized, double-blind, placebo-controlled trial (phase 2) to evaluate the safety and immunogenicity of the Nanocovax vaccine (in 25 microgram (mcg), 50 mcg, and 75 mcg doses, aluminum hydroxide adjuvanted). In phase 1, 60 participants received two intramuscular injection of the vaccine following dose-escalation procedure. The primary outcomes were reactogenicity and laboratory tests to evaluate the vaccine safety. In phase 2 which involved in 560 healthy adults, the primary outcomes are vaccine safety, and anti-S IgG antibody response. Secondary outcomes were surrogate virus neutralization, wild-type SARS-CoV-2 neutralization, and T-cell responses by intracellular staining (ICS) for interferon gamma (IFNg). Anti-S IgG and neutralizing antibody levels were compared with convalescent serum samples from symptomatic Covid-19 patients. Findings: For phase 1 study, no serious adverse events (SAE) were observed for all 60 participants. Most adverse events (AE) were grade 1 and disappeared shortly after injection. For phase 2 study, after randomization, 480 participants were assigned to receive the vaccine with adjuvant, and 80 participants were assigned to receive placebo. Reactogenicity was absent or mild in the majority of participants and of short duration (mean ≤3 days). Unsolicited adverse events were mild in most participants. There were no serious adverse events related to Nanocovax. Regarding the immunogenicity, Nanocovax induced robust anti-S antibody responses. In general, there humoral responses were similar among vaccine groups up to day 90. Anti S-IgG levels and neutralizing antibody titers at the peak response on day 42 were all higher than those of convalescent sera. Interpretation: Up to day 90, Nanocovax was found to be safe, well tolerated, and induced robust immune responses. 25 mcg was selected for a phase 3 trial to evaluate the vaccine efficacy. Trial Registration: ClinicalTrials.gov number, NCT04683484. NCT04683484, registration date in clinicaltrial.gov is Dec24, 2020, We has started our Phase 1 clinical trial in Vietnam on Dec 17, 2020, Funding: Research funded by Nanogen Pharmaceutical Biotechnology JSC., and the Ministry of Science and Technology of Vietnam Declaration of Interest: The following authors Thuy Phuong Nguyen, Hiep Khong, Tri Minh Le, Tuyen Thi Ngoc Trang, Thanh Thi Dinh, Thuong Van Vo, Thao Thi Thu Vu, Quynh Bao Phuong Nguyen, Vuong Tan Phan, Vinh The Tran, Mai Thi Nhu Tran, Truc Thi Thanh Nguyen, Phat Tan Ha, Hieu Trong Huynh, Khanh Duy Nguyen, Chung Chinh Doan, Thuan Trong Ung, Si Minh Do are employees of Nanogen Pharmaceutical Biotechnology JSC. All other authors declare no competing interests. Ethical Approval: The trials were designed and funded by Nanogen Pharmaceutical Biotechnology JSC and the Ministry of Science and Technology (MOST) of Vietnam. The trial protocol was approved by the Ethics Committee/Protocol Review Board of the Ministry of Health (Vietnam)

The complexity and cost of system-on-chip (SoC) designs keep increasing every year, which has progressively led to more opportunities for 2.5D System-in-Package (SiP) design. While 2.5D integration technology offers advantages for heterogeneous chiplet-based systems, it also poses challenges of a more complex overall design flow with limited EDA tools support, physical design optimization issues, interposer floor-planning difficulties and complex system-level verification. Furthermore, accurate inter-chiplet connection modeling, chiplet characterization and top-level simulation activities are also needed for comprehensive verification of SiPs. To tackle these challenges, we share an automated chiplet-based codesign flow: built on the backbone with standard EDA design tools, an automatic SiP register transfer language (RTL) generator is developed for top-level SiP netlist generation; inter-chiplet connection routing with chip assembly router and parasitic extraction tools; interposer design and bumps placement with the foundry defined redistribution layer (RDL).

This paper proposes a scalable neuromorphic processor utilizing asynchronous routers and configurable LIF neuron models. The routing fabric's asynchronous protocol allows for critical timing paths between blocks to be relaxed and reduces power consumption of the global clock tree. The proposed neuron model allows users to deploy different leak profiles for different applications. Furthermore, a hardware mapper is also available to overcome the issue of fixed neuron core size when running networks with different number of neurons per layer. Our 16-core fabricated chip in 40 nm CMOS process works at a wide range of supply voltages. At 0.5V, its measured leakage is only 0.93\ \mu\mathrm{W}/\text{core}$ and its average energy efficiency is 4.8 pJ/SOP, which is 20% better than the state of the arts.

In the era of digital world, Convolutional Neural-network is widely adopted. To keep the network in a reasonable size, down-sampling is required. Max-pooling is a common solution for down-sampling. High throughput and area-efficient -hardware design of 2D max-pooling is essential for CNN accelerator. In this paper, we propose a highly efficient hardware design of max-pooling for 2D data input. The proposed design can be integrated into the neural-network accelerator as it can process the 2D input feature map data in parallel. The proposed solution, which is supporting up to 31 parallel data input, has been synthesized using at 40nm process node with area of 90×100 µm2, and the estimated power is 2.9 mW @200Mhz @1.1V power supply.

This paper exploits circuit techniques to realize a power-gated MRAM with the instant-on characteristic. Each block in a large-capacity MRAM is gated by a separate power transistor, allowing it to be fully turned on after only 1.3 ns. As a result, the whole MRAM is always in sleep mode, except the selected block. This eliminates the need for access pattern prediction as well as the requirement that the MRAM must be in idle for a significant of time before it is put in sleep or deep sleep mode. Our simulation shows that even in the worst-case-scenario, 86% of leakage current is saved. In typical cases, there are 96.5% leakage and 69% total power reduction. Our proposed scheme’s implementation is straight forward and incurs less than 0.5% area overhead, including power transistors and control circuits.

With the semiconductor industry moving towards smaller and more advanced process nodes, the reliability of the fabricated system-on-chips (SoCs) has become a significant problem, although it can be mitigated by proper verification and validation methodologies. Typical neuromorphic SoC chips are resource constrained and have very low power envelopes, pushing designers to forego the integration of onchip debug circuits. Futhermore, these specialized neuromorphic SoCs may not even be capable of supporting memory debug circuits due to the inclusion of novel memory types. Hence, it is a huge challenge to execute a comprehensive system level post-silicon validation suite on such chips, while aiding debugging efforts reliably. This paper presents a post-silicon validation methodology and algorithm to test all the neurocores within our custom designed neuromorphic processing unit (NPU) chip, focused on pinpointing the faults on the synaptic weight storage elements. The described methodology does not require any specialized built-in debug circuits to infer and detect faults. Based on the test results, the custom NPU chip was able to respond accordingly to all performed tests under optimal voltage and frequency conditions.

In this paper we present an energy and area efficient Neuro Connection Map (NCM) which features high fan-out connection to improve the core utilization for large scale neuromorphic system. To meet the stringent power and area requirements, we propose to deploy multi-Vth memory cell design for performance-leakage optimization, localized priority encoder for area/power minimization and finally a decoder-less SRAM for area saving. Our measurements at 1 V supply show that the whole design consumes only 819nW of leakage power. Read and search power are at 5.9μW/MHz and 14.8μW/MHz, respectively. When used in a neuro core with average 100 spikes per neuron per second, the NCM consumes only 0.2pJ/Synaptic event at 1V, making it highly suitable for energy-efficient neuromorphic computing applications.

This paper proposes a scalable hardware architecture for block-based spiking neural networks utilizing a multiplierless spiking neuron model. These blocks were implemented as a neurocore mesh generated from an interconnect algorithm, allowing for seamless scalability of the network size while mitigating connectivity errors. The routing fabric asynchronous protocol allows for critical timing paths between blocks to be relaxed. The proposed neuron model consumed less logic compared to standard models with multipliers, reducing up to 16% of the neurocore logic cell area. The network was implemented alongside a computing subsystem as an FPGA-based system-on-chip, communicating via a fabric interconnect bridge. Experimental results validate the functionality of the proposed system, and achieved comparable classification accuracy to existing works.

Spiking neural networks (SNN) on non-volatile memory (NVM) based neuromorphic computing (NC) chips have been regarded as a promising solution in power constrained scenarios, such as Internet of Things (IoT), due to its low energy consumption. The high power efficiency of NC is due to various aspects including the non-von Neumann architecture of NC chip, low power NVM, and the event driven computation of SNN etc., and introduces a large space for low power design exploration. Therefore, a comprehensive quantitative study of the power modelling for such neuromorphic computing system is important for low power design. In this work, we propose NCPower, an energy consumption estimator for NVM-based neuromorphic chip. We systemically developed analytical models based on physical laws, and verify them by comparing the analytical results with measurement results from different neuromorphic chips. We integrated NCPower in a simulator, and analyzed the accuracy and energy consumption of both the traditional multi-spike based SNN and the new single-spike based SNN. It shows that the single-spike model has 7X energy efficiency over the multi-spike model, with similar accuracy under the CIFAR-10 dataset.

In this paper, a linear force model was applied to investigate the cutting force coefficients in flat-end milling process. Six components of cutting force coefficients were determined by experimental results. This method can be applied to calculate the cutting force coefficients of Al6061-T6 for a series of cutters. The significance of each cutting force coefficient was evaluated. The shear force coefficients are the most important coefficients in calculation of cutting forces. The effect of cutter diameter on each cutting force coefficient was investigated.

Let p be a prime number and \(f\in {S_{n}^{l}}({\Gamma }_{0}(N), \psi )\) be a Siegel cusp eigenform of genus n. We consider the standard zeta function D(Np)(f,s,χ), which takes algebraic values at critical points after normalization. We construct two h-admissible measures μ+ and μ− for certain h = [4ordp(α0(p))] + 1 explained in the Main Theorem with the following properties

This paper presents a true random number generator utilizing the probabilistic delay of the cross-coupled latch during start up as an entropy source. The start-up signal is used as a slow and jittered clock to sample a fast ring oscillator to harvest random bit stream. The tunable jitter delay range and all-digital design ensure high quality random bits generation across a wide range of supply voltages. The test chip consumes 0.54 pJ/bit with a bit rate of 15Mb/s at 0.5 V supply voltage while occupying only 18% area of the state of the art. The design's compact area, simple interface, and high energy efficiency make it a well suited choice for edge computing applications.

In this paper, a novel hybrid method that combines wavelet transform and deep sparse autoencoder for ocular artifact removal is presented. This deep wavelet sparse autoencoder (DWSAE) is capable of suppressing EOG artifacts effectively while preserving the nature of background EEG signals. DWSAE is automatic in either training (unsupervised learning) or correcting phase that makes it a good solution to be integrated into real-time Brain computer interfaces. DWSAE is compared with two other methods that are Second order blind identification (SOBI) and Wavelet neural network (WNN). The experimental results on a public visual attention task dataset show that it address limitations posed by SOBI and WNN effectively.

CMOS PUF is getting more attention from both research community and the industry because it allows cost-efficient integration of device’s digital signature for highly secured authentication protocols. Leveraged on usually-undesirable uncontrollable and random variations in CMOS fabrication process, many CMOS PUF implementations provide strong entropy source to construct low-power, unique and unpredictable device-specific fingerprints. One of the most critical issues in deploying PUFs is their stability against noise and environment conditions when they are interrogated with the same challenge at different time and conditions. This is usually characterized by the native bit-error rate (BER) or intra-class Hamming distance. We propose an arbiter-based PUF utilizing Ring-Oscillators in conjunction with a phase accumulation technique to minimize the BER. Its implementation in 65 nm CMOS consumes only 1. 2pJ/bit while having an error rate of 0.8%.

Network-on-Chip has been widely used as an interconnection fabric due to its high scalability. However, traditional router designs target multiprocessor systems-on-chips, and therefore needs to be improved according to the characteristics of neuromorphic computing. This paper proposes an ultra low power and low area router for neuromorphic computing. Clock gating technique is used to reduce router power consumption by reducing clock activities. The proposed router uses small FIFO based interface links to reduce router area. A modified round robin arbiter is proposed to reduce the router latency. The wormhole model is improved to make it better match neuromorphic computing applications. An ultra low power and small size ring oscillator was designed to provide a global clock to all design blocks. Experimental results show that the average power consumption of the proposed router is 0.26mW, and only 0.01mW when idle. It occupies a much smaller area (0.007 mm 2) compared to other router designs described in previous works. It can be seen from the experimental results that after the clock gating circuitry is added, the total power consumption of $a3 \times3$ router array is significantly reduced, approximately $2.1 \times$ lower when busy and $21 \times$ lower when idle.

The adoption of chronic implantable peripheral nerve-based prosthetic devices is currently hampered by the lack of a highly integrated neural signal acquisition system-on-chip (SoC). We report a ten-channel peripheral nervous system (PNS) electroneurogram (ENG) signal acquisition SoC within an implantable package. Requiring only four off-chip capacitors, this SoC can be co-encapsulated with flexible nerve electrodes and a resonant coil antenna to form a 3.4 cm3 and 3.9 g implantable device for chronic ENG acquisition. This SoC is inductively powered and controlled through a resonant coil at 22 MHz and transmits the digitized neural signal through a near-infrared LED (NIR-LED). Fabricated in 0.18- $\mu \text{m}$ CMOS, each amplifier channel exhibits an input referred noise of 1.9 $\mu \text{V}_{\mathbf {rms}}$ and a noise efficiency factor (NEF) of 4.0 within the signal bandwidth of 5.5 kHz. Each amplifier channel within the SoC is digitized with 10-bit resolution at 17.5 ksps, and the total power consumption (SoC and NIR-LED) is 4.4 mW when the NIR-LED is driven at 3 Mb/s. An electrode impedance measurement circuit with $\text{M}\Omega $ is also incorporated in this SoC. This wireless, low noise ENG acquisition SoC package has been validated in vivo while implanted on a rodent to acquire ENG from its sciatic nerve.

This brief presents an ultra-low power SRAM utilizing a column-based data encoding scheme for power reduction. The proposed scheme is particularly beneficial in applications like bio-signal and image processing where neighboring data have similar values. The proposed technique generates write data through bit-wise comparison, which leads to a larger number of “0s”. To utilize this, a data-aware bitline pre-charge scheme is proposed to minimize the write power for “0”. In addition, a PVT-tracking bias generator compensates for the read bitline leakage to improve the sensing margin. A 32Kb SRAM in 65nm CMOS technology shows successful operation down to 0.36 V with the power of 0.37 $\mu \text{W}$ and the maximum frequency of 0.25 MHz. The minimum energy is 0.3 pJ/access at 0.5 V.

In sub/near-threshold operation, SRAMs suffer from considerable bitline swing degradation when the data pattern of a column is skewed to ‘1’ or ‘0’. The worst scenarios regarding this problem occur when the currently read SRAM cell has different data compared to the rest of the cells in the same column. In this work, we overcome this challenge by using a column-based randomization engine (CBRE). This CBRE circuit randomizes data stored to SRAM. This makes distribution of “1” and “0” in each column close to 50%, significantly increasing bitline swing. To further improve the bitline swing, we employ bitline boost biasing and dynamic bitline keeper schemes. Based on the mentioned techniques, we fabricated a 256 rows×128 columns (32Kb) 8T SRAM array in 65 nm CMOS technology. In our silicon measurement, the SRAM array shows successful 200 mV operation at room temperature, where energy consumption and access time are 1 pJ and 2.5 s, respectively. ASTAR (Agency for Sci., Tech. and Research, S’pore) Accepted version

© 2018, International Osteoporosis Foundation and National Osteoporosis Foundation. Summary: It is not clear why type 2 diabetes (T2D) has an increased risk of fracture despite higher areal bone mineral density. This study showed that compared with controls, T2D patients had higher trabecular bone density but lower cortical bone density, resulting in a lower bone strength. Introduction: To define the association between type 2 diabetes and bone architecture and measures of bone strength. Methods: The study was part of the Vietnam Osteoporosis Study, in which 1115 women and 614 men aged ≥ 30 were randomly recruited from Ho Chi Minh City. HbA1c levels were measured with analyzers ADAMS™ A1c HA-8160 (Arkray, Kyoto, Japan). The diagnosis of T2D was made if HbA1c was ≥ 6.5%. Trabecular and cortical volumetric bone density (vBMD) was measured in the forearm and leg by a pQCT XCT2000 (Stratec, Germany). Polar stress strain index (pSSI) was derived from the pQCT measurements. Difference in bone parameters between T2D and non-diabetic individuals was assessed by the number of standard deviations (effect size [ES]) by the propensity score analysis. Results: The prevalence of T2D was ~ 8%. The results of propensity score matching for age, sex, and body mass index in 137 pairs of diabetic and non-diabetic individuals showed that T2D patients had significantly higher distal radius trabecular vBMD (ES 0.26; 95% CI, 0.02 to 0.50), but lower cortical vBMD (ES − 0.22; − 0.46 to 0.00) and reduced pSSI (ES − 0.23; − 0.47 to − 0.02) compared with non-diabetic individuals. Multiple linear regression analysis based on the entire sample confirmed the results of the propensity score analysis. Conclusion: Compared with non-diabetic individuals, patients with T2D have greater trabecular but lower cortical vBMD which leads to lower bone strength.

A method for producing ferulic acid by ultrasound-assisted, homogeneous, base-catalyzed hydrolysis of γ-oryzanol was developed. Experiments were conducted using various reaction temperatures and ratios of γ-oryzanol to base catalyst in both homogeneous and heterogeneous systems. The reaction performed without ultrasound under the homogeneous conditions of potassium hydroxide/γ-oryzanol ratio (wt/wt) 20 : 1 and 75°C gave a ferulic acid yield of 83.3% in 3 h. Acceleration of the homogeneous reaction using ultrasound irradiation at 20 (horn type) and 200 kHz (planar type) was explored by evaluating the kinetic parameters. At 30°C, the ratios of ultrasonic irradiation at low (20 kHz, 50 W) and high (200 kHz, 50 W) frequencies versus those of the heating method increased by 2.0- and 1.4-fold in comparison with those at 60°C, respectively. The contribution of ultrasonic irradiation (50 W) to the hydrolysis reaction decreased with increase of temperature. However, irradiation at 20 kHz and a power of 180 W gave a 94% ferulic acid yield at 60°C in 3 h. These results indicate that the use of low frequency (horn type and high-power irradiation) enabled yields higher than 90% to be obtained.

Ultra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boosting technique for enhancing the sensing margin. The proposed technique automatically tracks process, temperature and voltage (PVT) variations for robust sensing margin enhancement. A test chip fabricated in 65 nm CMOS technology shows that the proposed scheme significantly enlarges the sensing margin compared to the conventional bitline sensing scheme. It also achieves the minimum operating voltage of 0.18 V and the minimum energy consumption of 0.92 J/access at 0.4 V. Accepted version

Hemocompatibility, anti-inflammation and anti-thrombogenicity of acellular synthetic vascular grafts remains a challenge in biomaterials design. Using electrospun polycaprolactone (PCL) fibers as a template, a coating of polypyrrole (PPy) was successfully polymerized onto the fiber surface. The fibers coated with heparin-doped PPy (PPy-HEP) demonstrated better electroactivity, lower surface resistivity (9–10-fold) and better anti-coagulation response (non-observable plasma recalcification after 30 min vs. recalcification at 8–9 min) as compared to fibers coated with pristine PPy. Red blood cell compatibility, measured by% hemolysis, was greatly improved on PPy-HEP-coated PCL in comparison to uncoated PCL (3.9 ± 2.1% vs. 22.1 ± 4.1%). PPy-HEP-coated PCL fibers also exhibited higher stiffness values (6.8 ± 0.9 MPa vs. 4.2 ± 0.8 MPa) as compared to PCL fibers, but similar tensile strengths. It was also observed that the application of a low alternating current led to a 4-fold reduction of platelet activation (as quantitated by CD62p expression) for the PPy-HEP-coated fibers as compared to non-stimulated conditions. In parallel, a reduction in the leukocyte adhesion to both pristine PPy-coated and PPy-HEP-coated fibers was observable with AC stimulation. Overall, a new strategy involving the use of hemocompatible conducting polymers and electrical stimulation to control thrombogenicity and inflammatory responses for synthetic vascular graft designs was demonstrated.

Porthole die extrusion has a great advantage in the forming of hollow section of aluminum alloy tube. The proposed paper aims at the development of an extruding seam square tube of AA7075 high strength aluminum alloy by simulation and experiment. There are several factors related to extrusion load such as: billet temperature, billet dimensional, flow stress, die cavity and product geometry. The extrusion loads and die stresses for a hot extruding square tube of AA7075 with respect to different product have been investigated. This study used DEFORM 3D software based on finite element analysis to simulate two different types of hollow extruding die configurations in the square tube extrusion process, namely: Type I welding position at the corners of the square tube and Type II on the side faces. The welding strengths of these two kinds of extruded tube are studied by expanding test and tensile test. The die life of these two extrusion die components are studied based on the die stress and die wear information. The results of FE analysis are compared with those experiments.

This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 μs. Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V ~ 0.6 V by the proposed CAM-assisted circuit. ASTAR (Agency for Sci., Tech. and Research, S’pore) Accepted version

This paper proposes a low-power, small formfactor all-digital RNG utilizing a concept of capacitive coupling between two ROs to amplify jitter and a dual-edge sampling scheme to increase the data rate. It is the most useful in battery-powered IoT applications where both energy and silicon area are critical constraints. The capacitive coupling effect with all digital circuit allows our design to operate reliably over a wide range of supply voltages. It consumes only 1.85 pJ/bit at 1V supply and 67 Mb/s, which scales down to 25 fJ/bit at 0.3 V, 5 Mb/s. Its overall FOM is 1.7×104, which is more than 3× better than existing designs.

This paper describes the establishment of a machine vision system for measurement compression spring. This kind of spring is used in the automotive suspension systems on cars. The special features for this kind spring are non-uniform diameter, non-regular helix and non-unique center line. A reverse engineering to construct spring geometry for further manufacturing becomes necessary when there is no CAD data for this spring. The reverse measurement facilities include contact stylus instrument, laser scanner and white-light grating system. These devices can be used to measure spring, but time and money consuming is a common problem with this measurement solution. In this paper, a new method with low-cost measurement developed to solve this problem. A man-machine interface for measurement by Visual Basic 6.0 has been developed which adopted a single camera mounted in a three-axis measurement frame. A fixed focal length camera and image processing technique were used to construct the object's position as well as coordinates. Therefore, the spiral of the measured spring can be constructed. By comparing the measured data to the ATOS system with Poly-works, the differences can be obtained. The largest upper deviation is about 3.3 mm and the largest lower deviation about −2.7 mm for spring geometry construction.

Die-casting process is significantly used in the industry for its high productivity and less post-machining requirement. For high pressure die-casting, it needs well-design of gating and runner system; therefore, die cavity design and technology parameter calculations are essential. In the current paper of die-casting for automobile starter motor casing, the following issues are focused: filling simulation, defect analysis, and finally the use of the Taguchi multi-quality analysis method to find the optimal parameters and factors to increase the aluminum ADC10 die-casting quality and efficiency. When the casting speed is increased, the volume shortage detects due to solidification procedure can be reduced. However, if the casting speed exceeds a permissible level, the defects of gas volume and porosity will occur. After Taguchi method analysis, the results of the optimum parameters are: for the gate area of 40mm2, group 2 of the gate location, the speed of the liquid metal at the gate 50 m/s, the temperature of molten aluminum 670° C.

This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the delay of the sense amplifier enable signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum ML swing, making the CAM tolerant to variations. The proposed ABC scheme achieves the power reduction of 5.5× compared with the conventional ML sensing scheme. In addition, multi-V t transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharging speed by 2× when compared with the standard-V t devices at 1.2 V, 80 °C. A test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 1.2 V/500 MHz. Accepted version

A small bitline sensing margin is one of the most challenging design obstacles for reliable ultra-low-voltage static random access memory (SRAM) implementation. This paper presents design techniques for bitline sensing margin enhancement using decoupled SRAMs. The proposed bitline-boosting current scheme improves the bitline sensing margin at a given bitline configuration. The bitline sensing margin can be further augmented by equalizing bitline leakage. Simulation using a 40-nm CMOS process shows that the proposed techniques achieve larger bitline sensing margin, wider operating temperature and supply range, and a larger number of cells per bitline.

This paper proposes an 8T SRAMs utilizing a column-based data encoding scheme to reduce read and write power when there are similarities between consecutive data. It is useful in image processing applications where nearby pixels tend to have similar values. The proposed design has two modes of operation: normal and sequential modes. In the normal mode, it operates as a normal SRAM. In the sequential mode, bit-wise differences between consecutive data are written instead of the actual data. This leads to a much higher number of zeros in the array. Accordingly, a new data-aware bitline pre-charge scheme is proposed to minimize write power when writing a zero. A PVT-tracking reference voltage generator is also employed to compensate the read-bitline leakage for ultra-low voltage operation. On average, it offers more than 30% WBL switching power reduction. A 32Kb SRAM implemented in 65 nm CMOS process demonstrated successful operation down to 0.36 V. The total power consumption is 0.37 μW, corresponding to the maximum frequency of 0.25 MHz. Its minimum energy is 0.3 pJ/access achieved at 0.5 V.

Multi-electrode intracranial recording technology is highly required for various applications such as brain studies, brain machine interface (BMI) and treatment of disorders like epilepsy, memory loss and paralysis. The recording is done by inserting electrodes into the extracellular tissue of the brain to supposedly record the single-unit activity. However, the recorded signal is the summation of some near-by neurons activities and the background noise. Therefore, after recording and digitizing the signal by analog front-end, the first crucial step is to extract the information from extracellular recording [1]. This process is called spike sorting and shown in Fig. 1. It basically assigns the detected spike to their source neurons located near the corresponding recording electrodes.

This paper presents a power and area efficient processor for real-time neural spike-sorting. We propose a robust spike detector (SD), a feature extractor (FE), and an improved k-means algorithm for better clustering accuracy. Furthermore, time-multiplexing architecture is used in SD for dynamic power reduction. A customized 39kb 8T SRAM is also implemented to minimize leakage and storage area. The proposed processor consumes 0.175 µW/ch with leakage of 0.03 µW/ch at 0.54 V and area of 0.0033 mm2/ch.

Unbonded flexible pipelines for deep water field applications are subject to elevated hydrostatic constraints; bore pressure being dropped brings high compressive stresses due to reverse end cap effect. If the external sheath is unsealed, the axial compression loads transmitted to the tensile armors induce their radial expansion, which can lead to their buckling. Specific layers shall be added in order to maintain armors in place: anti-buckling tapes. These layers, designed with high performance fibers, have been introduced in the early 1990's when the use of flexible pipe has grown in deep water.Various failure modes are expected and observed depending on the fiber characteristics, tape construction, tensile armors properties and annulus environment. For each pipe design, an optimum has to be found between the anti-buckling tapes loads and the compressive stress in the armor layers in order to ensure sufficient safety margins against both tapes breakage and different buckling modes of the armors.Anti-buckling tape interaction with the tensile armors and annulus environment main influencing parameters will be explained in the light of full scale tests performed on flexible pipes in hyperbaric tank. Specific laboratory devices have also been developed to be representative of the operating behavior of both armors and high strength tapes.In parallel, this paper will present qualification tests performed in compliance with the requirements of 2014 editions of API standards 17J and 17B.The tests showing tape resistance and flexible pipe behavior have enabled to establish a robust design rule. This process is being scrutinized by an Independent Verification Agent and aims at leading to Type Approval Certification according to the latest edition of API 17J.

Background: Directing cell behaviour using controllable, on-demand non-biochemical methods, such as electrical stimulation is an attractive area of research. While there exists much potential in exploring different modes of electrical stimulation and investigating a wider range of cellular phenomena that can arise from electrical stimulation, progress in this field has been slow. The reasons for this are that the stimulation techniques and customized setups utilized in past studies have not been standardized, and that current approaches to study such phenomena rely on low throughput platforms with restricted variability of waveform outputs.Results: Here, we first demonstrated how a variety of cellular responses can be elicited using different modes of DC and square waveform stimulation. Intracellular calcium levels were found to be elevated in the neuroblast cell line SH-SY5Y during stimulation with 5 V square waves and, stimulation with 150 mV/mm DC fields and 1.5 mA DC current resulted in polarization of protein kinase Akt in keratinocytes and elongation of endothelial cells, respectively. Next, a miniaturized stimulation device was developed with an integrated cell chamber array to output multiple discrete stimulation channels. A frequency dividing circuit implemented on the device provides a robust system to systematically study the effects of multiple output frequencies from a single input channel. Conclusion: We have shown the feasibility of directing cellular responses using various stimulation waveforms, and developed a modular stimulation device that allows for the investigation of multiple stimulation parameters, which previously had to be conducted with different discrete equipment or output channels. Such a device can potentially spur the development of other high throughput platforms for thorough investigation of electrical stimulation parameters on cellular responses. Published version

Ion-Sensitive Field-Effect Transistor (ISFET) is an emerging technology that has the potential to be used for pH sensing and other ion-based sensing applications. In conventional ISFET designs, pH sensors convert H+ concentration into analog voltage before digitizing to binary bits. This paper proposes a digital-based ISFET design that minimizes the use of analog front end and directly converts pH into 10-bit binary output using digital comparators and a counter. Our simulation results in standard 65nm CMOS technology proved that the design has a resolution of 0.0437 pH with energy performance of 28.4 pj/conversion.

Real time spike detection is the first critical step to develop spike-sorting for integrated brain circuits interface applications. Nonlinear Energy Operator (NEO) and absolute thresholding have been widely used as the spike detection algorithms where NEO has a better performance measured by the probability of detection and false alarm. This paper proposes a hybrid spike detection algorithm incorporating both spike detection algorithms to reduce the power and to keep the detection rate the same as that of NEO. In the proposed algorithm, the absolute thresholding is performed first to detect a potential spike. Once a potential spike is detected, NEO is executed to check whether the detected spike by absolute thresholding is valid. Since NEO is conditionally conducted, this reduces the overall power consumption. The simulation shows that the proposed hybrid method improves the power consumption by 54.48% compared to NEO in 65 nm CMOS technology. Accepted version

Diminishing bitline sensing margin at low voltage condition is one of the most challenging design obstacles for reliable SRAM implementation in nano-scale CMOS technologies. This paper presents a self-biased design technique that improves the bitline sensing margin during the read operation by sourcing a current which is the same as the total leakage along each bitline. It is able to automatically track changes in supply voltage, operating temperature and die-to-die process variations. Furthermore, a 9T SRAM cell is utilized to ensure that bitline leakage is data-independent. Simulation and measurement results using 65 nm CMOS process show that the proposed technique enlarge the bitline swing over a wide range operating temperature and operates successfully down to the supply voltage of 0.18 V.

International audience; We explicitly compute the special values of the standard $L$-function $L(s, F_{12}, \mathrm{St})$ at the critical points $s\in \lbrace -8, -6, -4, -2, 0, 1, 3, 5, 7, 9\rbrace $, where $F_{12}$ is the unique (up to a scalar) Siegel cusp form of degree $3$ and weight $12$, which was constructed by Miyawaki. These values are proportional to the product of the Petersson norms of symmetric square of Ramanujan’s $\Delta $ and the cusp form of weight $20$ for ${\rm SL}_2(\mathbb{Z})$ by a rational number and some power of $\pi $. We use the Rankin-Selberg method and apply the Holomorphic projection to compute these values. To our knowledge this is the first example of a standard $L$-function of Siegel cusp form of degree $3$, when the special values can be computed explicitly.