0.8% BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique

CMOS PUF is getting more attention from both research community and the industry because it allows cost-efficient integration of device’s digital signature for highly secured authentication protocols. Leveraged on usually-undesirable uncontrollable and random variations in CMOS fabrication process, many CMOS PUF implementations provide strong entropy source to construct low-power, unique and unpredictable device-specific fingerprints. One of the most critical issues in deploying PUFs is their stability against noise and environment conditions when they are interrogated with the same challenge at different time and conditions. This is usually characterized by the native bit-error rate (BER) or intra-class Hamming distance. We propose an arbiter-based PUF utilizing Ring-Oscillators in conjunction with a phase accumulation technique to minimize the BER. Its implementation in 65 nm CMOS consumes only 1. 2pJ/bit while having an error rate of 0.8%.