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This paper presents the first demonstration of an active power divider operating from 100 MHz to 200 GHz. The circuit is based on a distributed architecture, where two output lines are fed replicas of the signals traveling in the shared input line. The gain element employed in the distributed divider consists of a triple-stacked cascode that exploits internal feedback to increase its equivalent transconductance. The higher transconductance toward frequency compensates the synthetic-line losses, which are the main limiting factor for applications at high frequencies of this class of circuits. A tapering of the synthetic-line impedance has also been adopted to further minimize the synthetic losses. Implemented in a high-performance 130-nm SiGe-BiCMOS technology, the system requires 300 mW of dc power consumption to provide 10 dB of gain over the 3-dB bandwidth 1–180 GHz. At 100 MHz and 200 GHz, the gain decreases to 0 dB. The presented circuit improves the state of the art for distributed power dividers implemented in any integrated circuit technology by a factor 5 for both maximum frequency of operation and bandwidth. Thanks to the triple-stacked gain cell in combination with the tapered synthetic line, the circuit reaches 10 dBm of output power at 1-dB gain compression, which is the highest reported for distributed power dividers. [ABSTRACT FROM AUTHOR]

A fully integrated wide-bandwidth transmitter (TX) module intended for use in short-range frequency-modulated continuous-wave radar applications is proposed. By incorporating an on-chip fractional- ${N}$ phase-locked loop based on the fundamental voltage-controlled oscillator, the TX is able to synthesize highly programmable 11-GHz linear chirps around the 65-GHz central frequency, hence theoretically enabling sub-1.5-cm spatial resolutions. Implemented in a 0.13- $\mu \text {m}$ BiCMOS process, the test-chip delivers more than +5 dBm of output power and achieves the measured root-mean-square ramp error (nonlinearity) of 340 kHz for a 60-GHz/ms modulation rate signal over the complete range of interest. The presented TX module dissipates 550mW and also includes an adequate on-board directional $4\times4$ antenna array. [ABSTRACT FROM AUTHOR]

This paper presents a high-integration miniaturized dielectric spectroscopy system for sensing the change of permittivity at 240 GHz in the SiGe BiCMOS technology. The sensor features a transducer with a resonator to perform bandpass frequency response, whose complex value of $S_{21}$ is varied with the permittivity of the sample under test. This variation can be detected and recorded as the change of amplitude and phase of the 240-GHz in-phase and quadrature direct conversion mixer. An external 30-GHz source is employed with cascade frequency multiplier chain to deliver a signal through the system with a wide tuning range of 215–245 GHz. An additional probe is employed to carry the sample and implement chip measurements on the probe station. The sensing function of this system is performed with the leaded wire as a metallic sample to be placed on the top of the transducer. Based on the measured dc output voltage changes, the calculated magnitude and phase of IQ signal in the 215–245-GHz range are used to estimate the complex permittivity change of MUTs. This dielectric spectroscopy system is also suitable for sensing the complexy permittivity change at higher frequencies in the future terahertz Lab-on-Chip measurements. [ABSTRACT FROM AUTHOR]

Fourier transformed infrared absorption spectroscopy was used to investigate the effect of germanium (Ge) doping on the production and evolution of divacancy (V2) complexes in neutron irradiated Czochralski (Cz) silicon. The generation rates of V2 and vacancy-oxygen (VO) complexes were found to increase in Ge doped silicon as compared with the controlled Cz silicon, which could be ascribed to the increased availability of vacancies in Ge doped silicon arising from the temporary trapping of vacancies associated with the transient GeV pairs. Upon annealing, most of the V2 complexes were eliminated via the reaction between divacancy and self-interstitials (Sii) (V2 + Sii → V), while only 6-24% of V2 complexes were transformed into V2O complexes via the trapping of V2 complexes by interstitial oxygen (Oi), as V2 diffuses much faster than Oi. It was observed that Ge doping accelerated the V2 annihilation and in turn suppressed the transformation of V2 into V2O complexes. Those phenomena can be attributed to the increased availability of free self-interstitials in Ge doped silicon, which enhances the recombination of V2 with Sii. Additionally, an increased production of V3O complexes was observed in Ge doped silicon. The role of Ge atoms in the V3O formation was discussed in view of the two reactions V2 + VO → V3O and V2O + V → V3O. [ABSTRACT FROM AUTHOR]

This paper presents design considerations for an 8:1 multiplexer (MUX) circuit in a SiGe BiCMOS technology intended to be monolithically integrated together with a plasmonic Mach–Zehnder modulator on a single chip. It is shown why a power MUX (PMUX) architecture, where the final MUX selector stage directly drives the load, is beneficial to obtain high data rates and high output voltage swings at comparatively low power consumption. Therefore, the relation between the clock input amplitude and parasitic capacitances on the rise time of the PMUX is analyzed. Owing to the importance of the clock signal to the PMUX performance, design considerations for the clock distribution are presented. The design concept is proven by electrical measurements that demonstrate a record performance by clear output eye diagrams at 100 and 140 Gbit/s with 2.0 $V_{\text {pp}}$ and 1.2 $V_{\text {pp}}$ differential output voltage swing, respectively. The 2.6mm $\times $ 1.7mm MUX chip is implemented in IHP SG13G2 SiGe BiCMOS technology and consumes 7.15 W on a single −5.5-V supply voltage. [ABSTRACT FROM AUTHOR]

94-GHz dual-polarized phased array transmitter and receiver ICs in 130 nm BiCMOS technology are reported. The transmitter IC integrates 16 transmitter front ends with two independent outputs, a 1-to-16 power splitter, and an intermediate frequency (IF)-to-RF up-converter. The receiver IC integrates 32 front ends, two separate 16-to-1 power combiners, and two RF-to-IF down-converters, which can either support a 32-element phased array or a 16-element polarimetric phased array if connected to 16 dual-polarized antennas. Both transmitter and receiver ICs include IF/baseband circuitry, a frequency synthesizer with continuous lock detection, a temperature sensor, and digital circuitry, including serial interface and front-end memory. On-wafer TX measurements at 94 GHz taken at 25 °C show an IF-to-RF conversion gain of 35 dB, oP1dB of 4 dBm, $P_{\text {SAT}}$ of 7.8 dBm per channel with a total power consumption of 3 W. On-wafer RX measurements at 94 GHz and 25 °C show a maximum RF-to-IF array conversion gain of 40 dB and an noise figure (NF) of 6 dB. The total RX power consumption varies from 3 to 4.6 W as it is configured from its minimum to its maximum RF front-end gain settings. RF phase shifting elements used in both TX and RX demonstrate a 1.6° phase resolution with 360° tuning range and gain variation (rms) lower than 0.5 dB. Phase-invariant gain tunability in TX and RX front ends has been achieved for independent tapering and beam steering, demonstrating the measured phase variation within ±0.5° for 10-dB gain tuning. Both TX and RX ICs are functional up to 105 °C, maintaining $P_{\text {SAT}}>6.5$ dBm per channel in TX and NF < 12 dB in RX. The TX and RX ICs each have a chip size of 6.7 mm $\times $ 5.6 mm. [ABSTRACT FROM AUTHOR]

This paper presents SiGe-based transmitter and receiver chips for a radio frequency identification (RFID) frontend in the 61-GHz industrial, scientific, and medical (ISM) frequency band. The chips are fabricated in a modern 130-nm SiGe BiCMOS technology with HBTs offering an $f_{T}$ of 250 GHz and $f_{\mathrm{max}}$ of 370 GHz. The presented transmitter consists of a fundamental voltage-controlled oscillator (VCO), a power amplifier (PA), lumped element Wilkinson power dividers, and a static divide-by-16 chain for stabilization within a phase-locked loop (PLL). Two variants of the transmitter are fabricated with supply voltages of 3.3 and 5 V, respectively. The transmitters are designed to provide an efficient signal source to supply a passive RFID tag with the maximum allowed 20-dBm effective isotropic radiated power (EIRP) for short-range devices. The 3.3-V transmitter chip achieves a peak output power of 17 dBm, PAEPA of 18.6% and dc-to-RF efficiency of 12.9% (excluding the divider). At 61 GHz, a phase noise of −102 dBc/Hz at 1 MHz offset is achieved. The power consumption for the 5- and 3.3-V transmitter chips is 710 and 482 mW, respectively. The receiver chip is implemented as two Gilbert cell mixers in-phase quadrature configuration to compensate for destructive interference that may be caused by varying distance between reader and tag. [ABSTRACT FROM AUTHOR]

We demonstrate multi-channel InP-based coherent transmitter and receiver photonic integrated circuits hybrid integrated with SiGe driving and amplifying electronics both capable of operating at 880 Gb/s and the transmitter alone up to 1 Tb/s per wave. These hybrid assemblies demonstrate optical transmissions across a commercial line system at distances from 200 to 1400 km, with symbol rates between 66–100 GBd, utilizing 16-, 32-, and 64-QAM modulation formats. Additionally, we demonstrate a back-to-back transmission from the TxPIC assembly to a reference receiver at 100 GBd $\times \,\, 32$ QAM, a 1 Tb/s per wavelength capability. [ABSTRACT FROM AUTHOR]

This paper investigates on-wafer characterization of SiGe HBTs up to 500 GHz. Test structures for on-wafer thru-reflect-line (TRL) calibration have been designed and are presented. The TRL calibration method with silicon standards has first been benchmarked through electromagnetic simulation. Passive and active components are then characterized up to 500 GHz. The slight discontinuities between the frequency bands are explored. A specific focus was placed on incorrect horizontal probe positioning as well as on probe deformation, resulting in a better assessment of possible measurement errors. [ABSTRACT FROM AUTHOR]

The authors report about a detailed study of the chemical composition of advanced HfO2/interfacial layer/SiGe stacks for future p-channel metal-oxide-semiconductor field-effect transistors. Several state-of-the-art characterization techniques are implemented to provide consistent and complementary information about interfacial chemical states and Ge diffusion along the stack. Angle-resolved x-ray photoelectron spectroscopy is performed in both standard and parallel modes. Results highlight the presence of elemental Ge in the HfO2, suggesting some Ge out diffusion from the SiGe substrate. This trend is confirmed by time-of-flight secondary ion mass spectrometry and plasma profiling time-of-flight mass spectrometry, a recently developed technique to monitor thin films compositions during device manufacturing. [ABSTRACT FROM AUTHOR]

A compact highly efficient high-power SiGe Ka-band balanced frequency doubler is presented. Using a compact single-footprint four-way transformer input balun, wideband matching, and high fundamental rejection were achieved simultaneously. A cascode topology with very low base impedance termination was utilized for stable operation and high-voltage swing at the output. Two cascode differential pairs form a common-centroid configuration, resulting strong enhancement in output power, power-added efficiency (PAE), fundamental rejection, and robustness to process and supply variation. The proposed Ka-band cascode balanced frequency doubler was implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology. Measured results show 13-dBm output power with 22% peak PAE at 34 GHz for a −1-dBm input power. The 3-dB conversion gain bandwidth is from 25 to 40 GHz, fully covering Ka-band. Peak fundamental suppression is 74.5 dB at 33 GHz, and it is higher than 35 dB over Ka-band. No performance degradation is observed after 24-h RF stress test. To the author’s best knowledge, this paper has the highest efficiency, the highest output power/power density, the highest conversion gain without output buffers, and the higher or comparable fundamental rejection among any Si-based frequency doublers. Therefore, this doubler will be a promising solution for efficient and high-power local oscillator generation in 5G wireless phased-array communication system. [ABSTRACT FROM AUTHOR]

Wireless systems like radar and communication systems evolved progressively into multichannel systems over the past years. The most common multichannel concepts are multiple-input multiple-output (MIMO) and phased array architectures. In this paper, we present a transmitter monolithic microwave integrated circuit (MMIC) in a SiGe BiCMOS technology for its application, a mixed-mode frequency modulated continuous wave radar that is able to operate in both ways, in an MIMO and a beamforming mode. The MIMO mode is used for medium range and fast 3-D scans and the phased array mode is used for beamforming. This mode increases the effective output power of the transmitted signal beam and thus system dynamic and detection range. For this purpose, we developed ultrawideband quadrature (IQ) generation techniques to generate synchronous IQ-signals in each channel of our system to feed a vector adder, which is capable of shifting the phase for beamforming. The developed IQ-generation circuits are able to operate from 1 to 30 GHz, and the complete radar transmitter MMIC, including a power amplifier (PA), operates from 11 to 20 GHz. The IQ-generation phase error in this frequency range is below 6° and below 9°/3.2°rms for the IQ-generation together with vector modulator. The power consumption is 285 mW and the PA consumes 1.25 W with a maximum output power of the complete multimode TX MMIC of 24.4 dBm at 15 GHz. [ABSTRACT FROM AUTHOR]

This paper evaluates enhanced low dose rate sensitivity (ELDRS) in Silicon–Germanium heterojunction bipolar transistors (SiGe HBTs) which are isolated by LOCOS process. The 60 Co gamma irradiations were performed at 80 rad (Si)/s and 0.1 rad (Si)/s respectively in order to investigate dose rate dependence of the SiGe HBT. Devices were set in forward, saturated, cutoff, and all-grounded biases during the irradiation. The degradation mechanism of different dose rate irradiations was analyzed via measurement of forward Gummel mode and inverse Gummel mode both pre- and post- irradiation. The results show that ELDRS exists at forward, saturated, and all-grounded biases irradiations. The dose rate dependences of various irradiated biases are different in the SiGe HBT. The interface-traps both in EB Spacer and LOCOS are the major irradiated damages in the SiGe HBT for the low dose rate irradiation. ELDRS is directly related to the quality, thickness, and shape of oxide layers. [ABSTRACT FROM AUTHOR]

This paper describes a novel distributed amplifier (DA) architecture for ultra-wide band of operation at millimeter-wave frequency. The DA consists of two cascaded single-stage DAs (CSSDAs) embedded in a balanced architecture. The implemented design retains the benefits of CSSDAs in terms of high maximum frequency, broad band of operation, and compact area, while significantly improving the amplifier input and output matching and its linearity with the balanced architecture, which are the major issues of this class of circuits. The small-signal analysis is provided in detail and explains the nature of the poor output matching typical of this class of DAs. Furthermore, the CSSDA gain is calculated as function of frequency and circuit parameters, extending available literature results, and providing direct design guidelines with a compact formula. Experimental validation is demonstrated with the fabrication of a circuit prototype in a 130-nm SiGe BiCMOS process. The circuit is able to provide an average of 16-dB gain over the frequency band 30–220 GHz, with input- and output-return losses above 10 dB, and a maximum measured output-referred 1-dB compression point of 4.5 dBm. To the best knowledge of the authors, the measured matching and linearity are the best reported for CSSDAs. [ABSTRACT FROM AUTHOR]

A 50-Gb/s optical receiver (RX) based on 0.18- $\mu \text{m}$ SiGe BiCMOS technology was fabricated and evaluated. To improve the horizontal eye opening and sensitivity of the RX without degrading its power efficiency, it is configured with a two-stage pre-amplifier with high gain (56 dB $\Omega $ ) and high bandwidth (35 GHz), a high-accuracy automatic decision-threshold control (ATC) consisting of power-supply variation and offset cancellers for improving sensitivity, and a jitter-reduction packaging structure for improving transimpedance flatness. The RX achieves high sensitivity of −9.2 dBm, while its power consumption is 7.9 pJ/bit at a data rate of 50 Gb/s. In 50- and 56-Gb/s transmission tests through a 100-m multi-mode fiber (MMF), it demonstrated error-free operation at the bit error rate (BER) of less than 10–12 with the sensitivities of −9 and −6.1 dBm optical modulation amplitude (OMA). It also demonstrated 300-m error-free MMF transmission (at 50 Gb/s) with the practical sensitivity of −7.6 dBm OMA. [ABSTRACT FROM AUTHOR]

Stress-engineered fin-shaped field effect transistors (FinFET) using germanium (Ge) is a promising performance booster to replace silicon (Si) due to its high holes mobility. This paper presents a three-dimensional simulation by the Sentaurus technology computer-aided design to study the effects of stressors--channel stress, stress-relaxed buffer (SRB), and source/drain (S/D) epitaxial stress--on different bases of FinFET, specifically silicon germanium (SiGe) and Ge-based, whereby the latter is achieved by manipulating the Ge mole fraction inside the three layers; their effects on the devices' figures-ofmerits were recorded. The simulation generates an advanced calibration process, by which the drift diffusion simulation was adopted for ballistic transport effects. The results show that current enhancement in p-type Fin- FET (p-FinFET) with 110% is almost twice that in n-type FinFET (n-FinFET) with 57%, with increasing strain inside the channel suggesting that the use of strain is more effective for holes. In SiGe-based n-FinFET, the use of a highstrained SRB layer can improve the drive current up to 112%, while the highstrain S/D epitaxial for Ge-based p-FinFET can enhance the on-state current to 262%. Further investigations show that the channel and S/D doping are affecting the performances of SiGe-based FinFET with similar importance. It is observed that doping concentrations play an important role in threshold voltage adjustment as well as in drive current and subthreshold leakage improvements. [ABSTRACT FROM AUTHOR]

The possibility of generation of ultrawideband chaotic oscillation in a frequency band of 10-30 GHz on the basis of the state-of-the-art microelectronic technology has been investigated. Schematic and topological models of a generator of chaotic oscillations based on elements from the 130-nm SiGe technology library have been proposed, developed, and investigated. The dynamics of the oscillation conditions and the energy efficiency of the generator has been analyzed. [ABSTRACT FROM AUTHOR]

In this work, performance analysis of strain-engineered FinFETs has been performed using simulation. The prospect of Silicon-Germanium (SiGe) as channel material has been explored for the introduction of SiGe-CMOS technology for FinFETs. The impact of Silicon-Germanium stressor in a SiGe-embedded source/drain FinFET structure is examined. As stress has a major impact on transistor characteristics in advanced devices, stress effects need to be determined from simulation in order to study the influence of stress-related effects. Through the use of the threetemperature dependent piezoresistive coefficients of silicon stress analyses have been performed and the results are presented. We have also investigated the effects of low temperature on the electrical performance of silicon FinFETs. The physics-based 3D device simulation tool VictoryDevice is used for the simulations and characterization of the electrical properties of strain-engineered SiGe-channel FinFETs. Performance enhancement is observed at low temperature. [ABSTRACT FROM AUTHOR]

Simple technique of formation of “black silicon” using wet chemical etching of crystalline Si wafers with SiGe self-assembled islands is proposed. The main idea consists of the utilization of SiGe islands as a mask for wet anisotropic etching of Si in alkali-based solution at the first etching stage and further removal of SiGe residuals by etching in a HF:H 2 O 2 :CH 3 COOH mixture at the second etching stage. Initial samples were the crystalline Si wafers with SiGe islands formed on them by deposition of 2.5–14 nm of Ge at 800 °C. After the two above-mentioned etching steps a submicron relief on a Si surface was formed. Investigation of optical properties of fabricated structures revealed significant decrease of reflection (AM 1.5 G weighted reflection ~2–3%) and increase of absorption in the wavelength range of 500–1200 nm. Due to the very small amount of Si removal (<0.5 µm), utilization of standard chemicals for Si-based solar cell technology and potential suitability for usage in large-scale manufacturing the proposed technique is promising for increasing of efficiency of thin wafers crystalline Si solar cell. [ABSTRACT FROM AUTHOR]

This paper presents a new analytic approach for static frequency divider design. It consists of derivations of analytic expressions for the self-oscillation frequency and frequency divider oscillation condition, based on the device-level circuit parameters only. Additionally, an analytic expression for frequency divider sensitivity is obtained based on injection-locking theory. The proposed approach is verified against measurement results of a static frequency divider, fabricated in SiGe BiCMOS 0.13- \mu \textm process. This approach enables fast preliminary frequency divider design based on time- and resource-efficient simulations. [ABSTRACT FROM PUBLISHER]

This paper describes the features and performance of an analog and RF device technology development on a 14-nm logic FinFET platform. An optimized single-side gate contact RF device layout shows a Ft/F\text {max} of 314/180 GHz and 285/140 GHz for N and PFinFET device, respectively. The double-side gate contact structure with contact on either end of active gate enhances the peak F\text {max} performance to 227 and 195 GHz for both N and PFinFET devices, respectively. A significant boost in the PFinFET RF performance is observed compared to 28-nm planar PFET, which is attributed to the source/drain SiGe epitaxy stressor that results in higher hole carrier mobility. On the other hand, the thin channel body of FinFET structure facilitates a better electrostatic control of gate over the channel region and hence suppresses short channel effects including the drain-induced barrier lowering. Consequently, a significantly higher self-gain ( Gm/G\text {ds})~40 and 34 for both NFinFET and PFinFET is achieved. In addition, N/PFinFETs demonstrate superior 1/f noise of 17/35 fV ^2\mu \textm^2 /Hz at 1 kHz compared to 171/106 fV ^\mathrm \mathbf 2\mu \textm^2 /Hz of 28-nm planar N/PFETs. To extend the low-voltage operation and power saving of FinFET RF platform, ultralow Vt N/PFinFETs in the range of 50 mV Vt\text{s} are also developed. Furthermore, a deep n-well process is added to the platform to provide device and circuit isolation from substrate and supply noise, while realizing the creation of new devices such as vertical NPN, PCAP, and high breakdown voltage deep n-well junction diodes. Overall, a superior Ft/F\textsf {max} , high self-gain, low 1/f noise, and robust substrate isolation characteristics extend the capability of this new 14-nm FinFET technology to the analog and RF circuit applications. [ABSTRACT FROM AUTHOR]

Heat transfer through interfaces in nanostructures is becoming ever more important in functional nanodevices. The existence of interface between two dissimilar materials overheats nanoelectronics and impacts heat transfer greatly. It is a challenge how to modulate interface to tailor the thermal transport properties of nanodevices from the perspective of atomic level. In this brief, we consider how size and interface strain affect thermal boundary resistance (TBR) as well as thermal conductivity (TC) of Si/Ge core–shell nanowires (CSNWs) using a thermal kinetic method in terms of atomic-bond-relaxation correlation mechanism and continuum medium mechanics. We propose a theoretical model to pursue the underlying mechanism on the TBR and TC that determined on the core or shell thickness, surface roughness, and interface mismatch. Our approach provides a useful guidance to the theoretical design and experimental control of epitaxial growth in the radial CSNWs for practice applications. [ABSTRACT FROM PUBLISHER]

In this work, a novel asymmetric dielectric modulated dual short gate (ADMDG) TFET is designed and their performance was analysed. The ADMDG TFET using silicon, germanium, and SiGe as channel and source materials were simulated and results are compared with conventional DGTFET. The device simulation has been performed using Sentaurus TCAD simulator. It is found that the proposed structure provides overall improved performance for silicon TFET such as higher on-current (I on = 4.2 μA), smaller SS = 40mV/decade and maximum I on /I off ratio (8.2 × 10 10 ) compared to conventional DGTFET. The on-current values obtained for SiGe source, Ge source and Ge channel ADMDG TFET are 0.22 mA, 0.69 mA and 0.14 mA respectively compared to silicon ADMDG TFET but compromises other dc parameters such as SS and I on /I off ratio. For CMOS circuits, the p-type silicon TFET of the proposed structure were also simulated and presented. Moreover, the proposed TFET structure is also simulated for different temperatures and its performance were compared and analysed. [ABSTRACT FROM AUTHOR]

Selective oxidation of the silicon element of silicon germanium (SiGe) alloys during thermal oxidation is a very important and technologically relevant mechanism used to fabricate a variety of microelectronic devices. We develop here a simple integrative approach involving vapor–liquid–solid (VLS) growth followed by selective oxidation steps to the construction of core–shell nanowires and higher-level ordered systems with scalable configurations. We examine the selective oxidation/condensation process under nonequilibrium conditions that gives rise to spontaneous formation of core–shell structures by germanium condensation. We contrast this strategy that uses reaction-diffusion-segregation mechanisms to produce coherently strained structures with highly configurable geometry and abrupt interfaces with growth-based processes which lead to low strained systems with nonuniform composition, three-dimensional morphology, and broad core–shell interface. We specially focus on SiGe core–shell nanowires and demonstrate that they can have up to 70% Ge-rich shell and 2% homogeneous strain with core diameter as small as 14 nm. Key elements of the building process associated with this approach are identified with regard to existing theoretical models. Moreover, starting from results of ab initio calculations, we discuss the electronic structure of these novel nanostructures as well as their wide potential for advanced device applications. [ABSTRACT FROM AUTHOR]

As standard planar transistors have reached their scaling limit new sophisticated architectures have found their way into mass production. One option is the Fully Depleted Silicon-on-Isolator (FDSOI) technology, which combines performance efficiency with a cost effective, planar architecture. Approximately, 75% of the process steps in FDSOI can be leveraged from the established 28 nm bulk technology, while there are certain process modules that require the introduction of new processes, i.e., low- k spacer deposition and the epitaxial growth of SiGe gate channels and Si:B, SiGe:B source/drain regions. In this article, we want to focus on the deposition of the low- k spacer, which provides low gate-to-drain capacitances. The standard SiN spacer was replaced by a SiBCN spacer. Electrical results show a clear 10% increase in ring-oscillator frequency. [ABSTRACT FROM AUTHOR]

This work aims to investigate the device performance of silicon–germanium (SiGe)/Si carbide (SiC) source/drain (S/D) asymmetric dual-k spacer underlap Fin-field-effect transistor (SiGe/SiC-AsymD-k FinFET) with Si channel for high performance and robust SRAM cell. Strain-induced mobility enhancement due to the Si1−x Ge x /Si1−y C y S/D leads to a significant drive current enhancement of the proposed device. The introduced asymmetric dual-k spacer at source side offers excellent gate control over the channel. By exploiting asymmetry in current, the authors prove that it is possible to achieve mitigation of read–write conflict in 6T SRAM bit cell. SiGe/SiC-AsymD-k FinFET SRAM offers 8.39% improvement in hold static noise margin, 14.28% in read and 18.06% in write mode over conventional FinFET-based 6T SRAM bit cell. When compared to conventional FinFET 6T SRAM bit cell, the proposed 6T SRAM bit cell shows lesser temperature sensitivity of cell stability. [ABSTRACT FROM AUTHOR]

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions (LG = 40 nm) published to date. Electrostatics and off-state leakage are maintained down to the shortest gate lengths studied, showing drain-induced barrier lowering of 30 mV/V and sub20 nA/μm Ioff at VDD = -0.5 V and LG = 40 nm. The short-channel device subthreshold slope SS and performance can be further improved by use of high-pressure annealing in hydrogen, yielding the best SSLIN and SSSAT of 71 and 76 mV/dec reported so far for any LG = 40-nm Ge pMOS channel device. [ABSTRACT FROM PUBLISHER]

We studied the miniband dependence on the structural parameters and shape in type-II multilayer germanium (Ge)/silicon (Si) quantum dot superlattice (QDSL) solar cell. A maximum tunable range of ground-state energy is 19% by tuning layer distance down to 0.5 nm, whereas 24.5% is achieved by adjusting the horizontal dot-to-dot spacing down to 0.3 nm. The reduction of effective bandgap is severe for cylindrical QDs than ellipsoidal and conical QDs in the ultradense QDSL, thus leading to a relatively lower conversion efficiency. On average, the thickness of QD shows a negative correlation to conversion efficiency. We observed a high conversion efficiency of 27.22% in a bilayer conical QDSL under an AM1.5 spectral irradiance and one sun illumination. [ABSTRACT FROM AUTHOR]

This paper deals with the Early effect of SiGe HBTs. Simple, analytical expressions are derived for forward and reverse Early voltages, considering different Ge profiles in the base, including box, triangular, and trapezoidal profiles. The SiGe parameters of the electron diffusion coefficient and the intrinsic carrier concentration are adopted to modify the traditional model. It is predicted that the triangular and box Ge shapes in the base of SiGe HBTs correspond to the best forward and reverse Early voltages, respectively. [ABSTRACT FROM AUTHOR]

SiGe thin films with different Ge fraction were obtained by Molecular Beam Epitaxy (MBE) on silicon (001) substrates. The SiGe thin films properties are obtained using Spectroscopic Ellipsometry (SE) in the frame of the New Amorphous model. This model demonstrates that depending on the Ge fraction high absorption coefficients of order 10 6 cm −1 were obtained. The solar cell performance of SiGe/Si heterostructures was measured using a JASCO YQ-250BX system with light source of AM 1.5 solar simulator. The experimental results obtained (y = 0.15, W a-Si: H = 2 nm) yielded to an improvement of about 1.3 mA cm −2 for the short-circuit current density, and about 2.2% for the cell efficiency compared to the conventional cell i.e. without a-Si:H thin layer (FSF). [ABSTRACT FROM AUTHOR]

In this research, the p-type Si80Ge20B3 alloys composited with YSi2 nanoinclusions were fabricated by melting spinning and then, spark plasma sintering. The metallic Y was chosen as the source of YSi2 nanoparticles. It was found that the fully dense nanocomposites were formed with the homogeneous distribution of YSi2 nanoinclusions in the SiGe matrix. The thermoelectric measurement showed that YSi2 addition reduces the electrical conductivity but increases the Seebeck coefficient, which was attributed to the decrease in carrier concentration. The thermal conductivity was suppressed for the composite SiGe-1.4%Y, which made this composition to exhibit the largest thermoelectric figure-of-merit (ZT) of 0.52. Figure-of-merit (ZT) and microstructure of the SiGe- x%Y SiGe-1.4%Y. [ABSTRACT FROM AUTHOR]

Computationally efficient modeling of the thermal conductivity of materials is crucial to thorough experimental planning and theoretical understanding of thermal properties. We present a modeling approach in this work that utilizes a frequency-dependent effective medium theory to calculate the lattice thermal conductivity of nanostructured solids. This method accurately predicts a significant reduction in the experimentally measured thermal conductivity of nanostructured Si80Ge20 systems reported in this work, along with previously reported thermal conductivities in nanowires and nano-particles in matrix materials. We use our model to gain insights into the role of long wavelength phonons on the thermal conductivity of nanograined silicon-germanium alloys. Through thermal conductivity accumulation calculations with our modified effective medium model, we show that phonons with wavelengths much greater than the average grain size will not be impacted by grain boundary scattering, counter to the traditionally assumed notion that grain boundaries in solids will act as diffusive interfaces that will limit long wavelength phonon transport. This is further supported by using time-domain thermoreflectance at different pump modulation frequencies to measure the thermal conductivity of a series nanograined silicon-germanium alloys. [ABSTRACT FROM AUTHOR]

Composition graded nanowires (NWs) have attracted increasing research interest in the application of optoelectronic devices, due to their graded bandgaps caused by the changing composition. However, the thermal transport property of composition graded NWs is not clear, which is critical for their potential applications in electronics and thermoelectrics. In this Letter taking SiGe NW as an example, we explore the thermal transport property of composition graded NWs. Molecular dynamics simulations reveal that the thermal conductivities (κ) of the composition graded SiGe NWs can be reduced up to 57% compared with that of the corresponding SiGe NW with abrupt interfaces. The κ reduction stems from the shortening of phonon mean free paths due to the inhomogeneous composition distributions. The phonon wave packet propagation analysis reveals that the composition gradient can reflect more than 70% of the wave packet energy, and phonon localization is observed in the composition graded region. Our findings suggest a promising prospect of composition graded NWs in the use of thermoelectrics and high temperature coatings, where low thermal conductivity is expected. [ABSTRACT FROM AUTHOR]

Safe-operating-area (SOA) in a high-voltage complementary silicon–germanium (SiGe) (= n-p-n + p-n-p) on silicon-on-insulator (SOI) technology is investigated from 24 °C to 300 °C. Three key reliability degradation regions are identified, including: 1) high-current; 2) mixed-mode; and 3) high-power. The degradation mechanisms, which are operative, including Auger damage, mixed-mode damage, and electrothermal runaway as well as their temperature dependences are identified. Mixed-mode damage exhibits a strong negative temperature coefficient for both n-p-n and p-n-p SiGe heterojunction bipolar transistors (HBTs) up to 300 °C, which leads to an increase in the SOA from a high-voltage perspective. Electrothermal boundaries are also explored by finding JC,{\textsf {crit}} and V{\textsf {CB},{\textsf {crit}}} across the JC – V\textsf {CB} plane up to 300 °C. Both n-p-n and p-n-p SiGe HBTs show an increase in the SOA for the electrothermal boundary as temperature increases. High-current-induced damage, on the other hand, exhibits a positive temperature coefficient, which implies that high current drive should carefully be considered when using SiGe HBT circuits operated in a high-temperature environment. However, at very high temperatures (>200°C), the high current damage processes show annealing properties, which implies that at sufficiently high temperatures, annealing can dominate over Auger damage and potentially extend the SOA of the technology. [ABSTRACT FROM PUBLISHER]

The paper presents a novel 5.15GHz-5.825GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14dB power conversion gain, 6dBm input third-order intercept point (IIP3), 6.85dB double side band (DSB) noise figure. The total mixer current is about 1.54mA from 1.4V supply voltage including output buffer. The total dc power consumption is 2.15mW. [ABSTRACT FROM AUTHOR]

In this paper, we present extensive random telegraph signal (RTS) noise characterization in SiGe heterojunction bipolar transistors. RTS noise, observed at the base, originates at the emitter periphery while at the collector side distinct RTS noise is observed at high-injection that originates from the traps in the shallow trench regions. Time constants extracted from RTS during aging tests allow understanding of trap dynamics and new defect formation within the device structure. This paper provides the first demonstration of RTS measurements during accelerated aging tests to study and understand generation of defects under bias stress in SiGe HBTs operating at the limit of their safe-operating area. [ABSTRACT FROM AUTHOR]

A heterojunction bipolar transistor (HBT) trigger Silicon Controlled Rectifier (SCR) device (HTSCR) in the 0.35 μm Silicon-germanium (SiGe) BiCMOS technology is proposed for Electrostatic Discharge (ESD) protection in this paper. The trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration (BV CEO ). The underlying physical mechanisms critical to the trigger voltage are demonstrated based on the transmission line pulsing (TLP) measurement results and physics-based simulation results. The experiment results show that the trigger voltage of the fabricated HTSCR reduces to less 64% of that of the conventional MLSCR, and I t2 of the HTSCR is 80% more than that of the conventional MLSCR. In order to reduce the chip area, an optimized HTSCR (OHTSCR) is also proposed. The OHTSCR has a smaller layout area and a lower trigger voltage. [ABSTRACT FROM AUTHOR]

This paper presents a Ka-band 4-bit BiCMOS digital step attenuator with maximum attenuation of 7.5 dB (16 states). The proposed attenuator design is based on switched T-bridge network including phase correction network and is fabricated in 0.13 μm SiGe BiCMOS technology. Attenuator with phase correction structure shows root mean square (RMS) amplitude errors < 0:8 dB at 31 to 33 GHz and the RMS insertion phase varying from 2.8° to 5.8° over 31 to 33 GHz. The measured insertion loss is 19 dB and total chip size including pad is 1:92 × 0:4 mm². [ABSTRACT FROM AUTHOR]

The Ni(Pt)/Si-cap/SiGe silicidation process has been optimized by modulating the Si-cap layer thickness and a cold Si preamorphization implantation (PAI), which effectively reduces the sheet resistance (Rs). In addition, it is revealed that PAI can obviously increase the Ni(Pt)Si grain size for a lower Rs. [ABSTRACT FROM AUTHOR]

This paper proposes a novel type of compact circuit model for silicon germanium (SiGe) heterojunction phototransistor (HPT) that is justified from the distributed nature of both its electrical and optical behaviors. The proposed model is based on a modified Ebers–Model structure and contains 28 different parameters. It is independent of the nature of the base bias (current or voltage), as opposed to existing models. The method to identify that the architecture of the model is original as it makes use of a drift–diffusion numerical simulation of a SiGe HPT adjusted to experimental data. A good fit of the model both in amplitude and phase is obtained through the nine optomicrowave S-parameters. [ABSTRACT FROM PUBLISHER]

Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the W -band frequencies (75–110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high- f\mathrm{ max} multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75–110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve f\mathrm{ max} and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage W -band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. [ABSTRACT FROM AUTHOR]

Ga-rich InGaP materials are attractive applications for yellow-green spectral range optoelectronics such as light-emitting diodes and solar cells on silicon substrate. Bulk, Ga-rich InGaP films grown by metalorganic chemical vapor deposition on SiGe virtual substrates were investigated in the V/III compositional ratio range of 44.3--402 using chamber pressures from 100 to 200 mbar. These films were nominally lattice matched to the SiGe virtual substrate with a bandgap energy of 2.07--2.09 eV at low temperature (10 K). The authors show that the surface morphology of the Garich InGaP films was dependent on the growth conditions, including the V/III gas phase ratio, pressure, and growth rate. By optimizing the growth conditions, the authors achieved improved surface morphologies of the Ga-rich InGaP films. The hillock density of the films produced using a V/III gas phase ratio of 44.3 and 75.4, a growth pressure of 100 mbar, and a growth rate of 0.9 lm/h was about an order of magnitude lower (30.3--50 x 104cm-2) than that observed using higher V/III gas phase ratios such as 201 and 402. An increase in luminescence efficiency of Ga-rich InGaP materials was observed when the hillock density is lower. The authors discuss the mechanisms of the hillock formation. [ABSTRACT FROM AUTHOR]

Simulation results are reported on the trapping MOS structure, which is a new metal insulator semiconductor pixel concept. Using a quantum well (QW) as a buried gate, I will show that this device is the ultimate design for photon sensitive pixels when pixel size is the criterion. The device reduces to only one transistor, which acts as a charge collecting device and amplifier and it is randomly addressable. I study here the device based on a silicon–germanium material couple, but the principle can be implemented with other materials. The photo-generated charge is collected by a buried gate based on a QW, and is able to selectively localize carriers that modulate the source–drain current in the readout mode. The device simulation is based on the quantum density gradient method, which had shown to give good results with respect to previous experimental studies. They are applied in the case of thin (20 nm) buried SiGe layers, which is comparable with an earlier structure using traps for charge retention. The simulation of this structure based on actual silicon germanium technologies is robust enough to assess the practical feasibility of the device. Downscaling to deep submicrometer sizes is possible with favorable consequences regarding the pixel’s sensitivity. [ABSTRACT FROM PUBLISHER]

In this paper, a 1-Transitor (1-T) capacitorless dynamic random access memory (DRAM) using bandgap-engineered silicon-germanium Bipolar ionization metal oxide semiconductor field effect transistor (I-MOS) is investigated through numerical simulations. We have demonstrated the application of the proposed Si0.6Ge0.4 Bipolar I-MOS for realization of a 1-T capacitorless DRAM. The proposed device can achieve hysteresis at significantly lower drain voltages ( V\mathrm{LD} =0.45 V to V\mathrm{LU} =1.15 V), in comparison to the inversion mode device ( V\mathrm{LD} = 8 V to V\mathrm{LU} =11 V). In addition, the proposed 1-T capacitorless DRAM exhibits a wider hysteresis window ( \Delta \textV ) of the order ~700 mV and a sensing margin ( \Delta \textI ) of ~5 orders in comparison to the inversion mode based 1-T capacitorless DRAM. Moreover, the proposed 1-T capacitorless DRAM exhibits the retention time of ~750 msec and ~320 msec for T = 25 °C and T = 85 °C, respectively. The proposed 1-T capacitorless DRAM also shows nondestructive read and an extreme long-term endurance. Therefore, the results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology. [ABSTRACT FROM PUBLISHER]

The types and the characteristics of the waste heat on hypersonic vehicles and the application feasibility of thermoelectric generators (TEGs) for hypersonic aircraft are discussed in this paper. Two thermoelectric generator schemes with an isothermal heat source and a variable temperature heat source were proposed, and the corresponding models were developed to predict the performance of the waste heat recovery systems on a hypersonic vehicle with different heat sources. The thermoelectric efficiency variation with electric current, the temperature distribution of fuel and junctions, and the distribution of the thermoelectric figure of merit (ZT value) are described by diagrams. Besides, some improvements for a better performance are analyzed. The results indicate that the maximum values of thermoelectric efficiency are 5% and 2.5% for the isothermal heat source and the variable temperature heat source, respectively, and the thermoelectric efficiency improves with the temperature of the hot junction. The performance of the TEGs with variable temperature heat source is worse than that of the other TEGs under the same highest hot junction temperature conditions, and the former has a better conversion efficiency than the latter when the average temperatures are identical. [ABSTRACT FROM AUTHOR]

ABSTRACT A novel and robust method to determine the internal variable base resistance ( RB) of SiGe HBT from small-signal S-parameters measurement is developed in present work. The proposed method is adopted in two kinds of SiGe HBT compact models, MEXTRAM and HICUM. With the aid of auxiliary collector resistance, the lower and upper limits of RB are built up and a narrow variation range of RB is obtained. Thus, RB can be directly estimated from the small-signal S-parameters measurement. The proposed method is successfully applied to several sizes of SiGe HBTs and the experiment results shows that average error between the lower and upper limits of RB is less than 3% over a wide range of bias points, which can satisfy the demands of most engineering applications. Therefore, we believe that the proposed technique is a reliable routine applicable to estimate the base resistance in SiGe HBTs. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:555-560, 2017 [ABSTRACT FROM AUTHOR]

The optical response of strained SiGe alloys, as well as thin Si layers, is analyzed using a sp 3 d 5 s ∗ tight-binding model within the independent particle approximation. The theoretical results are compared to measurements obtained on samples with various Ge content and layer thicknesses. The dielectric function is extracted from spectroscopic ellipsometry allowing a separation of its real and imaginary parts. Theory and simulation show similar trends for the variation of the dielectric function of SiGe with varying Ge content. Variations are also well reproduced for thin Si layers with varying thickness and are attributed to quantum confinement. [ABSTRACT FROM AUTHOR]

This paper reports ultralow contact resistivities ( \rho c) achieved on highly doped p-SiGe with two low-temperature contact formation methods. One method combines precontact amorphization implantation with ~500 °C rapid thermal processing (RTP)-based Ti germano-silicidation; \rho c achieved was \sim 2.9\times 10^-9~\Omega \cdot cm2. The other method combines codeposited TiSi—Ti:Si =1:1—with ~450 °C RTP-based Ti silicidation; \rho c achieved was \sim 1.7\times 10^-9~\Omega \cdot cm2. When \rho c reaches minimum, the TiSi(Ge) alloy is generally amorphous with embedded small crystallites, similar to the previous observations on pure Si substrates. [ABSTRACT FROM PUBLISHER]