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SiO2/high-k dielectric stack is a candidate for replacing the conventional SiO2-based dielectric stacks for future Flash memory cells. Electron traps in the high-k layer can limit the memory retention via the trap-assisted tunneling, and there is a pressing need for their characterization. A new two-pulse C-V measurement technique is developed in this letter, which, for the first time, allows us to probe the discharge of electron traps throughout the SiO2/high-κ stack. It complements the charge pumping technique, which can only probe near-interface traps. It is demonstrated that a large number of electron traps, indeed, exist in the bulk of high-k layer. Bulk electron traps also have different discharge characteristics from those near the SiO2 /high-k interface. [ABSTRACT FROM AUTHOR]

A pulsed Q-V method enabling charge or capacitance measurements versus gate voltage of aggressively scaled, leaky (up to ~10 A/cm²), and charge-trapping high-κ MOS devices is introduced. The method does not require RF structures and can be used on MOS capacitors or MOSFETs with an oxide capacitance of 1-10 pF. The method enables the measurement of charge trapping characteristics in leaky MOS devices and allows the accurate measurement of the inversion charge without influence of trapping for the determination of mobility in leaky charge-trapping MOS devices. [ABSTRACT FROM AUTHOR]

We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance-voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO 2 interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.

This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth. The proposed pixel architecture contains a 4T pinned photodiode, a correlated double sampling (CDS) amplification stage, and an in-situ memory bank. Focusing on the sampling noise, the system level trade-off of the proposed pixel architecture is discussed, showing its advantages on the noise, power, and scaling capability. Integrated with an AC coupling CDS stage, the amplification is obtained by exploiting the strong capacitance to the voltage relation of a single NMOS transistor. A comprehensive noise model is developed for optimizing the trade-off between the area and noise. As a proof-of-concept, a prototype imager with a 30 µm pixel pitch was fabricated in a CMOS 130 nm technology. A 108-cell memory bank is implemented allowing dense layout and parallel readout. Two types of CDS amplification stages were investigated. Despite the limited memory capacitance of 10 fF/cell, the photon transfer curves of both pixel types were measured over different operation speeds up to 20 Mfps showing a noise performance of 8.4 e - .

This work explores the benefits of linear-mode avalanche photodiodes (APDs) in high-speed CMOS imaging as compared to different approaches present in literature. Analysis of APDs biased below their breakdown voltage employed in single-photon counting mode is also discussed, showing a potentially interesting alternative to existing Geiger-mode APDs. An overview of the recently presented gated pinned avalanche photodiode pixel concept is provided, as well as the first experimental results on a 8 × 16 pixel test array. Full feasibility of the proposed pixel concept is not demonstrated; however, informative data is obtained from the sensor operating under -32 V substrate bias and clearly exhibiting wavelength-dependent gain in frontside illumination. The readout of the chip designed in standard 130 nm CMOS technology shows no dependence on the high-voltage bias. Readout noise level of 15 e - rms, full well capacity of 8000 e - , and the conversion gain of 75 µV / e - are extracted from the photon-transfer measurements. The gain characteristics of the avalanche junction are characterized on separate test diodes showing a multiplication factor of 1.6 for red light in frontside illumination.