251 results on '"Packaging Density"'
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52. High-Performance TSV Architecture for 3-D ICs
53. Optimal aspect ratios for minimal-area standard-cell integrated circuits
54. Architecture-compiler synergism in GaAs computer systems
55. Systolic arrays - from concept to implementation
56. BiMOS devices give designers the best of two worlds
57. Trends in advanced packaging technology
58. Self-calibration and oversampling make room for more digital circuitry on monolithic ADCs
59. Physical limits to the useful packaging density of electronic systems
60. Eurocard packaging suits a wide range of plug-in modules
61. Salicide: advanced metallization for submicrometer VLSI circuits
62. GaAs ROM hits 4 Gbytes/s
63. BGAs stepping into high-pin-count role
64. SunDisk, NEC ally in flash; plans 256-Mbit device for use in 500-MByte PC cards
65. Packaging debate rolls on
66. BGAs are extending their connections
67. PLD makers tiptoe toward 0.5 microns
68. One-micron process ups complexity of gauging ASIC performance
69. Small boards keep stacking up
70. Memories holding on to more bits
71. Packaging conference high on chip-on-board
72. IC makers are packing it in; search for tomorrow's cost-effective solutions begins
73. Papers ponder packaging; surface mount conference addresses high density
74. New fab process speeds up AT&T's FPGAs; different architecture promised for early next year
75. Lattice fields FPGA; uses E2PROM programming
76. Litho's light still bright
77. Chip makers target read channels
78. DRAM dynamics daunting for suppliers; denser devices force reassessment of cost structures
79. Altera tips new EPLD architecture
80. Heat demands advanced SMT packages for power use
81. The Japanese thin down for the '90s; use of thin small-outline packages is spreading beyond memory
82. External switchers come of age
83. PLDs will blur into ASICs
84. Actel plays to capacity with 8,000-gate FPGA
85. E-beams tackle MCM testing; probing wire networks in multi-chip modules cuts test time
86. Actel FPGAs: take 2; new line is designed for better gate utilization
87. Three-metal-layer TAB emerges
88. Fine-pitch bursts onto the market
89. The silicon challenges of the 1990s
90. Silicon atoms manipulated in IBM study
91. Thin means power in chip maker's art
92. Firm hopes to stack chips in its favor
93. Motorola, TRW develop new chip with more power
94. VLSI packaging for performance
95. Processors and PC chip sets merge: first target will be notebook computers
96. IBM moves to 'cubing' -- 3D semiconductor technology
97. Very small package hopes for bit IC impact
98. FIM plates temper converter heat
99. Technique boosts 3-D memory density
100. Group eyes 3-D packaging
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