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We demonstrate an accurate measurement of the interface trap density and the stress-induced dielectric charge density in Si/high-/spl kappa/ gate dielectric stacks of metal-oxide-semiconductor field-effect transistors (MOSFETs) using the direct-current current-voltage (DCIV) technique. The capture cross section and density of the interface traps in the high-/spl kappa/ gate stack were found to be similar to those of the Si/SiO/sub 2/ interface. A constant-voltage stress of the p-channel MOSFET in inversion is shown to result in a negative dielectric charging and an increase in the interface trap density.

Analytical expressions are derived for the temperature dependence of the peak current amplitude, peak gate voltage, and current-voltage linewidth of the basewell terminal current in metal-oxide-silicon transistors (MOSTs) due to electron-hole recombination at the interface traps. They are verified by experimental data. It is shown that temperature dependence of the basewell terminal current cannot distinguish a discrete energy level from a distribution of energy levels of the interface traps in the silicon energy gap, because the interface traps measured by surface recombination current are those traps with energy close to midgap. A demonstration is given for the accurate determination of the local temperature inside the transistor using the ideal exponential dependence of the collector current on the emitter-base forward-bias voltage.

Bias temperature instability (BTI) in FinFET transistors was investigated by charge-pumping (CP) and gated-diode measurements using n+/p- /p+ structures with the gate interface identical to that in SOI-FinFETs. The results show greatly improved sensitivity for gated diode measurements than for CP. The pre-stress interface trap density was found to be NIT ≅ 1011 cm-2 for SiO2/2 nm-HfSiON/TiN/polySi-capped gate stacks, which is about one decade larger than in planar devices. The kinetics of ΔNIT(t) under negative bias stress conditions (NBTI) suggests NIT is generated by Si-H bond breaking. The mechanism for interface trap generation under positive bias stress conditions (PBTI) requires further investigation.

Low-frequency-conductance-voltage (LFGV) method for analysis of heterojunction bipolar transistors (HBTs) is presented. The method gives accurate quantitative values for the important minority-carrier transport parameters that underlie the transistor performance, such as the base diffusion length, lifetime, diffusion coefficient and transit time. The method also allows a detailed analysis of the current gain and emitter injection efficiency. The analytical model and experimental methodology are demonstrated for a Si/Ge/sub x/Si/sub 1-x//Si HBT with a trapeziodal and linearly graded Ge profiles in the base. The LFGV method is general and can be applied to other bipolar transistors, including those based on III-V materials.

The base current relaxation transient following reverse emitter-base (EB) bias stress and its effect on time-to-failure (TTF) determination are examined in self-aligned and nonself-aligned silicon bipolar junction transistors (BJTs) with thermal and deposited base oxide. A quantitative model indicates that the transient is due to a reduction of the stress-generated positive charge trapped in the oxide layer near the emitter-base junction due to holes tunneling from oxide hole traps to silicon band states or SiO/sub 2//Si interface traps. The neutral oxide hole traps may be quickly recharged through hole tunneling or hole injection into the oxide during further reverse-bias stress. A delay time of /spl sim/10/sup -3/ s was observed after the termination of stress before base current relaxation begins, which affects the extraction of the ac operation TTF from dc stress measurements.

The physical degradation mechanisms of silicon bipolar function transistors at high forward current densities were delineated quantitatively using three n/p/p and one p/n/p state-of-the-art submicron polysilicon-emitter transistor technologies. The increase of the operating current gain and decrease of emitter series resistance from million-ampere per square centimeter stress current are related to hydrogenation of the electronic traps at the metal-silicide/polycrystalline-Si and polycrystalline-Si/crystalline-Si emitter contact interfaces. A demonstration of the 10-year operation Time-to-Failure extrapolation methodology is also presented.

Experimental evidences are given which demonstrate that degradation of the common-emitter forward current gain h/sub FE/ of submicron silicon npn bipolar transistors at low reverse emitter-base junction applied voltage is caused by primary hot holes of the n/sup +//p emitter tunneling current rather than secondary hot electrons generated by the hot holes or thermally-generated hot electrons. Experiments also showed similar kinetic energy dependence of the generation rate of oxide/silicon interface traps by primary hot electrons and primary hot holes. Significant h/sub FE/ degradation was observed at stress voltages less than 2.4 V.

An experimental technique is described for accelerated time-to-failure measurement of bipolar junction transistors under low-voltage emitter-base reverse-bias stress. Acceleration of 100 or more can be attained enabling ten-year operating life extrapolation at low operation voltages (/spl les/3.3 V) in less than 100 hours. The technique, the current acceleration method, exploits the large punch-through current when the collector is shorted to the base during the stress. The technique also provides a means to determine the degradation kinetics and fundamental failure mechanisms at low power supply voltages (3.3 V, 2.5 V, or lower) and low hot carrier kinetic energies. >

A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated. It uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a p/n junction isolation well to monitor the change of the oxide and interface trap density. The dc base and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping. >

Minority-carrier electron lifetime, mobility and diffusion length in heavily doped p-type Si were measured at 296 and 77 K. It was found that a 296 K mu /sub n/ (pSi) approximately= mu /sub n/ (nSi) for N/sub AA/ 3*10/sup 18/ cm/sup -3/, in contrast to the opposite dependence for mu /sub n/ (nSi) in n/sup +/ Si. >

A method for a quantitative charge-control analysis of bipolar base-junction transistors with a Gaussian dopant impurity-concentration profile is demonstrated. Analytical expressions for the base transit time are given for two different Gaussian impurity-concentration profiles with the peak concentration at the edge, and within the quasi-neutral base layer. It is also shown that approximating the Gaussian profile by a simple exponential profile results in only an insignificant error in the charge-control analysis.

As CMOS trends continue to scale for future technology nodes, three-dimensional (3D) multi-gate field effect transistors (MugFETs) could be a viable approach. One type of MugGET of particular interest is the FinFET in which a silicon fin is defined on a buried oxide (BOX) layer. The FinFET is attractive because it is compatible with conventional CMOS processing. However, due to the crystal orientation of the fin sidewalls, their interface with the gate dielectric may contain more interface states, as well as be more sensitive to stress-induced degradation than planar devices. Therefore, these interface states and their impact on longterm operation must be characterized. FinFETs on BOX, however, do not have a substrate contact for traditional interface state characterization methods. To circumvent this issue, a gated diode FinFET test structure can be used, which emulates a planar device configuration allowing interface characterization techniques such as charge pumping (CP) [1, 2] and DC gated-diode current-voltage (DCIV) measurements [3, 4]. To determine which technique best characterizes sidewall interfaces; CP and DCIV measurements were used to monitor the time evolution of interface state generation and oxide charging during bias temperature instability (BTI) tests of the gated diode FinFETs.

A method is proposed for a thorough characterization of semiconductor substrates in terms of transport and recombination parameters. The method is based on exploiting the fundamentally simple geometry of a lateral bipolar transistor in low injection. Accurate two‐dimensional numerical solutions of the continuity equation show how the collector current depends on geometry elements and recombination parameters. In addition to the steady‐state analysis, the frequency dependence of the collector current was determined for a more direct assessment of the bulk and surface recombination. The theoretical results were experimentally demonstrated by measuring the surface recombination velocity and bulk lifetime in a silicon wafer.

A nondestructive photoluminescence (PL) method for measurement of the bulk lifetime tau and interface recombination velocity S is presented. The method is based on an exact analytical solution for the PL decay in a thin semiconductor layer, S and tau are obtained by analyzing the PL-decay response to a pulsed laser excitation for layers with different thicknesses. The decay analysis is done in the frequency domain, which improves accuracy and suppresses noise. The method is demonstrated on isotype double AlGaAs-GaAs-AlGaAs heterostructure, but it is also applicable for thin layers bounded by interfaces with different recombination velocities, such as SOI, GaAs-Si, and Si/sub 1-x/Ge/sub x/-Si systems. >

The present study was undertaken to determine the effect of iontophoresis on the transdermal delivery of growth hormone releasing factor (GRF 1–44), a peptide shown to be effective in promoting linear growth in short-statured children. A reservoir patch with a conductive peptide gel was used for this purpose and the delivery of the peptide was monitored in vivo in hairless guinea pigs using a pulsed voltage generator specifically designed to provide a current limit. The current limit selected for the present study was 0.17 mA/cm 2 at 50 KHz and 50% daty cycle. The current conditions were selected based on previously performed in vitro experiments. The half life, volume of distribution and area under the curve (AUC) were determined to be 0.389 h, 8.861 and 0.453 (mg/ml) h, respectively from an intravenous administration of a 10 μg/kg dose in the same speries. Using this information, a flux of 3.16 μg/h was calculated based on a steady-state plasma concentration of about 0.20 ng/ml. This steadystate level was similar to a peak plasma level achieved after a subcutaneous dose of 10 μ/kg. An in vivo animal model, fabrication of a patch System and design of a unique pulsed voltage generator with current limiting feature have been shown, which can be used to determine the iontophoretic deiivery of compounds of interest.

New DC methods to measure the collector resistance R/sub C/ and emitter resistance R/sub E/ are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R/sub C/. R/sub E/ is obtained from the measured lateral portion of R/sub C/ and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R/sub C/ on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R/sub C/ is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R/sub E/ a value for the specific contact resistance for the polysilicon emitter contact of rho /sub c/ equivalent to 50 Omega - mu m/sup 2/ is obtained. >

A novel nondestructive and contactless experimental method for measurement of the minority-carrier lifetime tau and surface recombination velocity S is presented. The method is based on the analysis of the photoluminescence (PL) time decay after laser excitation. The PL decay is analyzed in the frequency domain, which allows accurate extraction of both tau and S independently from the same measurement. Closed-form analytical solutions are derived for the PL signal in the frequency domain. The novel technique is able to measure accurately subnanosecond lifetimes. It can also measure S on heavily doped semiconductors. The method, frequency-domain photoluminescence (FDPL), is demonstrated in Si, GaAs, and InP materials. >

Minority-carrier diffusion length L, lifetime tau , and diffusion coefficient D in n-type Si are measured at 296 K in the doping range from 10/sup 18/ cm/sup -3/ to 7*10/sup 19/ cm/sup -3/. The measurement is based on a lateral collection of carriers generated by a spatially uniform light. The distance between the illumination edge and the collection junction is defined by photolithography. This allows simultaneous and independent determination of all transport parameters in the same material. A self-consistency and accuracy check is provided by the relation L/sup 2/=D tau . Details of experimental procedures are described. Empirical best-fit relations for the three parameters are given. The extraction of lifetime and diffusion coefficient was done in the frequency domain, which allows for straightforward elimination of parasitic effects in the nanosecond and subnanosecond range. >

The recombination lifetime under high‐injection conditions in the base of n+/p−/p+ diode was investigated on the basis of the relation between electroluminescence and terminal current. For carrier plasma densities up to 1017 cm−3 the relation between the electroluminescence signal and the current through the device is linear and dominated by the heavily doped region recombination. This relation becomes sublinear for higher carrier density due to Auger recombination in the bulk of the p− base. The Auger recombination coefficient is extracted by fitting the experimental sublinearity with numerical solutions that express the electroluminescence signal as a function of the terminal current. In the 1017–6×1017 cm−3 carrier plasma density, the Auger coefficient was found to be 1.77×10−30 (±10%) cm6 s−1 at room temperature.

The mathematical analysis and parameter‐extraction process for a new characterization method are presented. This method allows simultaneous measurement of the minority‐carrier lifetime, diffusion coefficient, and diffusion lengths as well as surface recombination velocity. The technique employs semi‐infinite two‐dimensional photodiodes and uniform, instead of focused, illumination. The paper deals with the derivation of exact closed‐form solutions associated with two‐dimensional devices and discusses the simultaneous extraction of minority‐carrier transport parameters.

To explain the principles and indications of gamma knife radiosurgery and to illustrate the correlated neuroimaging features.Between December 1999 and July 2007, 1620 patients were treated by GK for a large variety of indications (metastasis 26%, vascular malformations 7%, trigeminal neuralgia 14%, pituitary adenoma 3%, primary CNS tumour 8%, other tumours 6%, vestibular schwannoma 19%, meningioma 17%, functional disorders1%). The patients benefited from MRI follow-ups.MRI is the imaging technique of choice for Gamma knife radiosurgery (GKRS) in almost all indications. Computed Tomography, Digital Subtraction Angiography and Positron Emission Tomography have an additional role in some indications. Significant MRI data is illustrated in most indications. Evaluation of the treatment is mainly performed using MRI follow-up studies. The main features of these MRI follow-ups are described. Stabilisation or shrinking of the lesions volumes was generally observed. T2 relaxation times were also modified in and around the treated target areas, in patients responding to treatment and without any symptomatic complications. Modifications in contrast uptake were also observed in those patients. A few patients presented symptomatic complications associated with T2 signal anomalies. The interpretation of those modifications is discussed.MRI is the method of choice for GKRS planning in most indications. Imaging changes after radiosurgery provide the best quality control available to assess the response to radiosurgical treatment and to identify and monitor potential complications.

After over 10 years of intensive study on high-k dielectric and metal gate electrode to replace silicon based materials (Si02 or SiON gate dielectric and polysilicon gate) in the complementary-metal-oxide-semiconductor (CMOS) application, it was claimed that hafnium based dielectric and metal gate are finally ready to be implemented in 45nm technology and beyond. It was reported that the minority carrier mobility in the metal-oxide-semiconductor field effect transistor (MOSFET) with hafnium oxide (Hf02) was improved significantly and performance reaches the comparable level of that of MOSFETs with silicon oxynitride even with further scaled equivalent oxide thickness (EOT). Since the device performance has been optimized, the focus of the high-k dielectric study shifts toward the device reliability issues.

Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (DeltaVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric

We combine conventional metal oxide semiconductor (MOS) gated diode measurements and very sensitive electrically detected electron spin resonance (ESR) measurements to detect and identify negative bias temperature instability (NBTI) generated defect centers in fully processed HfO2 pMOS field effect transistors (pMOSFETs). The spectra were found to be quite different from those generated by NBTI in conventional Si/SiO2 based devices. The defect spectra generated by long term stressing differ from the short term stressing signals and are somewhat similar to those observed in plasma nitrided oxide Si/SiO2 based devices. These traces are similar in that their ESR g values are virtually identical. Our results strongly suggest that, in these HfO2 based devices, NBTI defects are located in the interfacial SiO2 layer.

A systematic study to optimize gate stack constituents (interface, high- ?, metal gate) to maximize carrier mobility with aggressively scaled equivalent oxide thickness (EOT) is presented. We identify ultra-thin thermal oxide, atomic layer deposited HfSiON and optimized plasma nitridation performed in sequence as the optimized run path for sub-nm EOT scaling with high carrier mobility. A metal gate deposition process that minimizes the incorporation of impurities in HfSiON is also vital to maintaining good mobility at low EOTs.

Charge trapping in high-k transistor gate stacks shifts the threshold voltage and may affect the channel mobility. Since both electrons and holes may potentially contribute to charge trapping, it is important to determine the polarity of the trapped charge and to relate it to the stress or operating conditions. A constant-voltage stress was applied to nMOSFETs and pMOSFETs and the charge trapping in the gate stack and the interface trap generation was monitored by the DCIV method. Detailed band diagram for each stress condition is used to correlate the measured charge trapping and the interface trap generation/annihilation to the dominant tunneling current component and to delineate the physical mechanisms and charge-trapping pathways.

We demonstrate, for the first time, a HfLaSiON/metal gate stack that concurrently achieves the following: low threshold voltage (VT =0.33V), low equivalent oxide thickness (EOT=0.91nm) (Tinv =1.3nm) and 83% SiO2 mobility. Key enablers of this result are 1) La doped HfSiON for n-FET VT tuning 2) HfO2:SiO2 alloy ratio with 10% SiO2 suppressing crystallization up to 1070degC, 3) interlayer SiO2 (IL) to reduced bias temperature instability (BTI) and 4) plasma nitridation (N*)/post nitridation anneal (PNA) sequence for EOT scaling. This work advances high-k/band edge metal gate (MG) efforts by showing scalability of HfLaSiON to EOT=0.91nm without mobility or BTI tradeoff, while matching the VT of a SiO2/n-PolySi control

Using a combination of electrical characterization techniques, one can separate contributions from generated and pre-existing electron traps inherent to high-κ dielectrics, as well as identify process-induced effects in the device characteristics.

The effects of Ge in the epitaxial-base on the reliability of Si/Ge/sub x/Si/sub 1-x//Si heterojunction bipolar transistors were investigated. The ten-year time-to-failure under emitter-base junction reverse-bias stress was measured at the designed operation voltage by the current-acceleration method and compared to that of Si bipolar junction transistors with no Ge (x=0). The investigation shows that the Ge incorporated by the reduced pressure chemical vapor deposition epitaxial technology to give the ramp-type Ge profile has no adverse effects on the transistor reliability.

A second current-acceleration method for measuring the reliability of silicon bipolar transistors under reverse emitter-base bias stress is demonstrated in this paper. The low-voltage operation condition in submicron transistors may be attained during the stress experiments, providing an accurate determination of the transistor's operation time-to-failure (TTF) without extrapolating from higher voltage stress data. Two different current-acceleration stress methods are demonstrated in one transistor design and compared with the traditional voltage-acceleration method using the carrier kinetic energy as the independent variable. It is shown that the traditional voltage-acceleration method can give an erroneous and larger extrapolated time-to-failure by several orders of magnitude in some devices.

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 /spl mu/m n-channel Si MOS transistor with about 10/sup 11/ traps/cm/sup 2/ generated by channel hot electron stress.

Random telegraphic signals (RTS) are observed in the forward‐biased dc base current of electrically stressed silicon bipolar transistors. The RTS noise in the base current is shown to originate from random trapping of electrons at the stress‐created oxide and interface traps located over the oxide‐covered emitter‐base junction space‐charge region. The observed pulse width (∼0.1–100 s), the uniform height of the pulses (∼1% of dc base current), and their dependencies on temperature and VBE (emitter/base bias voltage), exp(qVBE/nkT) with n=2, are interpreted by the two‐step model consisting of electron tunneling between the oxide and interface traps, and the recombination of Si band electrons and holes at the interface traps.

New MOS transistor and metal contact/interconnect degradation mechanisms at high current densities (HJ) and low voltages (

Direct measurements of the minority-hole transport parameters in degenerate n-type silicon were done by analyzing transient photocurrent in the frequency domain. Minority-hole mobility is found to increase with doping for dopings larger than 4*10/sup 19/ cm/sup -3/. The ratio of minority-hole to majority-hole mobility is found to be about 2.8 at N/sub D/=7.2*10/sup 19/ cm/sup -3/. The measured lifetime shows a strongly Auger-dependent mechanism. The extracted Auger coefficient at 296 K is C/sub n/=2.22*10/sup -31/ cm/sup 6/-s/sup -1/, and is in agreement with that reported on other works. Self-consistent checking is used to validate the accuracy of the measured results. >

Temperature dependence of the minority hole mobility μp(ND,T) in heavily doped n+ silicon in the doping range from 1018 to 2.4×1019 cm−3 was investigated. The preliminary measurements show that the mobility is strongly temperature dependent. For temperatures below 200 K the minority‐carrier hole mobility increases with increasing doping, in contrast to the opposite dependence for the majority hole mobility in p+ silicon. Analytical fits to the measured data useful for low‐temperature modeling for bipolar devices are given.

An analysis of the current dependence is performed using a partitioned transistor equivalent circuit that includes the distributed effects of the emitter contact. It is shown that the emitter resistance increases with current if emitter current crowding is important. The current dependence of the emitter resistance is extracted as a function of the specific contact resistance and the base and emitter sheet resistances. >

A new characterization method is proposed based on measurements of the electroluminescence signal as a function of the terminal bias and the modulation frequency. The method is not susceptible to space charge region and emitter recombination currents and provides a direct measure for the separation of Fermi levels at the edge of the principal quasi-neutral region. The extraction of parameters, such as the series resistance and the minority carrier lifetime, is experimentally demonstrated on a silicon diode. The method can be extended to heterojunction bipolar transistors to measure the Fermi level drop across the heterojunction.