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Flexible In2O3 nanowire transistors gated by microporous SiO2-based solid electrolytes are fabricated on paper substrates at room temperature. Low-voltage (1.0 V) operation of these devices is realized owing to the large electric-double-layer capacitance of (1.73 μF/cm2 at 20 Hz) of the microporous SiO2 solid electrolytes, which were deposited at room temperature. The subthreshold swing, current on/off ratio, and field-effect mobility of the paper-based nanowire transistors are estimated to be 74 mV/decade, 1.7×106, and 218.3 cm2/V·s, respectively. These low-voltage paper-based nanowire transistors show promise for use in portable flexible paper electronics and low-cost portable sensors.

The aim of this work is to propose a compact analytical model for the Low Frequency Noise (LFN) in Junctionless Nanowire Transistors (JNTs). Since JNTs work differently from inversion mode transistors, the noise is also expected to behave differently. To the best of our knowledge, no analytical models have been presented for LFN in these devices. The proposed model is validated through numerical simulations. Experimental results are also used to demonstrate its applicability.

A study of Junctionless Nanowire Transistors (JNTs) is presented in this work, with emphasis on verifying the applicability of the charge pumping method for the analysis of interface traps. To the best of our knowledge, this is the first work to use this method in JNTs. The first step is the analysis of the performance using numerical simulations. It is stated that a transient current is observed in the devices with the charge pumping method application and increases with the trap density. Simulated and experimental data of Junctionless Nanowire Transistors show how this method can be useful and its applicability to verify the JNTs interface quality.

Gate-all-around (GAA) cylindrical channel Si nanowire field effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3-D TCAD simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3nm gate length. The performance of n-type silicon nanowire transistors is benchmarked using predictive TCAD device simulation.

In this work, we have designed and analyzed the performance characteristics of n-type silicon based multi-channel junctionless nanowire transistors (JLNTs) for both single gate and double gate configurations. Numerical simulations using CVT (lambardi) model has been carried out to investigate the effects of different device parameters such as gate insulator dielectric, gate insulator thickness, and separating materials between channels. To illustrate and evaluate the performances, input characteristic curves, transconductance, and Ion/Ioff ratio of the devices have been extracted. It is observed that Ion/Ioff ratio are directly affected by the variation of dielectric and thickness of the gate. Devices having a high-κ dielectric provides steeper characteristics and better Ion/Ioff ratio for both the structures. The value of transconductance is also found to be greater for high-κ dielectric in both configurations with the double gate providing a higher value compared to the single one.

This paper presents the simulation study of characteristics of an 11nm Silicon Nanowire Field Effect Transistor. This architecture is applicable for ultra-scaled devices up to sub-11 nm technology nodes that employ silicon films of a few nm in thickness. The defining characteristics of ultrathin silicon devices such as Short Channel Effects and Quasi-Ballistic transport are considered in modelling the device. Device geometries play a very important role in short channel devices, and hence their impact on drain current is also analyzed by varying the silicon and oxide thickness. The proposed simulation model gives a detailed outlook on the characteristics of the nanowire device in the inversion regime.

The ballistic hole transport properties in rectangular cross-sectional germanium nanowire transistors with various geometries were studied based on the “Top of the Barrier” model. Then, by an extension of this model, the quasi-ballistic hole transport was discussed taking into account phonon and surface roughness scattering in the channel and source-to-drain direct tunneling. Among several nanowire geometries targeted in this study, the [1 1 0]-oriented nanowire with large height along [1 1 ¯ 0] ([1 1 0]/(1 1 ¯ 0) NW) exhibited the largest ballistic current. This was understood from its large density of states and resulting high hole density. Large density of states, however, enhances backscattering in the channel. An approximation analysis of quasi-ballistic transport suggested that the [1 1 0]/(0 0 1) NW with higher mobility can outperform [1 1 0]/(1 1 ¯ 0) NW when scattering and tunneling are considered.

With feature size of transistors reducing down to sub-20 nm nodes, high mobility channel materials and novel device structures are critical to further improve the performance of transistors. Junctionless nanowire transistor (JNT) is recently proposed and regarded as promising candidate structure due to its simple fabrication process and excellent electronic properties [1]. Germanium-on-insulator (GOI) substrate is regarded as promising substrate due to its advantages of both Ge and on-insulator substrates. Although GOI-based JNTs have been reported [2,3], the performances are far from satisfactory. In this work, we fabricated high performance GOI-based JNTs with much smaller dimensions, where channel length and width are both less than 100 nm, and demonstrated their fabrication process and electrical properties in detail. Fig.1 shows SEM images of tri-gate JNTs with different dimension, (a)W/L=40nm/70nm and (b) W/L=40nm/100nm, respectively. Fig.2 shows TEM image of a GOI sample with Tge=10 nm. The original thickness of Ge film was about 50 nm. We reduced Tge down to 10 nm using a simple wet retching method as reported in our previous work [4]. Fig.3 shows the schematic diagrams of fabrication process. To reduce costs and improve efficiency, we used both optical lithography (OL) and electron beam lithography (EBL). First, we used OL to define active region of the devices. GeO2 channel passivation was carried out by ozone oxidation at 300 °C for 30 min. Then EBL was carried out to define the channel and gate electrode, which had much smaller dimensions. Finally, we used OL and lift-off process to define measuring electrodes. Fig.4 (a) shows Id-Vg characteristics of JNTs with Tge =20nm and Tge=10nm, respectively. It can be observed that Ion/Ioff ratio of the JNT with Tge=10nm is larger than 105 at Vd= -1V. The subthreshold slope at Vd= -0.1V and the drain induced-barrier lowering (DIBL) are estimated to be 110 mV/dec and 140 mV/V, respectively. With decrease of Tge, we get better device performance. Fig.4 (b) shows the Id-Vd characteristics of JNT with W/L=40nm/70nm, Na=1018 cm-3 and Tge=10nm. Liner and saturation regions are clearly exhibited. Fig.5 (a) shows the influence of temperature on Id-Vg characteristics of JNTs with W/L=40nm/70nm, Na=1018cm-3 and Tge =10nm. It can be observed that with increase of temperature leakage current increased dramatically. Fig.5 (b) shows mobility of the same JNT. The reported mobility values of a GOI JNT with Na= 1019 cm−3 [2] and a conventional Si pMOSFET [5] are also plotted for comparison. The peak mobility is larger than 200 cm2V-1S-1, which is close to that of bulk germanium with a doping concentration of 1018 cm−3. In summary, we fabricated high performance GOI-based JNTs using a Si-compatible process which combines OL and EBL. Good Ion/Ioff ratio, subthreshold slope, DIBL and mobility are extracted, which indicating that ultra-thin body GOI-based JNTs are promising for high performance circuits. The device performance can be improved by optimizing the fabrication process and device structure. Acknowledgments: This work was supported in part by the National Natural Science Foundation of China (No. 61306105). [1] J. P. Colinge et.al, Nat. Nanotechnol. 5, 225, 2010. [2] D. D. Zhao et al. Jpn. J. Appl. Phys., Part 1, 51, 04DA03, 2012. [3] R. Yu et al., Phys. Status Solidi RRL 8, 65, 2014. [4] C. Sun et al. ECS Solid State Lett. 4, P43, 2015. [5] S. Takagi et al, IEEE Trans. Electron Devices, 41,2363, 1994. Figure 1

This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which includes short-channel effects, and accounts for the dependences on the device dimensions, doping concentration, and quantum effects. It is validated with 3-D Technology Computer-Aided Design (TCAD) simulations for several device characteristics and biases as well as with the experimental results.

Through advanced electro-thermal simulations we demonstrate that self-heating effects play a significant role in ultrascaled nanowire field-effect transistors, that some crystal orientations are less favorable than others (⟨111⟩ for n-type applications, ⟨100⟩ for p-type ones), and that Ge might outperform Si at this scale. We further establish a relationship between the dissipated power and the electrical mobility and another one between the current reduction induced by self-heating and the phonon thermal conductivity.

We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes. SPICE modeling tool was used to extract the parameter from Id-Vg to Id-Vd characteristics with liner and saturation region. Dependence of source/drain parasitic resistances on nanowire width and gate sidewall thickness can be observed on the extracted parameters. Furthermore, parasitic capacitance was extracted from three-dimensional TCAD simulation with our fabricated device structure. Single sets of parameters can reproduce I-V characteristics with Lg down to 35nm for n-channel nanowire transistors. It was found that the extracted parameters will be a useful tool for characterizing the circuit performance of nanowire transistor. Therefore, this procedure is applicable to extract the BSIM4 model parameters for NW Tr. as well as other multi-gate FETs. SPICE parameters of BSIM4 were successfully extracted for tri-gate NW Tr.Dependence of Rsd on Tr. geometry and process can be observed on the parameter.Single sets of parameters for Lg down to 35nm were obtained.The parameters will be a useful tool for characterizing the circuit performance.

The fabrication of biologically inspired solid-state devices has attracted tremendous attention for decades, and the hardware implementation of artificial synapses using individual ionic/electronic hybrid devices is very important for neuromorphic applications. Herein, electric double-layer (EDL) synaptic transistors coupled by proton neurotransmitters with a multiple in-plane gate structure were successfully fabricated using SnO2 nanowires. Not only the important synaptic functions were mimicked in these devices, but also the synaptic behaviors can be modulated over a dynamic range via the multi-terminal regulation of synaptic inputs. Furthermore, a light source was used to illuminate the SnO2 nanowire synaptic transistors, which were used as the light-modulating terminals. The observed neuromorphic functions were also dynamically modulated via the light density. These excellent nanoscale synaptic transistors may find significant applications in synaptic electronics.

In this paper, we present the fabrication and characterization of gate-all-around (GAA) junctionless (JL) poly-Si nanowire (NW) transistors with a dual-gated configuration, in which a sub-gate is placed over a shorter main-gate in order to control the NW potential for the offset regions between the main-gate and S/D regions. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. Inevitable misalignment of lithographic patterning for the main-gate structure leads to asymmetrical channel offsets between the main-gate to source pad and to drain pad, respectively. That is, the length of un-gated NW close to the source pad differs from that to the drain pad. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end. Such a trend become less profound as the sub-gate bias increases.

This paper presents a novel micro-bolometer structure based on SOI gate all around Electrostatically Formed Nanowire (GAA EFN) transistors. The new design enables formation of the EFN conductive channels in the volume of the SOI devices layers, far from the top and bottom silicon/oxide interfaces, thus reducing the noise level and increasing the temperature sensitivity to 13.3%/K. Detailed electrical and thermal simulations show that the micro-bolometer structure has an effective responsivity of 1.95 × 103 A/W, noise equivalent power of 561 fW, noise equivalent temperature difference of 8 mK, and a thermal time constant of 35 msec, when operated in depletion all around mode (DAA) at the sub-threshold regime.

We present experimental results for junctionless nanowire transistors (JNTs) with different gate alignments to the nanowire. Devices with nanowire source/drain extensions (NSDE) show high series source/drain resistance due to the low doped nanowire extensions, which causes lower drive current and larger device performance variations comparing with devices in which the gate electrode overlaps with the source/drain contact pads (GSD). Due to the improved on-current GSD devices exhibit much higher cutoff frequency. The high fringing field in the NSDE JNT results in degradation of SS. An optimized “dumbbell” shape JNT structure is proposed to further improve the device performance. Our preliminary simulations demonstrate higher on-currents but also larger parasitic capacitances for the dumbbell JNT. However, the RF performance of the dumbbell JNT is still improved with a factor similar to our experiments. Much smaller fringing field for the dumbbell JNT is expected from the simulation, which can cause less device variations.

Compound contacts, formed by thermal annealing of metal-semiconductor nanowires (NWs), are prescribed for lithography-free self-aligned gate processes. Investigations of nanoscale contact metallization have revealed distinctive behaviors from their bulk counterparts, evoking reevaluation of the thermodynamics, kinetics, and resultant phases in alloyed and compound nanoscale contacts. In this chapter, we focus on several critical semiconductor materials of practical importance for devices, e.g., Si, Ge, and III–V NWs, and provide in-depth discussions on the phases of compound contacts, their reaction kinetics, and electrical properties. In Sect. 5.2, we introduce the phase selection rules that lead to multiphase coexistence in low-dimensional NW semiconductor channels. In Sect. 5.3, we discuss the kinetic processes during these solid-state reactions and present a model that can be used to distinguish the rate-limiting steps and to extrapolate the reaction kinetic parameters. In Sect. 5.4, we will introduce electrical properties of NW transistors with these compound contacts and summarize different applications of these contacts including ultrashort channel devices. This entire chapter is organized to demonstrate the promise of compound contacts in nanoscale electronics.

We experimentally investigate the one-dimensional transport through two subbands in silicon junctionless nanowire transistors. The drain-voltage dependent properties of one-dimensional transport was discussed in detail. The quantized drain current and peak-like transconductance can be identified at low drain voltage, resulting from the filling of discrete subbands. At high drain voltage, the drain current exhibits linear relationship with the gate voltage at each current-carrying mode. Moreover, the transconductance vs. gate voltage displays step-like shapes.

Silicon junctionless nanowire transistors with the typical nanowire section of 18 nm width and 30nm height are fabricated and the current-voltage characteristics are measured at low temperatures in this paper. We demonstrate the one-dimension electronic transport behavior from the quantized current steps and transconductance oscillation. Moreover, the Coulomb interaction related transport behaviors are observed below the temperature of about 30 K, supporting by the double sub-peaks in the transconductance characteristics.

The electrical characteristics of n/p Ge nanowire transistors (NWTs) with the cross section of $6\times 6\mathrm{n}\mathrm{m}^{2}$ have been studied. The ION performance and the subthreshold swing are simulated by multi-subband Boltzmann transport equation and ballistic quantum transport solvers, respectively. The performance of nGe NWTs is sensitive to the barrier height of interfacial layer due to highly-anisotropic $\Lambda$-valleys. The dimension-dependent k·p parameters based on tight-binding full band are used to address the strong confinement of pGe NWTs. Comparing to Si NWTs, the intrinsic I ON is twice as high for both n/p Ge NWTs at 28nm channel length. As the channel length is scaled down, such ION benefit is maintained till the tunneling effect comes in and degrades the subthreshold swing.

This paper reports on gate-all-around silicon nanowire field-effect transistors (FETs) built in a lateral configuration, which represent the ultimate scaling limit of triple-gate finFET devices and allow a less disruptive CMOS scaling path in terms of processing and circuit layout design. We address several of their critical technological challenges, looking in particular at doping strategies. A comprehensive review of junctionless versus inversion-mode type of transistors is here presented, evaluating the impact on the devices' operation mode and on device properties such as: variability, reliability, noise, DC and analog/RF performance. We also discuss the potential for further manufacturable co-integration options.

This paper discusses the occurrence of self-heating in Junctionless Nanowire Transistors, observed through drain current degradation in the transient regime. The analysis is made by performing experimental measurements using the Pulsed IV method in transistors with varied dimensions. It is shown that the junctionless nanowire’s susceptibility to self-heating is not high enough to significantly affect the transistor’s characteristics, where for all cases current degradation lower than 4.5% is seen.

This paper presents a compact analytical model for the static and dynamic electrical characteristics of Junctionless Nanowire Transistors. The static drain current model formulation is derived from the 2D solution of the Poisson equation with appropriate boundary conditions and long-channel devices, leading to a continuous effective surface potential that accounts for the conduction in partial depletion and accumulation regimes. The long-channel model is modified to account for short-channel effects by using the coupled solution of 3D Laplace equation with the 2D Poisson equation. The substrate bias influence on the drain current is also included in the model formulation. The charges at the device terminals are differentiated with respect to the applied biases leading to an analytical description of the transconductances and transcapacitances. The proposed model is validated using experimental data at different bias conditions and temperatures, showing very good agreement.

This paper presents the necessary adaptions on the proposed compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range. The model validation is performed by comparison against experimental results showing very good agreement, with continuous current and its derivatives in all regions of operation and temperatures.

The compositional dependence of electronic band structure in relaxed and biaxially strained Ge 1−x Sn x alloy is investigated with the first principles method. Based on energy band dispersion along the [100] crystal orientation, hole effective mass is extracted via parabolic line fit. Calculation results indicate Sn composition dependence of the hole effective mass for relaxed alloy is much less pronounced than biaxially strained alloy. And then the electronic structure of Ge 1−x Sn x -Si core-shell nano wire along the [110] direction is studied from first-principles calculation.

Ever since Intel launched its successful 22-nm Ivy Bridge CPU chip, establishing nonplanar finFET technology as a viable means of extending Moore’s law, variations of the basic finFET or the nanowire transistor have been introduced into nanoelectronics research and manufacturing efforts at an unprecedented rate.

A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high ${I}_{\rm on} /{I}_{\rm off} $ current ratio of $7\times 10^{8} $ ( $V_{\rm G} = 4$ V and $V_{\rm D} = 1$ V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

The increase of hot carrier degradation with decreasing wire width in nanowire gate-all-around (GAA) MOSFETs has been investigated through experiment and device simulation. From the systematical analysis of measurement and simulation, it is found that the increase of device degradation in narrow devices is dominantly governed by the increased current density, the large lateral and vertical fields, and the increased interface state generation rather than by the reduced floating body effects. The more significant hot carrier degradation with decreasing wire width is likely to be proportional to the surface-to-volume ratio of nanowires.

This paper aims at presenting, for the first time, an experimental comparative analysis between the main electrical parameters of Junctionless (JNT) and inversion mode nanowire (IM) transistors fabricated in SOI technology down to channel length of 10 nm. The analysis has shown that JNTs present larger immunity to SCEs with respect to IM nanowires of similar dimensions. However, JNTs have shown poorer Ion than IM devices, which could be compensated through the application of multifin JNTs, at cost of increasing area consumption.

This work presents a deep analysis on the effect of lateral spacers on the performance of the Junctionless Nanowire Transistors. An analytical model to account for the spacer influence on the device electrical behavior is proposed and validated through numerical simulation results.

This work presents an analysis of the influence of the crystal orientation on the performance of p-type Junctionless Nanowire Transistors. The main electrical parameters, such as threshold voltage, transconductance and subthreshold slope, were analyzed by means of experimental data, demonstrating that the substrate rotation can significantly worsen the electrical behavior of these devices.

This paper studies the effective mobility in n- and p-type junctionless nanowire transistors (JNT) with variable fin width from quasi-planar to nanowire devices. JNTs electrical parameters were analyzed and the results show that smaller fin width have higher mobility while the mobility decreases for quasi-planar devices. Simulations were used to analyze the mobility showing that small fin devices reach higher mobility for smaller gate bias variation above the threshold voltage and a higher mobility in the middle of the channel due to the better electrostatic coupling compared to larger devices.

In this paper, an analysis on the thermal profile of Junctionless Nanowire Transistors is made, where self-heating effects are evaluated in devices with a large 4-contact gate, comparing the results with a minimized gate structure device. Tests are performed for different fin widths and fin heights. The analysis is based on three-dimensional simulations. Results showed that the gate structure is impactful to the thermal behavior of narrow small transistors, but not wide and tall ones.

This research proposes a novel approach with vertical design space exploration (DSE) of several levels of configurable architecture design using Beyond Moore devices. ferrimagnets, Multistate Electrostatically Formed Nanowire transistors (MSET), and Magnetoresistive Random Access Memories (MRAM) are first set of devices used to explore the architectural space. Machine Learning (ML) and other scientific applications are accelerated using these architectures.

We report experimental results of the N/PBTl (Negative/Positive Bias Temperature Instability) reliability of vertically stacked Gate-All-Around (GAA) silicon nanowire (NW) MOSFETs. We benchmark the lifetime of these novel devices against FinFETs with different widths and similar gate-stack. We do not only compare the average degradation, but also the time-dependent variability. At last, we predict the impact of the nanowire diameter on the reliability using TCAD simulations. Both the experimental results and the simulations indicate that BTI reliability is not negatively impacted down to a nanowire diameter of 6nm.

This paper describes the properties and performance status of vertical III-V nanowire transistors. The development of key process modules has advanced the vertical fabrication technology and competitive device performance is reported for InAs MOSFETs and TunnelFETs. Besides the benefits in electrostatic control and the ease in integration on Si substrates, the vertical transistors offers a path towards 3D device integration as demonstrated by the stacked track-and-hold circuit where a capacitor is integrated on top of the vertical transistor for area reduction.