Performance and Opportunities of Gate-All-Around Vertically-Stacked Nanowire Transistors at 3nm Technology Nodes

Gate-all-around (GAA) cylindrical channel Si nanowire field effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3-D TCAD simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3nm gate length. The performance of n-type silicon nanowire transistors is benchmarked using predictive TCAD device simulation.