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We present the design and fabrication of complimentary metal-semiconductor field-effect transistors (MESFETs) monolithically integrated on a high-speed silicon photonics platform. The transistors were built in an existing silicon photonics process without any additional process steps or modifications to maintain consistent photonics performance. The MESFETs showed a threshold voltage of -1.4 and 2.0 V for NMES and PMES, respectively. The NMES transconductance was measured to be 46.4 μS/μm, and the cutoff frequency was shown to be 2.2 GHz. Transistors of this design can be simply integrated into silicon photonics platforms for on-chip feedback circuits. [ABSTRACT FROM PUBLISHER]

In this brief, we present a new silicon-on-insulator MESFET by using an SiGe region as a well for absorbing the holes which are generated in result of the impact ionization mechanism. The key idea in this brief is to improve the breakdown voltage and self-heating effect (SHE) by utilizing an SiGe region to decreasing the crowding of holes around the source. The well is located in the buried oxide under the channel region. Simulation results show two extra peaks created on the electric field distribution that improves the breakdown voltage. Also, the floating body effect improves due to absorbing the holes by the hole’s well and the lattice temperature decreases, so the SHE improves, too. [ABSTRACT FROM PUBLISHER]

Abstract: Designing high-performance semiconductor devices is a complex optimization problem, which is characterized by multiple and, often, conflicting objectives. In this research work, we introduce a multi-objective optimization design approach based on the Bi-Objective Mesh Adaptive Direct Search (BiMADS) algorithm. First, we assess the performance of the algorithm on the design of a silicon diode using a standard drift–diffusion model, showing that BiMADS is able to find the best solutions and to outperform the state-of-the-art algorithms. Successively, we tackle the design of MESFET and MOSFET devices, using a Maximum Entropy Principle (MEP) model; BiMADS is able to locate new designs that minimize the size of the device and provide an increased output current. Moreover, it is proved that BiMADS is able to locate promising solutions with a tight budget of objective function evaluations, which makes it suitable for large-scale industrial applications. [Copyright &y& Elsevier]

A novel backgate modulation technique alleviating limitations associated with supply-regulated polar transmitters is proposed. The backgate of a partially depleted silicon-on-insulator metal–semiconductor field-effect transistor with a breakdown voltage of 15 V is used to modulate the gain and output power of an RF power amplifier (PA). The high-impedance backgate provides high-efficiency and wide-dynamic-range modulation of PA gain. Measured results at 1.8 GHz demonstrate 16% power-added efficiency improvement at 6-dB backed-off output power, compared with the same RF PA without backgate modulation. [ABSTRACT FROM AUTHOR]

A silicon carbide (SiC) based metal semiconductor field effect transistor (MESFET) is fabricated by using a standard SiC MESFET structure with the application of a dual p-buffer layer and a multi-recessed gate to the process for an S-band power amplifier. The lower doped upper-buffer layer serves to maintain the channel current, while the higher doped lowerbuffer layer is used to provide excellent electron confinement in the channel layer. A 20-mm gate periphery SiC MESFET biased at a drain voltage of 85 V demonstrates a pulsed wave saturated output power of 94 W, a linear gain of 11.7 dB, and a maximum power added efficiency of 24.3% at 3.4 GHz. These results are improved compared with those of the conventional single p-buffer MESFET fabricated in this work using the same process. A radio-frequency power output greater than 4.7 W/mm is achieved, showing the potential as a high-voltage operation device for high-power solid-state amplifier applications [ABSTRACT FROM AUTHOR]

A novel silicon-on-insulator metal–semiconductor field-effect transistor (SOI MESFET) with controlled electric field distribution is presented in this brief. An additional layer of oxide (LO) is located in the device channel region in order to supervise the electric field distribution. The simulation results show that the LO region has excellent effects on the breakdown voltage of the device, which increases by 50% compared with that of the conventional SOI MESFET structure. Also, the maximum output power density improves by 53%. In addition, the LO region causes the improvement of the device gains and frequency parameters. Consequently, the novel SOI MESFET structure has superior electrical characteristics compared with the similar device based on the conventional structure. [ABSTRACT FROM PUBLISHER]

In this paper, a novel silicon-on-insulator (SOI) metal–semiconductor field-effect transistor (MESFET) with modified charge distribution is presented. Changing charge distribution leads to lower electric field crowding and increased breakdown voltage (VBR). For modifying charge distribution, a metal region (MR) is utilized in buried oxide of the SOI MESFET. In order to achieve the best results, the MR location and dimensions are optimized carefully. DC and radio frequency characteristics of the SOI MESFET with MR (MR-SOI MESFET) are analyzed by 2-D numerical simulation and compared with conventional SOI MESFET (C-SOI MESFET) characteristics. The simulated results show that the MR has excellent effect on the VBR of the device. The VBR of the MR-SOI MESFET structure improves by 116% compared with that of the C-SOI MESFET structure. Although drain current of the proposed structure reduces slightly, 126% improvement in maximum output power density of the device is achieved due to high enhancement of the VBR. Also, the MR leads to the enhancement of maximum oscillation frequency and maximum available gain of the MR-SOI MESFET structure. As a result, the MR-SOI MESFET structure has superior electrical performances in comparison with the similar device based on the conventional structure. [ABSTRACT FROM PUBLISHER]

The spatial dependence of transient currents induced in 4H-SiC MESFETs by various ions with the same Linear Energy Transfer (LET) but different projected ranges is evaluated. The largest signal is observed when an ion strikes the Gate-to-Drain (G-D) recess. In addition, enhanced transient currents are detected when an ion strikes the gate and the drain. The charge enhancement mechanism is clarified by using numerical simulations. Finally we discuss the effect of LET and the projected range on the charge enhancement effect. It is found that the early stage of charge collection (less than several ns) is insensitive to the projected range and energy but depends on LET. In contrast, the later stage of charge collection are independent of LET and depend on the projected range. [ABSTRACT FROM AUTHOR]

Metal-semiconductor field-effect-transistors (MESFETs) have been fabricated using a commercially available 45nm silicon-on-insulator (SOI) CMOS foundry with no changes to the process flow. Depending upon the layout dimensions, these n-channel, depletion mode devices can be designed for high current drive (IDSAT ≥ ), high operating frequency (fmax > 35 ) or enhanced breakdown voltage (VBD > 25). The design flexibility provided by the SOI MESFETs, coupled with the high performance of ULSI CMOS at the 45nm node will enable a variety of analog, RF and mixed signal applications. [ABSTRACT FROM AUTHOR]

In this paper, a consistent gate charge model for GaAs MESFETs based upon charge conservation is proposed for monolithic microwave integrated circuit power amplifier designs. This new model is capable of accurately modeling the transistor under various biasing conditions. The conventional approaches for charge modeling of GaAs MESFETs usually adopt analytical equations to fit nonlinear gate capacitors separately, which might be difficult to implement in circuit simulators whose capacitance is always the derivative of an internal state variable (charge). Moreover, compared with the conventional diode and Statz model, the performance prediction in the linear region, saturation knee region, and subthreshold region is greatly improved. Measured and modeled results of a 2\,\times\,150 \mu\ m GaAs MESFET are compared and good agreement has been obtained. Comparisons between the proposed model, diode junction model, and Statz model are also presented in this paper. In addition, a class-AB Ku-band power amplifier using a 0.18-\mu\ m GaAs MESFET process was designed with the new model for verification of the new model accuracy. [ABSTRACT FROM PUBLISHER]

Metal–semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal–oxide–semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = \150\ \nm have a current drive that exceeds 200 mA/mm with a peak fT > \35\ \GHz. This is considerably higher than the Lg = \400\ \nm MESFET with a current drive of \sim70 mA/mm and a peak fT = \10.6\ \GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg <\break \400\ \nm, resulting in an optimum MESFET gate length for this technology in the range of 200–300 nm. [ABSTRACT FROM PUBLISHER]

GaAs nanowire (NW)-based metal–semiconductor field-effect transistors (MESFETs) were constructed on flexible plastic substrates by a conventional top–down approach. The top–down approach utilized in this paper combines photolithography of high-quality GaAs bulk wafers with anisotropic chemical etching processes for preparation of GaAs NWs and photolithographic processes for formation of metal electrodes. For a representative GaAs NW-based MESFET, peak transconductance, the Ion/Ioff ratio, and the subthreshold slope are estimated to be approximately 19.7 \mu\S, \sim\!\!\10^7, and \sim100 mV/dec, respectively. The electrical characteristics of the GaAs NW-based MESFETs were maintained during 3000 times of bending cycles under maximal tensile strains of 0.77% and 1.02%. These results demonstrate the possibility of using these devices in high-speed and high-performance flexible electronics. [ABSTRACT FROM AUTHOR]

In this paper, we carry out a 2-D transient analysis of field-plate GaAs metal–semiconductor field-effect transistors (FETs) by taking surface states into account. Quasi-pulsed current–voltage curves are derived from the transient characteristics. We show that drain lag and current slump (power slump) due to surface states are reduced by introducing a field plate because the fixed potential at the field plate mitigates the trapping effects of the surface states. The dependence of lag and current slump on the field-plate length and the \SiO2 passivation layer thickness is also studied. We show that it is possible to reduce the current slump and maintain the high-frequency performance of GaAs FETs at optimum values of the field-plate length and the \SiO2 layer thickness. [ABSTRACT FROM PUBLISHER]

The paper reports a GaAs micro accelerometer by making use of the electromechanical coupling effect based on metal-semiconductor field effect transistor (MESFET). MESFET as a sensitive unit is located at high-stress region to detect the nanometers deformation under stress. The electromechanical coupling effect is validated, and at the same time, the piezoresistive effect and sensitivity, including linear, transition and saturation regions are analyzed under different voltage bias using static and dynamic testing methods. The results indicate that the piezoresistive coefficient and sensitivity of microstructure strongly depend on voltage bias. The transition region between the saturated and linear regions shows a greater sensitivity and piezoresistive coefficient. As a result, the GaAs microstructure based on MESFET can obtain higher piezoresistive coefficient and sensitivity by optimizing the combination of gate and drain voltage. [ABSTRACT FROM PUBLISHER]

The stimulated ignition of latchup effects caused by external radiation has till now proved to be a hidden hazard. However this paper presents the effect in a new light—as a new approach for detecting particles by means of a solid-state device susceptible to latchup effects. This device can also be used as a circuit for reading a sensor's signal by leaving off-circuit sensing capabilities. Given that MOS transistors are widely used in microelectronics devices and sensors, the latchup-based cell is proposed as a new structure for future applications in particle detection, in the amplification of sensor signals and also in radiation monitoring. [ABSTRACT FROM PUBLISHER]

Abstract: A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source–substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of −180 to 150°C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint''s Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications. [Copyright &y& Elsevier]

In the paper the problem of modelling DC characteristics of SiC MESFETs is presented. Some modifications of the popular Raytheon–Statz model built-in in SPICE are proposed. The original and the modified models are verified experimentally by comparison of the measured and simulated device characteristics. One of the two available today on the market SiC MESFETs–the transistor CRF24010 offered by Cree, Inc. is chosen for investigations. Copyright © 2008 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate novel MESFETs based on individual GaN nanowires. The Pt/Au Schottky gates exhibited excellent two-terminal Schottky diode rectification behavior. The average effective Schottky barrier height was 0.87 eV, with an average ideality factor of 1.6. In addition, the Schottky gates efficiently modulated the conduction of the nanowires. The threshold gate voltages required for complete pinch off were as small as -2.6 V, and transconductances exceeded 1.4 muS. Subthreshold swings approaching 60 mV/decade and on/off current ratios of up to 5times108 were achieved. These results show that the Schottky gate has the potential to significantly improve the performance of GaN nanowire field-effect devices. [ABSTRACT FROM PUBLISHER]

The influence of field plates and surface traps on silicon carbide MESFETs for microwave operation was investigated. By increasing the length of gate-connected field plates from 50 to 800 nm, it was possible to increase the gate-drain breakdown voltage of the devices from 125 to 170 V. At the same time, the current slump effect of traps in the passivation oxide was reduced. By using a combination of field plates and a passivation oxide with low interface trap density, it was possible to reach an output power density of 8 W/mm at 3 GHz. [ABSTRACT FROM AUTHOR]

The authors demonstrate that silicon-on-insulator (SOI) MESFETs can be fabricated alongside SOI CMOS with no changes to the foundry process flow. The MESFETs operate in depletion mode with a threshold voltage of -0.6 V for a gate length of 0.6 μm. The breakdown voltage of the MESFETs greatly exceeds that of the CMOS devices and varies in the range of 12-58 V depending upon the channel access length, i.e., the distance from the edge of the gate to the edge of the drain region. For MESFETs with a gate length of 0.6 μm and an access length of 0.6 μm, the peak cutoff frequency exceeds 7 GHz. The maximum available gain increases with drain bias and values of fmax range from 17 GHz at VDD = 2 V to 22 GHz at VDD = 8 V. [ABSTRACT FROM AUTHOR]

Abstract: It has been demonstrated that sub-micron metal–semiconductor field-effect transistors (MESFETs) can be fabricated using a commercial 3.5V silicon-on-insulator (SOI) CMOS foundry with no changes to the CMOS process flow. The SOI MESFETs demonstrate excellent RF capabilities and can operate at voltages that are at least 3X higher than the MOSFET breakdown voltage. If the high voltage capability is to be exploited in radio frequency integrated circuits it is important to develop an accurate empirical model of the device. This paper presents the SPICE model development of the SOI MESFET. A measurement-based approach is used to customize a commercially available, large-signal TOM3 MESFET model. Using the TOM3 model, an SOI MESFET Colpitts oscillator operating at 1.5GHz has been simulated with an output swing of 7V to illustrate the high voltage RF applications of the device. [Copyright &y& Elsevier]

Abstract: Conductance deep-level transient spectroscopy (CDLTS) has been performed for 4H-SiC metal–semiconductor field effect transistor (4H-SiC MESFETs). Additionally to an emission band, two unexpected hole-like traps labelled HL1 and HL2 are observed in the spectra. Different measurements, varying the bias conditions show that these traps originate either from the surface state outside the gate region between gate and drain electrodes (HL1) or from interface states at the channel/buffer-layer or buffer-layer/semi-insulating substrate (HL2). The activation energies of both states are respectively determined as 0.90eV for HL1 and 0.56eV for HL2. [Copyright &y& Elsevier]

Metal semiconductor field effect transistors (MES-FETs) have been fabricated using a silicon-on-insulator (SOI) CMOS process. The MESFETs make use of a TiSi2 Schottky gate and display good depletion mode characteristics with a threshold voltage of -0.5 V. The drain current can also be controlled by a voltage applied to the substrate, which then behaves as a MOS back gate. The transistors have been irradiated with 50 keV X-rays to a total ionizing dose in excess of 1 Mrad(Si). After irradiation the threshold voltage of both the top Schottky gate and the back MOS gate shift to more negative values. The shift in threshold is attributed to radiation induced fixed oxide charge at the interface between the SOI channel and the buried oxide. [ABSTRACT FROM AUTHOR]

Abstract: GaAs MESFETs with novel lowly-doped drain structures have been developed utilizing molecular implants of silicon trifluoride. Short-channel effects in the 1/4μm enhancement- and depletion-mode transistors have been suppressed with drain-induced barrier height lowering of less than 70mV/V and pinch-off voltage shifts of less than 220mV as the gate length was scaled from 1.0 to 1/4μm. The 3-terminal breakdown, the transconductance to output conductance ratio, and the unity current gain, cut-off frequency were simultaneously optimized. The E-mode device possessed breakdown of >10V, G m · R ds >9.5, F t >55GHz, and nominal on-resistance of 2.1Ωmm while the D-mode device had breakdown >10V, G m · R ds >6.0, F t >45GHz, and nominal on-resistance of 1.9Ωmm. These optimized transistors enabled the realization of a variety of low-power digital and high-power mixed signal circuits, using 3-level source-coupled transistor and common-mode logic, such as laser and electro-optic drivers, highly integrated transceivers, multiplexers, demultiplexers, and clock data recover circuits. [Copyright &y& Elsevier]

A comprehensive analysis of a multistage Doherty amplifier, which can be used to achieve higher efficiency at a lower output power level compared to the classical Doherty amplifier, is presented. Generalized design equations that explain the operation of a three-stage Doherty amplifier, which can be easily extended to an N-stage Doherty amplifier, are derived. In addition, the optimum device periphery, which minimizes AM-AM distortion for perfect Doherty amplifier operation, is analyzed. For the first time, a multistage Doherty power amplifier that meets wide-band code-division multiple-access (WCDMA) requirements is demonstrated. The designed power amplifier exhibits a power-added efficiency (PAE) of 42% at 6-dB output power backoff and 27% at 12-dR output power backoff. These PAEs are more than 2× and 7× better, respectively, than that of a single-stage linear power amplifier at the same output power backoff levels. The power amplifier is capable of delivering up to 33 dBm of output power, and has a maximum adjacent channel power leakage ratio of -35 and -47 dBc at 5- and 10-MHz offset, respectively. To the best of the authors' knowledge, these represent the best reported results of a Doherty amplifier for WCDMA application in the 1.95-GHz band to date. [ABSTRACT FROM AUTHOR]

In this paper, a novel approach to the measurement of mobility of GaAs HEMT devices is presented. The new approach employs high-order derivatives as a means of determining the parameters of the proposed new mobility equation. The new approach is compared to established mobility measurement methods, and shown to offer better accuracy. The results presented also consider the behavior of mobility in the linear and saturation bias regions. The mobility value extracted by this new method has permitted improvements to the MESFET/HEMT model when simulating the behavior of the device in the linear region. This is critical in many applications, such as in low current linear-mixing applications. [ABSTRACT FROM AUTHOR]

A finite difference upwind discretization scheme in two dimensions is presented in detail for the transient simulation of the highly coupled non-linear partial differential equations of the full hydrodynamic model, providing thereby a practical engineering tool for improved charge carrier transport simulations at high electric fields and frequencies. The discretization scheme preserves the conservation and transportive properties of the equations. The hydrodynamic model is able to describe inertia effects which play an increasing role in different fields of micro- and optoelectronics, where simplified charge transport models like the drift–diffusion model and the energy balance model are no longer applicable. Results of extensive numerical simulations are shown for a two-dimensional MESFET device. A comparison of the hydrodynamic model to the commonly used energy balance model is given and the accuracy of the results is discussed. Copyright © 2004 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

We present a theoretical study of metal-semiconductor field-effect transistor (MESFET) devices for three different materials: zincblende-phase gallium nitride (ZB-GaN), cubic-phase silicon carbide (3C--SiC) and gallium arsenide (GaAs). The dc breakdown voltage of comparable MESFETs made with the two wide bandgap materials, ZB--GaN and 3C--SiC are compared to that made with the well studied material, GaAs. In this way, the GaAs calculations serve as a control, enabling an accurate comparison of the device behaviors. The simulations are performed with a new, generalized, self-consistent, full-band Monte Carlo simulator. The new simulator includes fully numerical scattering rates and a fully numerical, overlap-based final-state selection process. A 0.1μm gate-length MESFET is used for all of the simulations, and rectangular wells of lightly doped material are used to model interface states. The calculated dc breakdown voltages of the ZB--GaN, 3C-SiC, and GaAs MESFETs are 18, 16, and 5 V respectively. The previously estimated factor-of-four difference between the breakdown voltage of ZB--GaN and GaAs devices is verified. [ABSTRACT FROM AUTHOR]

We have investigated the physical mechanism of off-state breakdown in GaAs MESFETs that exhibited an initial breakdown voltage shift called “walkout” and snapback in I–V characteristics. From experiments using dual-gate MESFETs under various bias stress conditions, we attributed the origin of breakdown walkout to the change in electrical properties of the surface state at the gate edge. This was confirmed by experiments using newly developed open-gate FETs whose surface state was changed from an electron trap to a hole trap in the ungated region within about 0.4 μm from the gate edges. The change in surface-state properties can be explained by assuming electron injection from the gate metal into the oxide layer and the following surface Fermi-level dynamics. To verify our breakdown walkout model, we performed a two-dimensional simulation of gate–drain breakdown in GaAs MESFETs taking into account impact ionization, tunneling, and the proposed surface-state model. Our simulation can successfully describe the experimentally observed breakdown behavior, i.e., walkout and snapback. [Copyright &y& Elsevier]

This paper describes a miniaturized monolithic-microwave integrated-circuit (MMIC) analog phase shifter using two quarter-wave-length transmission lines. A conventional analog phase shifter employs an analog phase-shifter topology using a 3-dB 90° branch-line hybrid requiring four quarter-wave-length transmission lines. Thus, in the first stage of our study, we present a new analog phase-shifter topology using only two quarter-wave-length transmission lines. The phase shifter here has only one-half as many transmission tines as a conventional analog phase shifter using a 3-dB 90° branch-line hybrid, and the circuit can be miniaturized to less than one-fourth as compared to the conventional analog phase shifter. Furthermore, we show that the operating frequency range of the phase shifter is very wide and can obtain large phase variation with small capacitance variation. Next, an experimental Ku-band MMIC analog phase shifter is presented. A phase shift of more than 180° and an insertion loss of 3.6±1.1 dB are obtained at the frequency range from 12 to 14 GHz. The chip size of the experimental MMIC phase shifter is less than 3.0 mm2 [ABSTRACT FROM PUBLISHER]

A phenomenologically based transient SPICE model was developed for GaAs MESFETs. The model accounts for both trapping and detrapping effects; hence, it can simultaneously simulate low-frequency dispersion and gate-lag characteristics. This is different from conventional models, which can simulate either effect, but not both. The present model has been used to describe both surface- and substrate-related trapping phenomena in epitaxial or ion-implanted MESFETs. The model was experimentally verified in terms of pulsed I-V characteristics and pulsed AC response [ABSTRACT FROM PUBLISHER]

A new small-signal equivalent circuit for HEMTs and MESFETs is proposed based on ac measurements. Instead of a pure output conductance gds in conventional equivalent-circuit models, an output admittance Yds=Gds+jB is introduced. The delay time τ in the conventional models can be interpreted physically. Using the model, simulated S-parameters agree well with the measured ones in the frequency range from 45 MHz to 40 GHz for HEMTs. © 2001 John Wiley & Sons, Inc. Microwave Opt Technol Lett 28: 375–378, 2001. [ABSTRACT FROM AUTHOR]

In this paper, a new semiempirical DC thermal model of low- and high-power GaAs MESFETs is proposed. The model takes into account the effect of device negative output conductance and simulates external thermal effects modelling the dependence on temperature of the device threshold voltage and the maximum saturation drain–source current. A number of GaAs MESFETs, very different from a geometrical and technological point of view, have been characterized as a function of temperature and modelled by our model with high accuracy. The CPU extraction time results are moderate in any example. Results have been compared with the Rodriguez–Tellez model, showing improvements of accuracy better than 30 per cent. The model can be successfully used n MMIC CAD applications. Copyright © 2001 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Explores the RF power performance of microwave amplifiers fabricated from wide bandgap semiconductor transistors and demonstrates that microwave power amplifiers fabricated from 4H-SiC and AlGaN/GaN transistors offer superior RF power performance, particularly at elevated temperatures. Theoretical models predict room temperature RF output power on the order of 4-6 W/mm and 10-12 W/mm, with power-added efficiency (PAE) approaching the ideal values for class A and B operation, available from 4H-SiC MESFETs and AlGaN/GaN HFETs, respectively. All calculations were thoroughly calibrated against dc and RF experimental data. The simulations indicate operation at elevated temperature at least up to 5000°C is possible. The RF output power capability of these devices compares very favorably with the 1 W/mm available from GaAs MESFETs. The wide bandgap semiconductor devices will find application in power amplifiers for base station transmitters for wireless telephone systems, HDTV transmitters, power modules for phased-array radars, and other applications. The devices are particularly attractive for applications that require operation at elevated temperature [ABSTRACT FROM PUBLISHER]

In the paper a balanced high power amplifier with class A silicon bipolar transistors for L-band T/R module is described. The amplifier was designed for maximum power and minimum transmitance distortions. The obtained parameters of the amplifier are as follow: output power at 1 dB compression P1 dB > 49 dBm, linear gain |S21| > 10 dB, and transmitance deviations during the RF pulse: phase arg(S21)

In this letter, we investigated the effect of magnetron cathode current ( Ic) during reactive sputtering of In–Ga–Zn–O (a-IGZO) channel layer on properties of metal-semiconductor field-effect transistors with Ru–Si–O Schottky gate electrode. One can observe that as Ic increased from 90 to 150 mA channel mobility ( \mu \mathrm {ch\!}) and subthreshold swing (S) improved from \mu _{\mathrm {ch_{_{}}\!}} =7.5 cm ^{2}/\text{V}\cdot \text{s} and S = 580 V/dec to \mu _{\mathrm {ch}} =8.8 cm ^{2}/\text{V}\cdot \text{s}$ and $S=420$ V/dec, respectively. This enhancement in transistors performance was attributed to the reduction of charge density in the depletion region of Ru–Si–O/In–Ga–Zn–O Schottky contacts, which we assigned to the densification of a-IGZO films fabricated at higher Ic . [ABSTRACT FROM AUTHOR]

In-Ga–Zn–O (IGZO) thin films (TFs) were grown by cost-effective nonvacuum solution-processed mist chemical vapor deposition. High quality AgOx Schottky contacts (SCs) were fabricated on these IGZO TFs with rectification ratios and barrier heights as high as 7.9 \times 10^\mathrm \mathbf 7 and 1 eV, respectively, combined with ideality factors as low as 1.32. These SCs were subsequently used as gate contacts in the production of metal–semiconductor field-effect transistors (MESFETs) with excellent switching and stability characteristics. For example, typical ( W/L 785 \mu \text{m}/5~\mu \text{m} ) MESFETs were capable of providing ON-currents up to 245 \mu \text{A} , combined with a large ON/OFF ratio of 3.8 \times 10^\mathrm \mathbf 7 . A mobility of 3.2 cm ^\mathrm \mathbf 2 /(V.s) and a low subthreshold swing of 356 mV/decade were achieved in the W/L~524\mu \textm/10~\mu \textm transistors. Under positive bias stress, these MESFETs were highly stable, demonstrating the feasibility of using a combination of mist chemical vapor deposition grown IGZO and AgOx SCs to produce stable, low power consumption, and low-cost switching devices. [ABSTRACT FROM AUTHOR]

• Two wells and additional oxides are inserted and engineered in the proposed symmetric structure. • Breakdown voltage and maximum output power experience higher values. • The device current capability is much higher than conventional structure. • Cut off frequency and maximum oscillation frequency beside other RF characteristics are improved. This paper presents an efficient structure for silicon on insulator metal semiconductor FETs. In this structure, by using two symmetrical SiO 2 pieces on both sides of the channel and creating two Si wells in the buried oxide along with an extra dent, it has caused DC characteristics and frequencies to be higher than conventional structure. In the proposed device, the breakdown voltage boosts from 15.5 V in the basic structure to 19.5 V in the novel device which indicates about 25% growth. Also, the maximum output power has increased from 0.69 W/mm in the basic structure to 2.4 W/mm in the proposed one which shows an improvement more than 3 times. Also, attributable to lessening of the gate-drain and the gate-source capacitances, the frequency characteristics such as the cut-off and maximum oscillation frequencies have been improved. Therefore, the investigations demonstrate that suggested structure has proper high power and high frequency characteristics. [ABSTRACT FROM AUTHOR]

This paper proposes a generalized radial basis function (GRBF) network to accurately describe drain to source current nonlinearity for intermodulation distortion (IMD) prediction of MESFETs and HEMTs applications in their saturated region. Trying to analytically reproduce the nonlinearities second and third order Taylor-series coefficients, responsible for IMD performance in these devices, may result in a quite difficult task. Neural networks were introduced as a robust alternative for microwave modeling, mostly employing the black-box model type approach of the multilayer perceptron network. The GRBF network we consider is a generalization of the RBF network, which takes advantage of problem dependent information. Allowing different variances for each dimension of input space, the GRBF network makes use of soft nonlinear dependence of the drain to source current derivatives with drain to source voltage for improving accuracy at reduced cost. The network structure and its learning algorithm are presented. Results of its performance are compared to other structures with similar amounts of parameters. Carrier to intermodulation (C/I) predictions validate this approach for precise IMD control versus bias and load in class A amplifiers applications. ©1999 John Wiley & Sons, Inc. Int J RF and Microwave CAE 9: 261–276, 1999. [ABSTRACT FROM AUTHOR]

Ion-implanted Si-doped GaAs MESFETs with 1pm and 5μm gate lengths have been subjected to DC life testing at temperatures of 220°C and 250°C for 4000 and 2250 h, respectively. Two failure mechanisms have been identified: 1. Diffusion of platinum from the gate contact into the n-GaAs channel. 2. An increase of deep-level trapping, specifically of EL2 (Ea=08 eV), in the channel region. [ABSTRACT FROM AUTHOR]

This paper reports a study on the fabrication technology of high performance functional devices, where high temperature superconductor and compound semiconductor devices are monolithically integrated on the same substrate. We investigated optimal conditions for epitaxial liftoff process and succeeded in fabricating HTS device and GaAs MESFET on SrTiO/sub 3/ substrate without degrading characteristics of superconductor and semiconductor devices. We also carried out basic integrated circuit fabrication processes such as patterning and etching for quasi-monolithic structure. The results confirmed that fabricating high performance functional devices is feasible. [ABSTRACT FROM PUBLISHER]

To meet the specifications of future radar and communication systems we developed a low phase noise microwave oscillator. This feedback oscillator consists of a commercial MESFET-amplifier at room temperature and a LaAlO/sub 3/ dielectric resonator with high temperature superconducting (HTS) shielding at 63 K. The resonator operating at a resonance frequency of 5.6 GHz showed unloaded quality factors in the 10/sup 5/ to 10/sup 6/ range. By means of a strong resonator coupling (|S/sub 21/|=6 dB) and an amplifier gain of 20 dB we obtained an output power of +15 dBm. The phase noise L(f/sub m/) of the oscillator was below the detection limit for offset frequencies beyond 10 kHz. For offset frequencies below 5 kHz measurements revealed perfect L(f/sub m/)/spl prop/f/sub m//sup .3/-behaviour according to the Leeson model. The phase noise was -110 dBc/Hz at 1 kHz offset and -130 dBc/Hz at 10 kHz. This phase noise performance is superior to state of the art SAW- or quartz oscillators for f/sub m/>10 kHz. To further reduce the phase noise performance close to the carrier we investigated the implementation of a phase locked loop (PLL). The long term temperature stability of the oscillator frequency can be enhanced by introducing a central cylinder made from rutile (TiO/sub 2/). We present numerical and experimental results on this compensation. [ABSTRACT FROM PUBLISHER]

A novel distributed amplifier topology is proposed to increase the power performance and the gain. In comparison with the conventional configuration, a considerable advantage is obtained by introducing Lange couplers at the input and output ports of the amplifier. Design examples are discussed to confirm the validity and the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

Silicon-on-insulator (SOI) metal-semiconductor field-effect transistors (MESFETs) with complementary n- and p-type channels have been fabricated using a commercial 45-nm CMOS process. The current drive and transconductance of the n-MESFET is approximately three times larger than that of the p-MESFET due to the higher electron mobility. Both devices operate in depletion mode with the threshold voltage of the n-MESFET being approximately −0.4 V, while that of the p-MESFET is $\sim 0.3$ V. The MESFETs have multiple gigahertz cutoff frequencies and can withstand drain bias in excess of 4 V making them attractive for analog- and mixed-signal applications that require higher operating voltages than the baseline CMOS. The p-MESFET has higher leakage current due to the lower Schottky barrier height to the p-type channel. [ABSTRACT FROM PUBLISHER]

A diamond metal–semiconductor field-effect transistor (MESFET) with a Pt Schottky gate was fabricated. The MESFET exhibited clear saturation and pinchoff characteristics. The drain current of the MESFET operated at 300 °C was 20 times higher than that at room temperature due to the activation of acceptors. The breakdown voltage was highly dependent on the gate–drain length and reached 1.5 kV at a gate–drain length of 30 \(\mu \text{m}\) , which is the highest reported for a diamond FET. [ABSTRACT FROM AUTHOR]

Highlights: [•] SOI MESFETs have been fabricated using a commercial CMOS foundry at the 45nm node. [•] Breakdown voltages exceeding 25V have been measured. [•] A simple model based on avalanche multiplication is developed to explain the measured breakdown voltages. [ABSTRACT FROM AUTHOR]

Transparent metal-semiconductor field-effect transistors (MESFETs) with a ZnCoO channel have been fabricated by pulsed laser deposition on c-plane sapphire substrates at a temperature of 550^\circC. The paramagnetic properties have been confirmed by magnetotransport measurements on undepleted ZnCoO films without Schottky gate contacts. The Au/AgxO Schottky gate contacts were processed by optical lithography and metallization. Below 50 K, the MESFET characteristics are persistently changed from a low resistance state (LRS) to high resistance state by an external magnetic field. The MESFET can be switched back into the LRS only by heating it up to room temperature. [ABSTRACT FROM AUTHOR]

A silicon metal-semiconductor-field-effect-transistor (MESFET) power amplifier operating at 900 MHz fabricated on a 45 nm silicon-on-insulator CMOS process with no changes to the process flow is presented. The soft breakdown of the MESFET is 20 times that of the MOSFET and allowed a single transistor amplifier based on Class A bias conditions to operate at up to 32 dBm output power with an 8 V drain bias. The amplifier had a peak power added efficiency of 37.6%, gain of 11.1 dB, OIP3 of 39.3 dBm and 1 dB compression point at an output power of 31.6 dBm. The device required only 0.125 mm^2 of active area. Additionally, the depletion mode operation of the MESFET enables a simple input bias approach using an inductor to ground at the gate of the device. [ABSTRACT FROM PUBLISHER]