401. Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors
- Author
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Daniele Bortolotti, Andrea Bartolini, Christian Weis, Davide Rossi, Luca Beninio, Bortolotti, Daniele, Bartolini, Andrea, Weis, Christian, Rossi, Davide, and Benini, Luca
- Subjects
Energy utilization ,010302 applied physics ,Design ,E-health monitoring system ,020208 electrical & electronic engineering ,Engineering controlled terms: Bioelectric phenomena ,Static random access storage ,Environment monitoring ,02 engineering and technology ,Emerging application ,Technology scaling ,Wireless body sensor networks Engineering main heading: Memory architecture ,7. Clean energy ,01 natural sciences ,020202 computer hardware & architecture ,11. Sustainability ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Body sensor network ,Voltage scaling Biomedical signal ,Normal operation ,Multicore architecture - Abstract
Technology scaling enables today the design of sensor-based ultra-low cost chips well suited for emerging applications such as wireless body sensor networks, urban life and environment monitoring. Energy consumption is the key limiting factor of this up-coming revolution and memories are often the energy bottleneck mainly due to leakage power. This paper proposes an ultra-low power multi-core architecture targeting eHealth monitoring systems, where applications involve collection of sequences of slow biomedical signals and highly parallel computations at very low voltage. We propose a hybrid memory architecture that combines 6T-SRAM and 8T-SRAM operating in the same voltage domain and capable of dispatching at high voltage a normal operation and at low voltage a fully reliable small memory partition (8T) while the rest of the memory (6T) is state-retentive. Our architecture offers significant energy savings with a low area overhead in typical eHealth Compressed Sensing-based applications
- Published
- 2014
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