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It is known that products made of polymer materials or especially polymer materials with glass fiber and carbon fiber are used in many different areas such as automotive, aerospace, and defense. At this point, studies in the literature have gained momentum due to the combination of fiber-reinforced polymer materials emerging as a result of technological developments and industrial demands, and the fused deposition modeling (FDM) method providing the production of parts in desired sizes and complexity. Residual stresses and distortions occurring in polymer-based composite parts produced with FDM are among the problems that should be minimized. In this study, the influences of fiber ratio (%10, %15, and %20), infill rate (%20, %50, and %80), and infill pattern (line, honeycomb, and triangle) on the residual stresses and warpages generating in impact test specimens produced from glass fiber reinforced ABS filaments by fused deposition modeling were tried to be determined with the Digimat 2021 program. As a result of the findings, it was determined that the distortion values decreased and the thermal residual stress values went up with the increase in fiber ratio and infill rate. In addition, it can be reported that the distortions that bring out as a result of the separation of the produced parts from the production platform are caused by the high deformations condensing at the lower corner points of the parts. [ABSTRACT FROM AUTHOR]

In order to solve the problem of small chip size, high fan-out ratio and other fan-out packaging, JCET ADVANCED PACKAGING CO. LTD. introduced a new kind of encapsulation material and a new wafer reconstruction method to complete the fan-out packaging. The new wafer reconstruction method is to divide the wafer into a single chip first, the single chip is facedown to the metal carrier, then the new encapsulation material is attached to the metal carrier with a single chip, and finally the reconstructed wafer is completed by lamination, leveling, and silicon support processes. However, it also faces warpage problems after curing. Excessive warpage poses a significant challenge to subsequent redistribution layer fabrication, mid-testing, and other automatic processes. In this article, finite element methods are used to study the effects of chip thickness, fan-out area, the encapsulation material properties, and the warpage of support silicon wafer after curing. The results indicate that wafer warpage will gradually increase with the thickness increasing of the encapsulated material, whereas the encapsulation material with low modulus and small Coefficient of Thermal Expansion (CTE) can improve warpage performance. High modulus, thicker support silicon has a significant effect on reducing warpage, and larger CTE support silicon can also effectively reduce wafer warpage because the larger CTE support silicon reduces the degree of mismatch with the encapsulation CTE. Thinner chips and higher fan-out areas tend to increase the warpage of the reconstituted wafer. The study of warpage of package structure and material properties can provide theoretical basis for predicting and improving warpage during the design and evaluation phase of the product. [ABSTRACT FROM AUTHOR]

The shape memory effect, as the most important ability of shape memory polymers, is a working property and provides the design ability to shape memory polymer features. Shrinkage and warpage are important parameters to control the dimensional accuracy of permanent and temporary shapes of an injection moulded shape memory polyurethane (SMPU) part. In this study, the effects of injection moulding parameters on the shrinkage and warpage of the permanent shape of moulded SMPU parts were experimentally investigated. The parameters of injection pressure, melt temperature, mould temperature, packing pressure, packing time, and cooling time, were chosen as the injection moulding control factors. Taguchi's L27 orthogonal array design table was used with six injection moulding parameters and their three levels. The results showed that the part has different shrinkage ratios in three main directions, namely, the flow direction, perpendicular to the flow direction, and the direction through the thickness. The results of the analysis of variance showed that the cooling time is the most influential parameter on both the shrinkage (except in thickness) and warpage. The shrinkage in the flow direction as well as in perpendicular to the flow direction decreased with increasing the cooling time. Warpage also decreased with increasing the cooling time. Injection pressure and melt temperature were found to be effective on shrinkage in thickness. Effects of mould temperature, packing pressure, and packing time were found to be limited. A statistically significant relationship has been noticed among shrinkage, warpage, and residual stresses during the study. [ABSTRACT FROM AUTHOR]

Wafer warpage is a baseline issue faced by semiconductor manufacturers and is, in fact, particularly conspicuous among those which are involved in the fabrication of power metal oxide semiconductor field effect transistors (MOSFETs). This is because vertical MOSFETs experience larger warpage effects compared with their conventional lateral counterparts. Wafers with warpage exceeding its critical value fail to be chucked by vacuum adsorption during the automatic handling process; the devices fabricated in the wafer face reliability issues as well. This paper presents an analysis on various mechanisms employed to reduce warpage in power MOSFET wafers. The warpage behavior was examined by varying the backside metallization (BSM) thickness, the sputtering power for film deposition and the wafer's temperature (i.e., a cryogenic condition was introduced into the process). The results suggest that both the BSM thickness and wafer's temperature do not manifest a clear correlation with the wafer warpage when the front-end fabrication process is completed. The wafer bow level was, however, found to be in direct proportion with the magnitude of the sputtering power. When the sputtering power is reduced, less residual stress is induced to deform the wafer structure. Hence, the sputtering power could be adjusted to ensure that the warpage effect stays below its critical value. [ABSTRACT FROM AUTHOR]

In the present study, a systematic methodology has been presented to determine optimal injection molding conditions for minimizing warpage and shrinkage in a thin wall relay part using modified particle swarm algorithm (MPSO). Polybutylene terephthalate (PBT) and polyethylene terephthalate (PET) have been injected in thin wall relay component under different processing parameters: melt temperature, packing pressure and packing time. Further, Taguchi's L9 (32) orthogonal array has been used for conducting simulation analysis to consider the interaction effects of the above parameters. A predictive mathematical model for shrinkage and warpage has been developed in terms of the above process parameters using regression model. ANOVA analysis has been performed to establish statistical significance among the injection molding parameters and the developed model. The developed model has been further optimized using a newly developed modified particle swarm optimization (MPSO) algorithm and the process parameters values have been obtained for minimized shrinkage and warpage. Furthermore, the predicted values of the shrinkage and warpage using MPSO algorithm have been reduced by approximately 30% as compared to the initial simulation values making more adequate parts. [ABSTRACT FROM AUTHOR]

The fan-out interposer (FOI) technology with fine pitch is demonstrated and presented for heterogeneous integration as a cost-effective and enabling technology. The co-design modeling methodology is established for the FOI technology, including wafer process-induced warpage, package assembly warpage, and board-level solder joint reliability to optimize the structure design, wafer process, assembly process, and material selection. Through the wafer warpage modeling, desirable glass carrier, photodielectric, and molding compound materials and interposer structure are suggested to reduce the wafer warpage. Effect of stiffener on assembly induced package warpage is simulated and studied. Board-level solder joint reliability is investigated and optimized based on the simulation results. The optimized materials and the structure design are determined based on the co-design modeling and simulation results to achieve the successful FOI wafer fabrication, assembly process, and board-level reliability for extreme large package with FOI. [ABSTRACT FROM AUTHOR]

This paper presents a systematic methodology to determine optimal injection molding conditions for minimum warpage and shrinkage in a thin wall relay part using modified particle swarm optimization algorithm (MPSO). Polybutylene terephthalate (PBT) and polyethylene terephthalate (PET) were injected in a thin wall relay component for different processing parameters: melt temperature, packing pressure and packing time. Further, Taguchi's L9 (3 2) orthogonal array is used for conducting simulation analysis to consider the interaction effects of the above parameters. A predictive mathematical model for shrinkage and warpage is developed in terms of the above process parameters using regression analysis. ANOVA analysis is performed to establish statistical significance within the injection molding parameters. The analytical model is further optimized using a newly developed MPSO algorithm and the process parameters values are predicted for minimizing shrinkage and warpage. The predicted values of shrinkage and warpage using MPSO algorithm are improved by approximately 30% as compared to the initial simulation values and comparable to previous literature results. [ABSTRACT FROM AUTHOR]

Recently, advanced experimental mechanics have been developed using optical techniques for measuring 3D deformations of objects in industries. Especially, Moiré systems and 3D DIC (digital image correlation) were competing in characterizing warpage behaviors of electronics package under thermal loading with consideration of manufacturing process, which is accompanied by elevated temperatures. Both techniques conventionally require various surface treatments either physically or chemically, which involves contaminations on measuring objects. Additionally, excessive surface treatment results in reduction of measurement accuracy. Thus, in this study, truly in situ and non-contact 3D DIC method is developed using virtually generated speckle pattern. A commercial DLP (digital light processing) projector together with devised collimate lens system is used to project proper image of speckles on surface of specimen. The collimate lens system fully controls size of speckle image on such small area of electronics package. The feasibility of 3D DIC with virtual pattern is validated, and warpage characterization of PBGA (plastic ball grid array) package (15 mm × 15 mm) is successfully demonstrated. [ABSTRACT FROM AUTHOR]

The objective of this paper is to achieve the minimization of warpage for an injection molded part. The techniques that were implemented to minimize the warpage are the design of experiment (DOE), response surface methodology (RSM), firefly algorithm (FA), and annealing treatment. The packing time, cooling time, and melt temperature were shown to be significant parameters and FA was employed to seek these suitable values by experimental tests based on simulation software Moldex3D and injection machine. Analysis of variance (ANOVA) was used to validate experiments. Annealing treatment process was then applied to reduce more warpage phenomenon; the results showed that warpage phenomenon decreased dramatically compared with popular optimized parameter methodology. Moreover, the residual stress which was obtained by using photoelasticity showed that it has a direct relationship with warpage reduction. Therefore, the best solution of warpage mitigation can be solved by popular optimum process parameters and also annealing treatment. [ABSTRACT FROM AUTHOR]

In this paper, the warpages of a chip-first and die face-up fan-out wafer-level packaging (FOWLP) with a very large silicon chip (10 mm $\times \,\, 10$ mm $\times \,\, 0.15$ mm) and three redistributed layers are measured and characterized. Emphasis is placed on the measurement and 3-D finite-element simulation of the warpages during the FOWLP fabrication processes, especially for: 1) right after postmold cure; 2) right after backgrinding of the epoxy molding compound to expose the Cu-contact pads; and 3) the individual package (right after the solder ball mounting and dicing) versus surface mount technology reflow temperatures. The simulation results are compared to the measurement results. Some recommendations on controlling the warpages are provided. [ABSTRACT FROM AUTHOR]

Warpage is one of the most frequent issues facing the molding industry, especially for different wall thickness products. The aim of this study is to generate an optimization method in order to reduce warpage of a protector cover as much as possible. Topology optimization and deflection analysis were carried out to obtain a stiff design that resists warpage. The topology optimization results suggest a weak area/void in the product design. Then, a careful consideration in patterning the rib location and modification wall thickness based on topology data was introduced until it obtained an optimum wall deflection. Finally, the warpage conditions were found to optimize approximately 79.52% (left side), 76.12% (middle area), and 69.06% (right side) with respect to the reference model. [ABSTRACT FROM AUTHOR]

In this study, the amount of warpage occurring in a polymer-metal hybrid during its manufacturing process and the mechanical properties of the warped hybrid under bending load were investigated both experimentally and numerically. The cohesive zone model was employed to define contact between the polymer and the metal layer which the cohesive parameters were obtained from experimental tests. The effect of different injection process parameters including packing time, injection time, and melt temperature on the amount of warpage was also investigated. The results showed that the amount of warpage decreases by increasing injection time and increases by boosting melt temperature. Moreover, the results indicated that the amount of warpage decreases and then remains approximately constant as packing time is increased. In addition, packing time and melt temperature have the greatest impact on the amount of warpage. The results showed that there is a good agreement between simulated and experimental warpage and also between bending modulus obtained from experimental tests and simulation. [ABSTRACT FROM AUTHOR]

A crucial factor for ensuring the reliability of chip packages is the measurement and control of warpage. The warpage of chip packages, printed wiring boards (PWBs), and PWB assemblies (PWBAs) are typically measured by moiré techniques (i.e., shadow moiré, laser fringe projection, and digital fringe projection), which have noncontact, full-field, and high-resolution capabilities. The application of moiré techniques typically involves spraying a mist of reflective paint on the surface of a sample to ensure the uniformity of surface reflectance and to obtain better fringe image contrast and better sinusoidal waveforms in the fringe patterns for the measurement process. However, since painted samples may no longer be re-used, the process of spray painting is not suited for inline inspection; a new technique for measuring warpage without painting is required. In this research, a dynamic digital fringe projection (DDFP) technique for measuring the warpage of unpainted plastic ball grid array (PBGA) packages and boards was developed. The DDFP technique dynamically determines proper fringe intensity distributions for PBGA packages and PWBs and uses them to produce a better fringe image contrast and better sinusoidal waveforms without painting. Experimental results showed that the DDFP technique successfully measures the warpage of PBGA packages and PWBs in unpainted PWBAs accurately. [ABSTRACT FROM AUTHOR]

Warpage for 320 mm × 320 mm panel level fan-out packaging based on die-first process was investigated by both simulation and experimental approaches. In the present paper, a simple and efficient FEA (Finite Element Analysis) method based on shell element was introduced. Finite element models were built by using the software of Ansys products to predict and analysis the warpage for feasibility of large panel fan-out packaging technology in aspect of material, package geometries, package size, process conditions and metal density. In order to verify the accuracy and the precision of the simulation method, test vehicle with dies was fabricated by using low cost ‘die first (face down)’ fan-out technology. Warpage of the test vehicle was measured by using Shadow Moiré method. The simulated warpage result and the experimental one exhibit good consistency. [ABSTRACT FROM AUTHOR]

Through-silicon via (TSV)-free interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. In this paper, structure–material–assembly–reliability–thermal (SMART) codesign modeling methodology is established for a package using TFI technology by considering wafer process, package assembly and package/board-level temperature cycling reliability, and thermal performance to optimize structure design, assembly process, and material selection. Experimental results are used to validate wafer warpage modeling results first. Through wafer-level modeling, suitable carrier and molding compound materials are recommended to control wafer warpage less than 2 mm for 12-in molded wafer. Effects of coefficient of thermal expansion of package substrate and stiffener on package warpage induced by assembly reflow process are simulated and analyzed. The recommended materials and geometry design based on thermal cycling reliability simulation are aligned with that from wafer and package warpage simulation results. The final test vehicle design and material selection are determined based on SMART codesign modeling results for achieving successful TFI wafer process and package assembly and long-term board-level reliability. [ABSTRACT FROM AUTHOR]

In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, reconstituted carrier material and thickness, and die-attach film, on the warpage after postmold cure and backgrinding of the EMC. The simulation results are compared to the experimental measurements. Also, the thermal performance (junction-to-ambient thermal resistance) of FOWLP with various chip thicknesses is characterized. Finally, some FOWLP important parameters affecting the warpage and thermal performances are recommended. [ABSTRACT FROM PUBLISHER]

Flip chip thermo-compression bonding (TCB) involves the use of heat and pressure to simultaneously form interconnections for microelectronic packaging. In-situ measurements of thermo-mechanical stresses that arise during this bonding process could provide unique insight to help better understand the TCB process. A 4 mm × 3 mm × 500 μm complementary metal-oxide-semiconductor (CMOS) sensor chip with an 8 × 8 array of Au-bumped sensor pads was developed for this purpose. It was designed to record XYZ force and temperature signals from bump locations, during a simulated flip chip process similar to TCB. In-situ measurements during simulated TCB events proved useful for tilt detection, thermal gradient characterization, and thermal expansion measurements. Further interpretation of the signals proved tilt and other thermo-mechanical effects were induced by thermal expansion mismatches. The most thermo-mechanically stressful stage of bonding was found to occur during thermal transients, specifically during bond head ramping. Further analysis concluded the actual time necessary to heat the bumps was less than 0.5 s. Finally, the lateral thermal gradient across the sensor chip was calculated to be smallest in the central bump locations, and largest in the bump array corners due to warpage, tilt, and heat sink effects of the digital logic region. [ABSTRACT FROM AUTHOR]

The setting of suitable parameter's level and values were very crucial in determining the quality characteristic of the injection moulding's product, especially made from advanced polymer nanocomposites. Therefore, this research was proposed to optimise the injection moulding parameters towards the quality characteristics of samples made from polypropylene-nanoclay-Gigantochloa Scortechinii fibers. The quality characteristics that need to be controlled were shrinkage and warpage, and the selected parameters were packing pressure, barrel temperature, screw speed and filling time. The Gigantochloa Scortechinii fibers need to be preheated at 120 0 C first, and then mixed with polypropylene, polypropylene grafted maleic anhydride and nanoclay through the compounding process by using Brabender Plastograph. The injection moulding process was performed based on the orthogonal array from Taguchi Optimisation Method. According to the results, the value of warpage was reduced when the fiber content was increased from 1 wt. % to 3 wt. %. The warpage value changed from 0.025 mm to 0.009 mm. The optimum parameter for warpage were 175 °C barrel temperature, 40% packing pressure, 35% screw speed and 2 seconds filling time for both 1 wt. % and 3% of GS fiber. However, in terms of shrinkage, the increment of fiber content doesn’t have much impact towards the response. The value of shrinkage was reduced but not significantly from 0.0136 mm to 0.0134 mm when the percentage of fiber was added. The optimum parameter for 1 wt. % fiber to control shrinkage are 170 °C melt temperature, 35% packing pressure, 30% screw speed and 2 seconds of filling time. The findings of this research will be valuable for quality control and references for products made from polypropylene-nanoclay-Gigantochloa Scortechinii fibers. [ABSTRACT FROM AUTHOR]

Injection molding process causes differences between designed shape and real parts, all of them associated to shrinkage and warpage phenomena. Temperature, pressure distribution, and other injection parameters during molding process originate local shrinkage and the internal stresses depending on the relative stiffness of each part area. The aim of this work is to review and report the influence of injection molding process parameters on the postmolded strength, shrinkage, and warpage of injection molded parts. It is also to investigate the influence of injection molding process parameters on the postmolding shrinkage and warping of parts made of polypropylenes. [ABSTRACT FROM PUBLISHER]

The purpose of this paper is to analyze and predict the thermal deformation of the through silicon via (TSV) interposer package during the manufacturing process and to perform a parametric study to minimize the warpage and thermal stress. Samples were selected during different stages of the assembly to observe the thermal behavior change. The Digital Image Correlation (DIC) technique was employed to measure the real-time deformation of the samples under thermal loading. To make a finite element analysis (FEA) model, material properties were characterized by DIC and Dynamic Mechanical Analysis (DMA). Based on the material properties and deformation data determined by experiments, a validated FEA model was established. To reduce the modeling complexity and the computing time in the simulation, the C4/underfill layer, micro bump/underfill layer, and TSV interposer were assumed to be isotropic. The most effective material properties for the isotropic layers were calculated by the composite theory. Also, the simulation followed the sequential manufacturing processes to investigate the thermal deformation change of each step and to obtain a more accurate prediction result. The thermal behavior from simulation showed a good agreement with the experimental result and this verified simulation model was implemented for the parametric study. A series of simulations were carried out to minimize the package warpage. To avoid any delamination failures, the stresses at the interface between the interposer and underfill were also evaluated. The effect of the interposer underfill material property, substrate material property, substrate thickness, and TSV density (Cu volume fraction) in the interposer were studied. It has been shown that low modulus, low coefficient of thermal expansion (CTE), and high glass transition temperature ( T g ) underfill, as well as a low modulus and low CTE substrate can mitigate the package warpage and stress development at the interface between interposer and underfill. Also, a larger Cu volume TSV interposer and thick substrate can lessen the warpage of the package and stress at the interface. [ABSTRACT FROM AUTHOR]

ABSTRACT This paper presents a hybrid multiobjective optimization system for minimizing the warpage and cycle time of the plastic injection molding process. During optimization, an innovative adaptive Kriging surrogate modeling strategy is applied to substitute the computationally intensive numerical simulation of the injection molding process. The system consists of two main stages. In the first stage, the Taguchi optimization method, the analysis of variance, and the signal-to-noise ratio are employed to find the significant process parameters. The most influential factors' domains will be divided into two subregions equally in the next step. The Kriging surrogate model is developed to obtain the mathematical relationship between the warpage and process parameters based on the fractional factorial design. A parallel efficient global optimization, named subregional efficient global optimization (SEGO), is proposed. SEGO algorithm is continued till the convergence accuracy is satisfied, and the sufficiently accurate Kriging surrogate model is established. In the second stage, the nondominated sorting-based genetic algorithm II is used to search for the pareto-optimal solutions for two objectives. Numerical result shows that the pareto-frontier is well identified with a small number of simulation runs. The proposed approach can help engineers obtain optimal process conditions and achieve competitive advantages of product quality and efficiency. [ABSTRACT FROM AUTHOR]

In flip-chip packages, the coefficient of thermal expansion (CTE) mismatch between the chip and the substrate is the root cause for reliability issues such as excessive warpage, low- $k$ dielectric layer cracking, solder mask cracking, and bump cracking. The first and foremost thing in designing a flip-chip package is to meet the warpage specification. This paper proposes a capped-die flip-chip package to control the warpage as well as to reduce the stress in solder bumps. In the capped-die flip-chip package, a metal cap tightly covers and bonds with the die through an adhesive material, leading to a capped die with a higher effective CTE. By adjusting the thickness of the metal cap, the effective CTE of the capped die may match with that of the substrate, theoretically achieving zero warpage or warpage free. Guided by finite-element analysis, a $45\times 45$ -mm2 size of capped-die flip-chip package was manufactured, and a copper die cap with 0.4 mm thickness is selected to verify this concept. Shadow Moiré test data showed that in the temperature range from 25 °C to 260 °C, the warpage curve of the capped-die package is almost flat and close to zero, confirming the capped-die concept. Furthermore, finite-element modeling was used to investigate the stress in bump, as well as the thermal performance of the capped-die flip-chip packages. It is found that thermal performance of the capped-die package can be good enough for high-power applications. The bump stress of the capped-die package is about 50% lower compared to the lidded package. The applications of the capped-die package design in coreless substrate packages are also discussed in this paper. [ABSTRACT FROM PUBLISHER]

Composite thick films consisting of multi-layered polymers and metals are widely used in integrated circuits(IC) and its packaging, and it arises intricate stress and warpage problems due to complex inner stress distribution and evolution. The wafer warpage origination and evolution of multi-layered polyimide (PI)/Cu composite film is measured in-situ by a Multi-beam Laser Optical Sensor (MOS) system. It's found that PI has an intricate influence on wafer warpage evolution and Cu plastic deformation due to viscoelasticity and glass-transition, and the influence differs in different structures and at different temperatures. Nonlinearity of the curvature–temperature curve of the composite occurs at much lower temperature than in single PI or Cu film, showing mutual effect of PI and Cu. Unlike bare or capping PI film that totally stress relaxed at high temperature, bottom PI coated by Cu film sustains a medium compressive stress, indicating that Cu coating film has restrained stress relaxation of PI. The warpage evolution during heating is different from that during cooling, perhaps due to different deformation mechanism. [ABSTRACT FROM AUTHOR]

The challenge for three-dimensional integrated circuit assembly is how to manage warpage and thin wafer handling to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have microbumped die with pitches ranging from 120 μm down to 60 μm. The high density of pads and the large die size make it extremely challenging to ensure that all of the microbump interconnects are attached to a thin Si interposer (ITP). In addition, the low standoff between the die and ITP makes it difficult to underfill. A likely approach is to first attach the die to the ITP and then the die/ITP subassembly to the substrate. In this scenario, the die/ITP subassembly is comparable to a monolithic Si die that can be flip chip attached to the substrate. In this article, we discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do two-and-half-dimensional assembly in an outsourced assembly and test facility. [ABSTRACT FROM AUTHOR]

A numerical procedure for constructing the multiaxial viscoelastic model for polymeric packaging material over a wide range of temperature is presented. By using the proposed best-fitting procedure, experimentally measured frequency-domain Young's and shear storage moduli are used to calculate the time-domain bulk and shear relaxation moduli which describe the three-dimensional constitutive behavior of a viscoelastic solid. The numerical procedure incorporates restrictions that ensure that the derived time-domain material function is physics compatible. The proposed procedure was applied to construct the viscoelastic constitutive models of epoxy molding compounds (EMCs), and compared to results obtained by using approximate-formula based direct conversion procedure. It was shown that, without using the proposed procedure, the directly calculated time-dependent Poisson's ratio oscillates significantly in the rubbery regime and is physically inadmissible. To validate the constitutive model constructed by using the proposed procedure, a numerical finite element model that incorporates the viscoelastic constitutive model of the EMC was applied to simulate warpage of an overmolded package under the solder reflow process and compared to experimental shadow Moiré measurements. [ABSTRACT FROM AUTHOR]

An automotive triangle trim was chosen as a research model, and the influence of processing parameters was determined with the Taguchi experimental method. An L (3) orthogonal array was constructed to investigate the significance of each factor (mold temperature, melt temperature, injection time, V/P switchover, packing pressure, and packing time). The computer-aided engineering software Moldflow was employed to determine the extent of warpage. The influence of processing parameters was analyzed by obtaining the signal- to-noise ratio and by conducting a range analysis. Furthermore, the processing parameters for minimizing warpage were optimized. Subsequently, the optimization packing condition for warpage minimization based on the filling conditions. [ABSTRACT FROM AUTHOR]

Package-on-package (PoP) assemblies may experience warpage during package fabrication and later during surface mount assembly. Excessive warpage may result in loss of coplanarity, open connections, misshaped joints, and reduction in package board-level reliability under environmental stresses of thermal cycling, shock, and vibration. Previous researchers have shown that warpage may be influenced by a number of design and process factors including underfill properties, mold properties, package geometry, package architecture, board configuration, underfill and mold dispense and cure parameters, and package location in the molding panel. A comprehensive inverse model incorporating a full set of design and process parameters and their effect on PoP and PoP assembly warpage is presently beyond the state of the art. In this paper, data have been gathered on multiple PoP assemblies under a variety of assembly parameters. The packages have been speckle coated. The warpage of the PoP assemblies have been measured using a glass-top reflow oven using multiple cameras. Warpage measurements have been taken at various temperatures of the reflow profile between room temperature and the peak reflow temperature. Finite-element models have been created, and the PoP warpage predictions have been correlated with the experimental data. The experimental data set has been augmented with the simulation data to evaluate configurations and parameter variations, which were not available in the experimental data set. Statistical models have been developed to capture the effect of single and multiple parameter variations using principal component regression and ridge regression. The best subset variables obtained from stepwise methods have been used for model development. The developed models have been validated with the experimental data using a single factor design of the experimental study and are found to accurately capture material and geometry effects on part warpage. The results show that the proposed approach has the potential of predicting both single and coupled factor effects on warpage. [ABSTRACT FROM PUBLISHER]

This article presents a sandwich-structured SiC power module that can be operated at 225°C. The proposed power module has two ceramic substrates that are made of different materials (Si3N4 and Al2O3). The SiC devices are sandwiched between these ceramic substrates. The module also has a baseplate soldered onto the ceramic substrate. Conventional power modules use baseplate materials with a large coefficient of thermal expansion (CTE), for example, Cu (17-18 ppm/°C and Al (23-24 ppm/°C). In the fabrication process, the soldering temperature reaches 450°C because Au-Ge eutectic solder is used. A problem was found in the fabrication process of the module because of the high soldering temperature and CTE mismatches of the components. Furthermore, for high-temperature operation, a thermal cycle of 240°C to 250°C will be needed to ensure reliability and it is important to decrease the warpage of the module during the thermal cycle. By using stainless steel (CTE: 10 ppm/°C) for the baseplate, the warpage measured at room temperature was reduced to one-third that of a module using a Cu baseplate. Further, the warpage displacement from 50°C to 250°C was also reduced. [ABSTRACT FROM AUTHOR]

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only -30 mm ~ -40 mm at room temperature (25°C) for 25 mm x 31 mm in size and +20 mm ~ +25 mm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study. [ABSTRACT FROM AUTHOR]

Headlight lampshades with an uneven part thickness and large-area complicated geometry often exhibit uneven shrinkage and considerable deformation when fabricated using injection molding. Conventional strategies for controlling shrinkage and warpage involve optimizing the gate number and location, cooling system, and mold conditions and performing annealing in a secondary process; however, conventional strategies are limited in improving the quality of injection molding. This study involved employing conventional approaches and external gas-assisted injection molding (eGAIM) to control part shrinkage and warpage effectively. The research consisted of three stages: (1) using computer simulations to optimize the mold design and molding conditions and, thus, reduce the shrinkage and warpage of headlight lampshades; (2) verifying the performance experimentally using a miniaturized geometry of the one use in (1); (3) applying eGAIM to show the potential of further improving part warpage. Simulation and experimental results indicated that optimizing the gate location facilitates improving the flow balance and reducing the filling pressure, leading to a reduction in part deformation. An optimal layout of cooling channels combined with two-stage holding conditions contributed to a superior cooling effect and low volumetric shrinkage. Parts fabricated using eGAIM exhibited less volumetric shrinkage than did parts fabricated using conventional injection molding. Moreover, annealing treatment can further reduce the deformation of molded parts. This case study investigated headlight lampshade deformation and was systematically conducted; the experimental results showed the feasibility of using eGAIM to minimize part warpage. [ABSTRACT FROM AUTHOR]

This paper presents a warpage analysis method that predicts the warpage behavior of electroplated Cu films on glass fiber-reinforced polymer (GFRP) packaging substrates. The analysis method is performed using the following sequence: fabricate specimens for scanning 3D contours, transform 3D data into curvatures, compute the built-in stress of the film using a stress-curvature analytic model, and verify it through comparisons of the finite element method (FEM) simulations with the measured data. The curvature is used to describe the deflection and warpage modes and orientations of the specimen. Two primary factors that affect the warpage behavior of the electroplated Cu film on FRP substrate specimens are investigated. The first factor is the built-in stress in a Cu film that explains the room temperature warpage of the specimen under no thermal process. The second factor is the misfit of the coefficient of thermal expansion (CTE) between the Cu and FRP layer, which is a dominant factor during the temperature change. The calculated residual stress, and predicted curvatures using FEM simulation throughout the reflow process temperature range between 25 and 180 °C are proven to be accurate by the comparison of the FEM simulations and experiment measurements. [ABSTRACT FROM AUTHOR]

Wafer level bonding and stacking process for 3D stacked IC was proposed and technical issues were discussed. Cu bumps surrounded by recessed SiO 2 were thermo-compression bonded and electrically evaluated using Kelvin structures. Defects at the bonding interface such as voids were responsible for electrical resistance distribution. Wafer alignment during stacking process was found to be affected by several factors like non-uniform bump height, the spacers in a bonding fixture and wafer warpage. Step by step warpage measurement revealed that the wafer warpage was dependent on process steps and worsened at bonding step. [ABSTRACT FROM AUTHOR]

Purpose - This paper aims to reveal the causes and find an efficient method to compensate the shrinkage to reduce failure costs. Reflow-induced printed circuit board (PCB) shrinkage is inspected in automotive electronics production environment. The shrinkage of two-sided, large PCBs results in printing offset errors and consequently soldering failures on smaller components during the reflow soldering of the second PCB side. Design/methodology/approach - During the research, the investigations had to adapt to actual production in an electronics manufacturing plant. A measurement method was developed to approximate the overall shrinkage of the given product. With the shrinkage data, it is possible to perform an efficient compensation on the given stencil design in computer-aided manufacturing environment. Findings - It was found that even with the investigated lower-quality PCB materials, the compensation on the stencil significantly reduces the quantity of failures, offering an efficient method to improve the yield of the production. Research limitations/implications - Research was oriented by the confines of production (fixed PCB sources, given PCB materials, reflow process and production line), where an immediate solution is needed. Future investigations should be focussed on the PCB parameters (different epoxy types, glass-fibre reinforcements, etc.). Practical implications - The optimised production reduces overall failure costs. The stencil re-design and application is a fast and efficient way to immediately act against the shrinkage-induced failures. The method was successfully applied in automotive electronics production. Originality/value - The paper presents a novel approach on solving an emerging problem during reflow. [ABSTRACT FROM AUTHOR]

Inevitable and severe warpage and stress due to serious mismatch in coefficient of thermal expansion (CTE) between direct bond copper (DBC) plate and copper substrate will be induced into power devices during the reflow process, in which the ambient temperature around the package structure varies from room temperature to die attach solidification temperature and finally to room temperature. The existed warpage and stress or strain can be a hidden danger, and may impact the long-term reliability and durability. This paper investigated warpage and residual stress induced by reflow process in insulated gate bipolar transistor (IGBT) modules by means of the numerical and experimental analysis. The pre-warping of substrate, as an efficient method to reduce final warpage, was quantitatively examined to study effects of the pre-warped copper substrate on final warpage and residual stress in IGBT modules after reflow process. Finite element models considering the viscoplastic behaviors of solder materials and geometric nonlinearity were established to predict the warpage and thermal stress developed in IGBT modules during the reflow process. The aforementioned studies were found to be effective to reduce warpage of entire packaging structure induced by reflow process via finite element method-based simulation validated by experimental measurements. [ABSTRACT FROM AUTHOR]

We investigated an appropriate preparation condition for anode-supported SOFCs: (La,Sr)MnO3/cathode functional layer/YSZ/Ni-YSZ were fabricated with and without a Ni-YSZ anode functional layer (AFL) via the tape-casting method, where the AFL thicknesses were controlled from approximately 20 to 80 μm. The warpage depended on the co-sintering temperature of the electrolyte/AFL/anode-support half-cells, indicating that similar shrinkage of the electrolyte/ AFL/anode support is significant for lower warpages. The electrical properties of SOFCs with AFLs were compared to those of SOFCs without AFLs. In this regard, the use of an AFL decreased the ohmic and activation polarization resistances due to both the decrease in contact resistance between the electrolyte and the AFL and the increase in three-phase boundaries. However, the polarization diffusion increased when an AFL was employed, because AFL layers are denser than the anode support. The maximum power densities of samples with AFL were higher than those of SOFCs without AFLs, indicating that the decrease in both ohmic and activation- polarization resistances is more significant for improving the power densities, as compared to the concentration polarization resistance. [ABSTRACT FROM AUTHOR]

Among the various warpage measurement techniques, digital fringe projection (DFP) technique is recent trend because of its noncontact, full-field, and high-resolution measurement capabilities for measuring the warpage of chip packages, printed wiring boards (PWBs), and PWB assemblies (PWBAs). When using the DFP technique, reflective painting is generally sprayed on a sample surface to ensure uniform surface reflectance and to obtain better image contrast for the measurement process. However, because painted samples may no longer be reused, and the spray-painting process is not suitable inline, warpage measurement of unpainted chip packages, PWBs, and PWBAs using the DFP technique is required. One of the important tasks for measuring the warpage of unpainted PWBAs is segmentation of the chip package and PWB regions in unpainted PWBA images so that separate warpage of the chip packages and the PWBs can be determined. This paper presents a novel automatic segmentation method, region-growing method (RGM), which segments plastic-ball grid array (PBGA) packages and PWB regions in unpainted PWBA images. The experimental results show that the RGM successfully segments the PBGA package and PWB regions in unpainted PWBA images. The results also show that the RGM can be used in a DFP system to measures the warpage of PBGA packages and PWBs in unpainted PWBAs [ABSTRACT FROM AUTHOR]

This study investigated total warpage of a type of motorcycle seat support made of polypropylene (PP) during the entire process of injection molding and free-cooling after demolding. Finite element modeling (FEM) analysis for injection molding and its associated thermal deformation was carried out in the study. The effects of processing parameters on warpage occurring in different stages were analyzed by Taguchi optimization method. It was found that packing pressure is the major factor that affects warpage in the injection stage, whereas cooling time is the major factor in free-cooling stage. From an overall evaluation, melt temperature affects the total warpage most, followed by cooling time, packing pressure, packing time and mold temperature. The result proved that optimum parameters for minimizing final warpage of the injected parts can be obtained only when the deformation in the entire manufacturing process is addressed in both molding and demolding stages. [ABSTRACT FROM AUTHOR]

Due to the constant development of new components in microsystem technology the possibility to guarantee the reliability and lifetime of these components is essential. An efficient method for this purpose is Finite Element (FE) modelling. In order to shorten lengthy and expensive lifetime tests, FE simulations become more and more necessary. To obtain suitable FE models, multitude of material and technical component characteristics are needed. However, due to the rapid development of new materials, the characteristics are often insufficient or even unknown. Therefore additional measurements of the material or the complete system are necessary. Which material data is required depends first and foremost on the component and its usage. In this paper the importance of temperature dependent topographic measurements for the simulation model of a package design (Smart Power Module) will be demonstrated. The warpage of a whole package was measured at different temperatures in order to obtain unknown material behaviour like the chemical shrinkage and polymer relaxation. For this purpose, the Shadow Moiré Measurement Method was utilised. This work will focus on how to obtain experimental data of two different molding compounds (MC) in several stages of lifetime as well as implementing the results in a FE simulation model. [ABSTRACT FROM AUTHOR]

Electronic packaged devices are becoming increasingly smaller in size and higher in density while requiring higher performance and superior reliability. Warpage is one of the crucial factors for the thermomechanical reliability of electronic packages and warpage control becomes a more crucial process during the printed wiring board (PWB) fabrication and package assembly processes. This requirement necessitates more accurate methods of measuring warpage. The fringe projection methods are recent trends for measuring the warpage of chip packages, PWBs, and PWB assemblies (PWBAs) because of their noncontact, full-field, and high-resolution measurement capabilities. This paper presents a comparison of two fringe projection methods: laser fringe projection (LFP) (projection moiré) and digital fringe projection (DFP). Experimental results show that digital fringe projection has higher practical resolution, and better accuracy and precision than laser fringe projection. [ABSTRACT FROM AUTHOR]

Highlights: [•] Serious warpage of IGBT power module is induced from assembly processes. [•] A pre-bending substrate with a curve opposite the warp is proposed. [•] Design is validated by FEA and related actual measurements. [•] Increasing DBC thickness of Al2O3 layer reduces warps and bonded solder stresses. [•] A thicker base plate is suggested to reduce warping of the entire packaging structure. [ABSTRACT FROM AUTHOR]

One of the crucial factors for the thermo-mechanical reliability of electronic packages is warpage that occurs during the printed wiring board (PWB) fabrication, solder masking and solder reflow processes. As the quality and reliability requirements of electronic components (packages) become higher, warpage control becomes a more crucial process during the PWB fabrication (manufacturing) and package assembly processes. The warpage of PWBs, PWB assemblies and electronic packages are measured by various techniques. Each technique has both its advantages and disadvantages; therefore the choice of a particular technique depends on whether one wants to measure the warpage of a PWB, PWB assembly or chip package. This paper reviews the pros and cons, such as resolution, speed, costs, accuracy, in-line capability, flexibility, and robustness, of different techniques used for measuring the warpage of chip packages, PWBs and PWB assemblies. [ABSTRACT FROM AUTHOR]

Warpage and residual stresses in plastic electronics packages are partly due to the shrinkage of the epoxy molding compound during the cure stage and partly due to the mismatch in thermal expansions during the cooling stage. Here, we present a simple but robust way of estimating the warpage part due to the curing effects. The main assumption of our analytical model is that the molding compound remains in the rubbery phase during cure. Using this model, we derive expressions for the effective cure shrinkage and the stress-free temperature. The effective cure shrinkage is a single parameter that can be used as an intrinsic strain value in numerical simulations, which then allows accounting for the curing effects. The solutions are benchmarked with both experimental warpage curves from the literature and with full numerical simulations on a four-layer package consisting of lead frame, die attach, die, and the molding compound. Both comparisons show that our analytical predictions are well capable of accurately predicting cure-induced warpage in multilayer systems. [ABSTRACT FROM PUBLISHER]

The demands on flip chip packaging are increasing as the requirement for miniaturization and thinner silicon chips rises. In encapsulating flip chip packages it is important to not only maintain the mountability, but also to control the warpage of the package. In this paper, three types of underfill material with different thermomechanical properties are prepared. The requirements for achieving both longer interconnect life and the mountability with lower warpage are investigated. Underfill material with higher Young's modulus shows a longer interconnect life. From the results of failure analysis after thermal cycling, cracking at the edges of the bumps is observed. It is found from finite element analysis that underfill material with higher Young's modulus can effectively reduce the strain accumulating inside the bump. Underfill material with a low coefficient of thermal expansion reduces warpage after chip assembly. Therefore, optimization of both Young's modulus and the coefficient of thermal expansion of the underfill material are essential in order to achieve higher interconnect reliability while maintaining higher mountability. [ABSTRACT FROM PUBLISHER]

A waferlevel package (WLP) that has a flipchip form and uses thin-film redistribution with solder bumps to connect the package to the printed wiring board directly is discussed in this paper. A liquid molding compound is used for the encapsulation process. Since the thickness of the fan-out WLP is smaller than that in a traditional integrated circuit (IC) package, the fan-out WLP induces more serious warpage. Warpage plays an important role during the IC encapsulation process, and too large a warpage would not let the package proceed to the next manufacturing process. This paper uses an approach that considers both cure- and thermal-induced shrinkages during the encapsulation process to predict the amount of warpage. Cure-induced shrinkage is described by the pressure–volume–temperature–cure (PVTC) equation of the liquid compound. The thermally induced shrinkage is described by the coefficients of thermal expansion of the component materials. The liquid compound properties are obtained by various techniques, such as cure kinetics by differential scanning calorimetry- and cure-induced shrinkage by a PVTC testing machine. These experimental data are used to formulate the PVTC equation. A fan-out WLP is first simulated, and the simulation results are verified with experiments. It is shown that an approach that considers both thermal and cure/compressibility effects can better predict the amount of warpage for the fan-out WLP. The PVTC equation is successfully implemented, and it is verified that warpage is governed by both thermal and cure shrinkages. The amount of warpage after molding could be accurately predicted with this methodology. Simulation results show that cure shrinkage of the liquid compound is the dominant factor responsible for package warpage after encapsulation. [ABSTRACT FROM PUBLISHER]

A sequential optimization design method based on artificial neural network (ANN) surrogate model with parametric sampling evaluation (PSE) strategy is proposed in this paper. The quality index, such as warpage deformations, thickness uniformity, and so on, is a nonlinear, implicit function of the process conditions, which are typically evaluated by the solution of finite element (FE) equations, a complicated task which often involves huge computational effort. The ANN model can build an approximate function relationship between the design variables and quality index, replacing the expensive FE reanalysis of the quality index in the optimization. Moldflow Corporation's Plastics Insight software is used to analyze the quality index of the injection-molded parts. The optimization process is performed by a Parametric Sampling Evaluation (PSE) function. PSE is an infilling sampling criterion. Although the design of experiment size is small, this criterion can take the relatively unexpected space into consideration to improve the accuracy of the ANN model and quickly tend to the global optimization solution in the design space. As examples, a scanner, a TV cover, and a plastic lens are investigated. The results show that the sequential optimization method based on PSE sampling criterion can converge faster and effectively approach to the global optimization solution. [ABSTRACT FROM AUTHOR]

Abstract: In mold decoration (IMD) injection molding is a relatively new multi-process technique that has been used for improving the surface quality and achieving colorful cosmetic surface of molded parts. During IMD processing, the film having the same shape as mold cavity is first inserted into the mold then molten polymer is injected into the cavity. Heat transfer in the cavity surface is significantly retarded because of the low thermal conductivity of film. As a result of the asymmetric melt and mold temperature, thermal-induced part warpage easily occurs. The effects of inserted film on the asymmetric mold temperature field of IMD injection molding process for polypropylene (PP) parts were investigated. Experiments were conducted under various conditions of mold temperature, melt temperature and film thickness. The associated part warpage and crystallinity due to the asymmetric mold temperature were examined. It was found that the heat transfer retardation results in a delay in mold temperature drop at film–mold interface of the cavity surface and the maximum temperature difference compared with that of conventional injection molding without film may be as high as 10°C. The retardation-induced mold temperature difference and part warpage increased with increasing melt temperature and film thickness, whereas they decreased with increasing mold temperature. The crystallinity of molded PP parts increased through insertion of film. The mold temperature field of the IMD process and molded part''s warpage were predicted via numerical analyses. The predicted values showed reasonable agreement with the experimental results. Asymmetric cooling system design reduced part warpage when IMD processing was used. [Copyright &y& Elsevier]

The injection molding process of thin shallow part requires several concerns in order to produce a quality output. In part of determining the best parameter settings, among other considerations that need to be taken are the types of plastic materials selected and the mold design. This research is performed to optimize the parameter settings for the injection molding process of thin shallow part using three different types of plastic materials; Polypropylene(PP), Acrylonitrile Butadiene Styrene+Polycarbonate(PC+ABS) and Acrylonitrile Butadiene Styrene (ABS). The parameters setting and warpage results are analyzed using Taguchi Method and optimized using Analysis of Variance (ANOVA) to identify the contribution of each parameter. The processes are simulated in three experiments corresponds to the three selected materials using Moldflow Plastic Insight (MPI) software. The result shows that the process of thin shallow part using ABS and PC+ABS materials are influenced by the packing time parameter by more than 85%. For PP material, the most affecting parameter is the packing pressure by 58%. For all three materials analyzed, it can be concluded that the warpage of the thin shallow part are most affected by both packing parameters; the packing time and packing pressure. [ABSTRACT FROM AUTHOR]

- Mura defects become visible in a 13.3-in. TFT-LCD using chip-on-glass (COG) packaging when the thickness of the glass substrate is decreased from 0.5 to 0.3 mm. Mura, the non-uniform brightness in LCDs, is caused by COG packaging due to the mismatch of the coefficient of thermal expansion (CTE) and Young's modulus between the glass substrate and the IC-driver Si chips. In this paper, a 3-D finite-element-analysis (FEA) model, coupled with transient thermal analysis is first established to examine the warpage and stress behavior in the upper-glass-plate post-COG-package processing for identifying the root causes of the light-leakage phenomenon. Prior to that, the simulated warpage results are validated by surface-contour measurement. Data and modeling results show that a low bonding temperature together with a low modulus in novel ACF materials can effectively eliminate Mura. Besides, thinner silicon or a shorter length of Si chips as drivers offers enhanced reduction in the localized warpage, and thus can be a practical and low-cost solution for eliminating mura defects. [ABSTRACT FROM AUTHOR]