Numerical Simulation on the Warpage of Reconstructed Wafer During Encapsulation Process.

In order to solve the problem of small chip size, high fan-out ratio and other fan-out packaging, JCET ADVANCED PACKAGING CO. LTD. introduced a new kind of encapsulation material and a new wafer reconstruction method to complete the fan-out packaging. The new wafer reconstruction method is to divide the wafer into a single chip first, the single chip is facedown to the metal carrier, then the new encapsulation material is attached to the metal carrier with a single chip, and finally the reconstructed wafer is completed by lamination, leveling, and silicon support processes. However, it also faces warpage problems after curing. Excessive warpage poses a significant challenge to subsequent redistribution layer fabrication, mid-testing, and other automatic processes. In this article, finite element methods are used to study the effects of chip thickness, fan-out area, the encapsulation material properties, and the warpage of support silicon wafer after curing. The results indicate that wafer warpage will gradually increase with the thickness increasing of the encapsulated material, whereas the encapsulation material with low modulus and small Coefficient of Thermal Expansion (CTE) can improve warpage performance. High modulus, thicker support silicon has a significant effect on reducing warpage, and larger CTE support silicon can also effectively reduce wafer warpage because the larger CTE support silicon reduces the degree of mismatch with the encapsulation CTE. Thinner chips and higher fan-out areas tend to increase the warpage of the reconstituted wafer. The study of warpage of package structure and material properties can provide theoretical basis for predicting and improving warpage during the design and evaluation phase of the product. [ABSTRACT FROM AUTHOR]