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3D neuromorphic hardware system is first demonstrated in neuromorphic application as on‐chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of Ta2O5 and HfO2 is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non‐volatile memory devices. As a result, a memory window is improved over 106 in both types of devices. Improved and 3D integrated 12 × 14 array devices are identified in the synaptic characteristics according to the change of the synaptic weight from the interconnected Test Element Group (TEG) of the Complementary Metal Oxide Semiconductor (CMOS) circuits. The trained array devices present recognizable image of letters, achieving an accuracy rate of 92% when utilizing a convolutional neural network, comparing the normalized accuracy of 93% achieved by an ideal synapse device. This study proposes to modulate the memory windows up to 106 in an integrated hardware‐based neural system, considering the possibility of device degradation in both volatile and non‐volatile memory devices demonstrated by the hardware neural system. [ABSTRACT FROM AUTHOR]

The high curing temperatures required for traditional benzocyclobutene (BCB) materials have posed limitations on their applicability in high‐temperature‐sensitive fields. To address this challenge, our work focuses on the synthesis of a novel tetraphenylethylene (TPE)‐functionalized BCB monomer, TPE–BCB, achieved through the introduction of an ether bond onto the BCB's four‐membered ring via Williamson reaction. TPE–BCB demonstrates remarkable low‐temperature curing properties, characterized by a ring‐opening peak temperature of 190°C, representing a reduction of 60°C compared to conventional BCBs. Fully cured TPE–BCB resins exhibit exceptional dielectric and mechanical properties, coupled with minimal water absorption. Additionally, the incorporation of TPE with aggregation‐induced emission characteristics enhances the resins' luminescence and photolithographic capabilities. Notably, our TPE–BCB resins achieve impressive photolithography performance with a resolution ratio of up to 10 μm. In contrast to conventional BCB‐functionalized resins, TPE–BCB offers the dual advantage of low‐temperature curing and luminescence. This development marks a significant step in the advancement of low‐temperature curing BCB materials and serves as a pioneering example in the realm of multilayer wafer bonding materials. [ABSTRACT FROM AUTHOR]

Purpose: Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment. Design/methodology/approach: The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied. Findings: The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency. Originality/value: Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding. [ABSTRACT FROM AUTHOR]

Wafer bonding of β‐Ga2O3 and N‐polar GaN single crystal substrates is demonstrated by adding ZnO as a "glue" interlayer. The wafers are fully bonded such that Newton rings are not observed. Temperature‐dependent current‐voltage (I–V) measurements are conducted on the as‐bonded Ga2O3/ZnO/N‐polar GaN test structure and after annealing at 600 °C and 1100 °C. The impact of post‐annealing temperature on the electrical and structural characteristics of the bonded samples is investigated. A consistently ohmic‐like characteristic is obtained by annealing the bonded wafers at 1100 °C in N2, which is in part due to crystallization of ZnO and diffusion of Ga into ZnO which makes it n‐type doped. The wafer bonding of β‐Ga2O3 and GaN achieved in this work is promising to combine the material merits of both GaN and Ga2O3 targeting breakthrough high‐frequency and high‐power device performances. [ABSTRACT FROM AUTHOR]

Single-mode long-wavelength (LW) vertical-cavity surface-emitting lasers (VCSELs) present an inexpensive alternative to DFB-lasers for data communication in next-generation giga data centers, where optical links with large transmission distances are required. Narrow wavelength-division multiplexing systems demand large bit rates and single longitudinal and transverse modes. Spatial division multiplexing transmission through multicore fibers using LW VCSELs is enabling still larger-scale data center networks. This review discusses the requirements for achieving high-speed modulation, as well as the state-of-the-art. The hybrid short-cavity concept allows for the realization of f3dB frequencies of 17 GHz and 22 GHz for 1300 nm and 1550 nm range VCSELs, respectively. Wafer-fusion (WF) concepts allow the realization of long-time reliable LW VCSELs with a record single-mode output power of more than 6 mW, 13 GHz 3 dB cut-off frequency, and data rates of 37 Gbit/s for non-return-to-zero (NRZ) modulation at 1550 nm. [ABSTRACT FROM AUTHOR]

Aerosol jet printing (AJP) is an emerging additive manufacturing technology that is gaining increasing attention in the electronic field. Several studies have been carried out on the AJP of conductive, semiconductive, and dielectric polymers for electronic applications. However, wafer bonding is an application that is still uncovered by literature. Therefore, in this work, the AJP of benzocyclobutene (BCB) as a polymeric adhesive for wafer bonding is presented for the first time. A thorough characterization of the processing parameters is carried out to identify the most ideal conditions for printing at a relatively high speed. Then, square patterns are printed, proving the versatility of the AJP technology in terms of the reachable thickness of the deposited BCB patterns. Complex patterns with a resolution of ≈60 µm are also printed. The bonding properties of the BCB are characterized from a morphological and mechanical point of view. In particular, the shear strength of the BCB coatings deposited with AJP is ≈39 MPa and it is comparable with the shear strength of BCB coating deposited by spin‐coating. Consequently, AJP represents a valid alternative for the deposition of polymeric adhesive for wafer bonding. [ABSTRACT FROM AUTHOR]

This paper investigates a moiré-based mark for high-precision wafer bonding alignment. During alignment, the mark is combined with digital grating, which has the benefits of high precision and small size. A digital grating is superimposed on the mark to generate moiré fringes. By performing a phase calculation on the moiré fringe images corresponding to the upper and lower wafers, the relative offset of the upper and lower wafers can be accurately calculated. These moiré fringes are exceptionally stable, thereby enhancing the alignment stability. In this study, through practical experiments, we tested the rationality and practicability of the mark. [ABSTRACT FROM AUTHOR]

A bonding process was developed for glass-to-glass fusion bonding using Borofloat 33 wafers, resulting in high bonding yield and high flexural strength. The Borofloat 33 wafers went through a two-step process with a pre-bond and high-temperature bond in a furnace. The pre-bond process included surface activation bonding using O2 plasma and N2 microwave (MW) radical activation, where the glass wafers were brought into contact in a vacuum environment in an EVG 501 Wafer Bonder. The optimal hold time in the EVG 501 Wafer bonder was investigated and concluded to be a 3 h hold time. The bonding parameters in the furnace were investigated for hold time, applied force, and high bonding temperature. It was concluded that the optimal parameters for glass-to-glass Borofloat 33 wafer bonding were at 550 °C with a hold time of 1 h with 550 N of applied force. [ABSTRACT FROM AUTHOR]

Direct wafer bonding is one of the most attractive techniques for next-generation semiconductor devices, and plasma has been playing an indispensable role in the wider adoption of the wafer bonding technique by lowering its process temperature. Although numerous studies on plasma-assisted direct wafer bonding have been reported, there is still a lack of deep investigations focusing on the plasma itself. Other than the plasma surface treatment, the wafer bonding process includes multiple steps such as surface cleaning and annealing that require comprehensive studies to maximize the bonding strengths. In this work, we evaluate the various process steps of Si–SiO2 wafer bonding through case-by-case experimental studies, covering factors including the plasma conditions for surface treatment and secondary factors such as the time intervals between some process steps. The results show that plasma treatment with increasing input power has a trade-off between bonding strengths and interfacial voids, requiring the optimization of the plasma conditions. It is also noticeable that the effects of plasma treatment on wafer bonding can be improved when the plasma-treated wafers are stored in ambient atmosphere before the subsequent process step, which may suggest that wafer exposure to air during the bonding process is advantageous compared to processing entirely in vacuum. The results are expected to allow plasma-assisted direct wafer bonding technology to play a bigger role in the packaging process of semiconductor device manufacturing. [ABSTRACT FROM AUTHOR]

For radiation hardened image sensors, a Silicon-On-Insulator (SOI) -Si/ 4H-SiC hybrid pixel device was developed. The hybrid pixel device consists of one Si photodiode and three 4H-SiC nMOSFETs. At fabrication, SOI substrate was directly bonded on 4H-SiC substrate via SiO2. After bonding, the base silicon substrate and Buried Oxide (BOX) were removed by TMAH wet-etching. By using this SOI-Si/ 4H-SiC substrate, the SOI-Si photodiodes and 4H-SiC nMOSFETs were integrated in the same substrate. As a result, a response of the SOI-Si/ 4H-SiC hybrid pixel device to light illumination was successfully demonstrated. [ABSTRACT FROM AUTHOR]

In this letter, we present a photoreceiver front-end circuit that consists of an InP p-i-n photodetector (PIN PD) on an InP transimpedance amplifier (TIA) with double HBTs (DHBTs), in which the key integrated fabrication route of a transfer-printing (TP) process is introduced. Prior to integration, PDs and TIAs are individually fabricated on their respective wafers. Then, a discrete PD with only active layers is transferred onto the destination on a TIA wafer, thereafter, an on-chip coplanar waveguide connection is integrated. The PIN PD and DHBT TIA exhibit excellent performance, characterized by a responsivity of 0.51 A/W at $1.55~\mu \text{m}$ with a bandwidth of 20 GHz and a transimpedance gain of 36 dB $\Omega $ with a bandwidth of 27 GHz, respectively. Finally, the monolithically integrated circuit demonstrates a better frequency response by maximally reducing the parasitic effect, with an open clear eye diagram under a 20 Gb/s nonreturn-to-zero pattern, which evidently manifests its ability for ultrahigh-rate data operation. The present work, by employing a TP process, overcomes the issues in integrating discrete optoelectronic devices and proposes a unique approach for monolithic optoelectronic integrated circuit fabrication. [ABSTRACT FROM AUTHOR]

• Monolithic lithium niobate microfluidic chips are realized by facile fabrication. • Room temperature H 2 plasma proton exchange enhances the bonding performance. • High-density and diverse functional groups on the surface of lithium niobate. • Lithium niobate channel processing with high etching rate and smooth morphology. • The superior performance of full lithium niobate structure in SAW applications. In the quest to enhance the functionality and efficiency of lab-on-a-chip systems, integrating diverse physical phenomena such as acoustics, optics, and electronics into a single platform has emerged as a pivotal strategy. Lithium niobate (LiNbO 3 , or LN) stands out for its exceptional piezoelectric and electro-optic properties, making it an ideal candidate for such integrated systems. However, the full exploitation of LN in microfluidic applications has been hindered by the complex challenges associated with its fabrication. Addressing this gap, our research introduces a facile fabrication method for creating monolithic LN microfluidic chips. By employing a proton exchange-assisted surface-activated bonding technique, we achieve high-strength, flawless bonding at lower temperatures, overcoming the traditional barriers of LN machining. This method eliminates the chemical stability of LN by removing lithium ions and significantly enriches the surface with functional groups, leading to a bonding strength exceeding 10 MPa after annealing at 150 °C. Additionally, we have optimized an argon plasma etching process to ensure the creation of smooth LN channels at room temperature. The development of a fully integrated LN chip through this approach demonstrates superior performance, especially in surface acoustic wave (SAW) applications, compared to conventional PDMS/LN hybrids. This breakthrough not only realizes the fabrication process of LN microfluidic devices but also opens new avenues for the advancement of integrated microsystems across various scientific and technological domains. [ABSTRACT FROM AUTHOR]

[Display omitted] • Bonding interface is modified to a homogenous one with an epitaxial layer. • Epitaxial layer constrains the defects, disperses and reduces the heterogenous mismatch stress. • Epitaxial layer is doped to reduce the carrier recombination leakage current in this defect-rich layer. In the realm of optoelectronic integration, silicon-based Ge bonding has attracted great attention due to its advantages in short-wave infrared response and low cost. However, owing to the inherent lattice mismatch and thermal mismatch between Ge and Si, the bonded Ge-Si heterogenous interfaces encountered problems of thermal instability and high interface states. Herein, an approach of separating the bonding interface from the heterogenous interface is proposed through inserting a Ge epitaxial layer (GeEL) between the Si substrate and Ge film. This separation modifies the bonding interface to a homogenous one, alleviating the massive mismatch stress and achieving film relaxation, enhancing bonding stability in all aspects. Moreover, during 850 °C annealing, GeEL is doped via diffusion hence realizes electric filed modulation, inhibiting the carrier recombination leakage current and trap assisted tunneling in this defect-rich layer. A Ge-Si heterogenous PIN diode prepared by this bonding method has achieved a remarkable low dark current density (1.33 mA/cm2), a low ideality factor (1.11), and a high on–off ratio (1 0 6), confirming the outstanding quality of the bonded heterojunction. This work provides great prospects for higher performance, larger scale and multi-functional Si-based heterogenous material device applications. [ABSTRACT FROM AUTHOR]

We explore compatibility of Ru with Al-Ge eutectic wafer bonding. We first present experiments to check for the presence of Ru ternary alloy poisoning inhibiting Al-Ge melting as well as evaluations of Al-Ge melt wettability on Ru and diffusion outcomes following bond-simulating anneals. Results show that Ru is stable with no observed microstructural changes or dissolution in the melt, indicating no ternary poisoning for the applied thermal budget. Ru was found to act as an effective barrier offering good melt wettability in all considered configurations with Al and Ge. From inspection of the binary constituents of Al-Ge-Ru we propose that Al-Ge eutectic melting temperature will decrease marginally for Ru contamination in a 1-2% range before a drastic increase in melting temperature (>10°C/% Ru) at higher Ru compositions. We then demonstrate wafer-level packaged 200 mm devices and MEMS with strong bond outcomes of devices bearing Ru contacts. We conclude that Ru has high compatibility with Al-Ge eutectic bonding. [2022-0037] [ABSTRACT FROM AUTHOR]

Heterogeneous integration of micro-electro mechanical systems (MEMS) and complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) by 3D stacking or wafer bonding is an emerging approach to advance the functionality of microdevices. Aluminum (Al) has been of interest as one of the wafer bonding materials due to its low cost and compatibility with CMOS processes. However, Al wafer bonding typically requires a high temperature of 450 ° C or more due to the stable native oxide which presents on the Al surface. In this study, a wafer bonding technique for heterogeneous integration using electroplated Al bonding frame is demonstrated. The bonding mechanism relies on the mechanical deformation of the electroplated Al bonding frame through a localized bonding pressure by the groove structures on the counter wafer, i.e., press marking. The native oxide on the surface was removed and a fresh Al surface at the bonding interface was released through such a large mechanical deformation. The wafer bonding was demonstrated at the bonding temperatures of 250–450 ° C. The influence of the bonding temperature to the quality of the bonded substrates was investigated. The bonding shear strength of 8–100 MPa was obtained, which is comparable with the other Al bonding techniques requiring high bonding temperature. [ABSTRACT FROM AUTHOR]

We report a low-temperature and low-cost wafer-bonding method for silicon (Si) and indium phosphide (InP) based on a microcrystalline germanium (Ge) interlayer. The sputtered amorphous Ge (a-Ge) annealed at different temperatures exhibited different crystallinities. It is fully crystallized when the sputtering is carried out at 400 °C. For the microcrystalline Ge sputtered on the Si and InP, the Ge crystallizes along the crystal orientation of the Si, and exhibits a polycrystalline state on the InP. The crystallization evolution, bubble evolution, and bonding strength evolution at the wafer-bonded interface are investigated. The mechanism by which the bubbles are eliminated is revealed. In the case of samples featuring microcrystalline Ge grown on Si, the bonding interface consists of single crystal Ge. Bubbles can only escape from the bonding interface through atomic migration. Due to lattice mismatch and lack of gas transport channels, bubbles and dislocations form at the bonding interface. The samples with microcrystalline Ge grown simultaneously on Si substrate and InP wafer have a polycrystalline Ge layer (poly-Ge) at the bonding interface, which acts as a lattice barrier and gas transport channel. The combined action of lattice blocking and channeling effectively removes bubbles and dislocations at the bonding interface. After post-annealing, the bonding strength of the sample with fully crystallized intermediate layer can reach the bulk fracture strength of InP wafers. In addition, the carrier transport mechanism at the InP/Si bonding interface is also clearly elucidated. The above findings provide a direction for the preparation of high-performance Si-based III-V compound semiconductor photodetectors. • Microcrystalline Ge semiconductor interlayer is proposed to realize InP/Si bonding. • The InP/Si lattice is isolated by polycrystalline Ge and the dislocation nucleation is eliminated. • The crystallization status of microcrystalline Ge on Si and InP is clarified. • The process unveils bubble fade out at bonded interfaces via gas removal by atomic recombination and polycrystalline Ge. • A microcrystalline Ge layer is introduced to eliminate the influence of the oxide layer. [ABSTRACT FROM AUTHOR]

Aluminum nitride (AlN) is a ceramic material with excellent dielectric and thermal properties, and it is used in the microelectron and energy fields. Despite polishing, the roughness (rms >10 nm) of AlN wafers fabricated by sintering fails to meet the surface requirements (rms <0.5 nm) for direct wafer bonding. However, rough-surface wafer bonding of paired AlN and AlN can be achieved with the following procedure: (1) rough surfaces are activated by oxygen plasma to introduce strong capillary action, (2) reactions of AlN and bonding species (OH−) are promoted by clamping during storage and annealing and (3) low-temperature annealing (<150 °C) joins the two surfaces of AlN/AlN by synthesizing Al 2 O 3 at the bonding interface. TEM and XPS results show that a transition layer exists between bonding surfaces wherein the concentration of nitrogen decreases while that of oxygen significantly increases. [ABSTRACT FROM AUTHOR]

Aluminum-to-aluminum wafer bonding is a promising technique for future wafer-level packaging and heterogeneous integration. The main challenge for a successful Al-to-Al thermocompression bonding is the fast oxidation of the aluminum surface. In this article, a surface-activated Al-to-Al wafer bonding process for patterned 200-mm wafers is presented, which removes the oxide in an argon plasma and enables a high bond quality with an accurate alignment. The influence of the bonding parameters’ temperature (200 °C–300 °C), force (20–40 kN), and activation time (2.5–5 min) on the contact resistances and bonding yield is analyzed. Additionally, we modified an etch mask during wafer fabrication and thereby improved the condition of the Al pad surface, which resulted in a higher bonding quality. Based on this optimized wafer fabrication process, we achieved a high bonding yield of >85% and contact resistances in the $\text{m}\Omega $ range for bonding temperatures as low as 250 °C. This demonstrates the potential of Al-to-Al wafer bonding to create reliable interconnects for 3-D wafer-level integration. [ABSTRACT FROM AUTHOR]

A thin Si layer transfer process for monolithic 3D (M3D) integration is proposed using hydrogen ion (H+) implantation. The upper Si layer was transferred to CMOS circuits fabricated on the lower substrate by H+ implantation, oxide-to-oxide bonding, and a cleavage process at low temperature (< 500 °C). The M3D system comprising the photosensor connected to the CMOS device was demonstrated, where the thickness and roughness of the transferred Si layer were determined by H+ implantation and subsequent processes. The hetero-junctional photosensor was fabricated on the transferred Si layer, which generated the photocurrent ($\text{I}_{\text {ph}}$) by light exposure. The photosensor and ring oscillator circuits of the vertical structure implemented by the M3D process generated the $\text{I}_{\text {ph}}$ according to the light exposure intensity and showed different frequency behaviors accordingly. Compared with the continuous device scaling approach, M3D may be an alternative scheme for low-power, high-performance, and multi-functional devices. [ABSTRACT FROM AUTHOR]

Compared to silicon substrates, III–V materials based on GaAs and/or InP are generally limited to small diameters, up to 150 mm for GaAs and 100 mm for InP, even though bulk wafers of 150 mm diameter have already been sampled. Herein, a new technology is proposed to extend the diameter of these materials by combining the Smart Cut technology, which is based on wafer bonding and layer transfer techniques, with tiling. In this unique approach, the donor substrate used in the layer transfer step is not a simple bulk wafer (limited in diameter), but a large‐diameter rebuilt wafer produced by tiling many coupons of wafers, which are cut from bulk III–V substrates of small diameter. As already established in high‐volume manufacturing schemes for silicon on insulator substrates generated through the Smart Cut process, the donor substrate can be repeatedly reclaimed and reused, allowing this approach to be economically viable. Herein, the production of an InP film of 200 mm diameter on silicon substrates is investigated and successfully demonstrated. This generic approach can be adapted to produce other large‐diameter III–V on Si substrates, including those of 300 mm diameter. [ABSTRACT FROM AUTHOR]

Capacitive micromachined ultrasonic transducer (CMUT) was introduced as an alternative to the piezoelectric thick-film-based transducers in medical imaging applications. Gradually, CMUTs have been investigated in almost all the applications in acoustics due to their superior transduction properties. CMOS compatible process flow and limitless possibilities of miniaturization made CMUT a preferred choice for the ultrasound industry. This article comprehensively reviews all the applications in which CMUT was used until now. Such a complete review of the practical applications of CMUT has not been reported elsewhere. A topicwise presentation approach is adopted, and wherever possible, the necessary details of the device properties and experimental niceties were briefly covered. [ABSTRACT FROM AUTHOR]

We demonstrate, for the first time, GaAs thin film solar cells epitaxially grown on a Si substrate using a metal wafer bonding and epitaxial lift-off process. A relatively thin 2.1 μm GaAs buffer layer was first grown on Si as a virtual substrate, and a threading dislocation density of 1.8 × 107 cm−2 was achieved via two In0.1Ga0.9As strained insertion layers and 6× thermal cycle annealing. An inverted p-on-n GaAs solar cell structure grown on the GaAs/Si virtual substrate showed homogenous photoluminescence peak intensities throughout the 2″ wafer. We show a 10.6% efficient GaAs thin film solar cell without anti-reflection coatings and compare it to nominally identical upright structure solar cells grown on GaAs and Si. This work paves the way for large-scale and low-cost wafer-bonded III-V multi-junction solar cells. [ABSTRACT FROM AUTHOR]

We systematically investigated the wafer- bonded interfaces of p+GaAs/n+InGaAs and p+InGaAs/ n+InGaAs by using a circular transmission line method (CTLM) for the increased extraction accuracy. Based on the low-temperature bonding process at 50 °C, the bonded interfaces were successfully fabricated without degradation of the material quality. While the fabricated devices exhibited the linearly increased resistance as a function of channel distances, the p+InGaAs/n+InGaAs structure revealed the improved interfacial resistivity of $3.9\times 10^{-3} \,\, \Omega \cdot \text{cm}^{2}$ compared with $3.3\!\times \!10^{-2} \,\, \Omega \cdot \text{cm}^{2}$ of the p+GaAs/n+InGaAs. Since these values suggested good electrical properties in wafer-bonded structures, the developed wafer-bonded interfaces could be a good approach for integrating electronic and optoelectronic devices. [ABSTRACT FROM AUTHOR]

In this article, we have demonstrated 125-nm-gate InGaAs-on-insulator (InGaAs-OI) high-electron-mobility transistors (HEMTs) on Si substrates via wafer bonding. The highlights of this device were the i-In0.53Ga0.47As/i-InAs/i-In0.53Ga0.47As quantum-well channel for high RF performance by improving electron transport properties and the low processing temperature of 250 °C or less for monolithic 3-D integration. As a result, we obtained a current gain cutoff frequency (ƒT) of 227 GHz and a maximum oscillation frequency (ƒMAX) of 187 GHz. These results are the highest ever reported in monolithic 3-D RF transistors above LG = 100 nm. In addition, through the small-signal modeling, we have found that the impact of the back-gate (BG) on RF performances of top devices is a critical issue in M3D RF systems. [ABSTRACT FROM AUTHOR]

This paper presents a room temperature bonding technique of glass substrates with a transparent bonding interface. As a room temperature bonding method, surface activated bonding (SAB) is applied for the bonding of glass using Si intermediate layer. However, the bonding interface is colored by the deposited Si layers, which leads to lower applicability to optical devices. In this study, a new concept of SAB is developed using aluminum oxide intermediate layer. Glass substrates are successfully bonded at room temperature via the aluminum oxide intermediate layers activated by Ar ion beam irradiation, showing a bond strength of 1.32 J m−2. It is also shown that the optical characteristics at the interface such as transparency and reflectance are not degraded, while the bonding interface of the SAB using Si intermediate layer deteriorates. The XPS and STEM‐EDX analyses indicate that the bonding is achieved through the amorphous and O‐deficient aluminum oxide interface. This technique will provide a transparent interface for glass bonding by a room temperature process, which is highly desired in optical device fabrication. [ABSTRACT FROM AUTHOR]

A novel solid-liquid inter-diffusion (SLID) bonding process is developed allowing to use thin layers of the Au-Sn material in wafer-level microelectromechanical systems (MEMS) packaging while providing a good bonding strength. The bond material layers are designed to have a robust bond material configuration and a metallic bond with a high re-melting temperature, which is an important advantage of SLID bonding or with its alternative name, transient liquid phase (TLP) bonding. The liquid phase in SLID bonding is the gold-rich eutectic liquid of the Au-Sn material system, where the bonding temperature is selected to be 320 °C for a reliable bonding. The average shear strength of the bonds is measured to be 38± 1.8 MPa. The hermeticity of the package is tested with the He-Leak test according to MIL-STD 883, which yields a leak value lower than $0.1 \times 10^{-9}\,\, atm.cm^{\textit {3}}/s$. The vacuum inside the package without a getter is calculated as 2.5 mbar after cap wafer thinning. The vacuum level is well preserved after post-processes such as annealing at 400 °C and the dicing process. These results verify that thin layers of Au-Sn materials can be used reliably with the SLID or TLP bonding technique using the new approach proposed in this study. [2020-0353] [ABSTRACT FROM AUTHOR]

A novel high‐speed photodiode (PD) with an InGaAs/Si structure fabricated by atomic‐diffusion bonding (ADB) is proposed with the aim of improving the heat transfer. The fabricated PD shows a responsivity of 0.42 A W−1 and a 3 dB bandwidth of over 50 GHz. The maximum damage‐threshold photocurrent, or high‐power tolerance, is higher than that of a conventional PD on an InP substrate, thanks to the high thermal conductivity of Si used as the collector in the PD. [ABSTRACT FROM AUTHOR]

Fully-epitaxial magnetoresistance (MR) devices with half-metallic Heusler alloys has attracted considerable attention for years due to their excellent spin-dependent transport properties such as high MR ratio and ultra-low resistance-area product. However, their poor manufacturability due to the necessity of epitaxial growth on a special single crystalline substrate such as MgO(001) hinders their practical applications. To overcome this issue, in this study, we fabricated Heusler-based epitaxial current-perpendicular-to-plane giant magnetoresistance (CPP-GMR) film grown on Si substrate and directly bonded it to poly-crystalline electrode wafer by using three-dimensional (3D) integration processes such as direct wafer bonding and removal of backside Si substrate. First we explored suitable seed/buffer layers for the (001)-oriented epitaxial growth of Heusler CPP-GMR on Si(001) substrate. Si-subs/NiAl/CoFe seed/buffer structure was found to induce (001)-oriented epitaxial growth and to suppress an Al diffusion from NiAl to the Heusler electrode even after annealing at 500 °C, resulting in large MR ratio comparable to that with MgO substrate. After direct wafer bonding process, the microstructure analysis revealed clean damage-free bonded interface between the epitaxial Heusler GMR and poly-crystalline electrode films with Au capping layers. After the 3D integration processes, high MR performance has been successfully reproduced. This unique processing method enables the integration of high performance Heusler-based epitaxial spintronic devices for various practical applications. Image, graphical abstract [ABSTRACT FROM AUTHOR]

Reactive bonding using nanoscale multilayers based on the high specific surface/interface energy is a promising low-temperature and low-pressure wafer-bonding process. Herein, Si wafers were bonded using nanoscale Ag/Cu multilayers in N 2 or the ambient atmosphere. A flawless joint composed of Ag-rich and Cu-rich face-centered cubic (fcc) phases was achieved in N 2 with 22.2 MPa shear strength. However, a peculiar "fcc-(Ag)+voids/Cu 2 O/fcc-(Ag)+voids" three-layer sandwich structure with 11.1 MPa shear strength was formed due to significant out segregation of Cu toward the bonding-interface in the ambient atmosphere. The bonding mechanism and the role of oxygen were unveiled based on CALPHAD (CALculation-of-PHAse-Diagram) thermodynamic modeling. Image, graphical abstract [ABSTRACT FROM AUTHOR]

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Considering the demand for low temperature bonding processes in packaging of micro-electro-mechanical systems (MEMS), such as accelerometers or micro mirrors, in this paper a method for selective and energy-efficient heating of metallic intermediate bonding layers by applying high-frequency electromagnetic fields with frequencies in the range of 1. 0 < f < 2.0 MHz is presented. Therefore, the induction heating process was modeled and analyzed by means of numerical simulation. Additionally, heating experiments were carried out by using IR thermography in order to verify the simulation results. The developed inductor shape allows almost homogeneous heating of all metallic layers with heating rates of more than ΔT∕Δt = 150 K∕s. [ABSTRACT FROM AUTHOR]

Wafer-scale heterogeneous integration provides a viable pathway for the development of highly capable microsystems. However, it remains challenging to integrate die-and wafer-level components with a high-density interconnects while minimizing the system volume and within the temperature restrictions imposed by integrated circuits. Advancements in CMOS have motivated the development of low-temperature and low-resistance metal–silicon alloys or silicides. Nickel silicide (NiSi) is a CMOS-compatible material that forms at temperatures and anneal times within the thermal budget of commercial CMOS die and can be implemented with a wide range of nickel and silicon thin-film processing methods. We describe here the development of a 3-D integration strategy utilizing NiSi formation to generate both mechanical bonding and electrical interconnection between wafers. Specifically, we show that our NiSi-based wafer-bonding process is effective below 400 °C, at very short anneal times (minutes), and with a variety of thin-film processing methods. This NiSi-based process offers a robust approach for creating heterogeneously integrated microsystems in a CMOS-compatible fashion. [ABSTRACT FROM AUTHOR]

MEMS atomic vapor cells have a large variety of applications in chip-scale atomic devices such as clocks, gyroscopes or magnetometers. These cells are usually hermetically sealed by anodic bonding of borosilicate to silicon, a proven and reliable method, yet showing specific limitations such as inherent oxygen contamination of the cavity or limitation to a few combinations of materials. As an alternative, we report on the successful wafer-level fabrication of cells sealed by Cu-Cu thermocompression bonding. This alternative technique allows to overcome the constraints of anodic bonding while allowing a new variety of other materials. Characterization of the bonding quality is presented as well as a spectroscopic characterization in view of use for chip-scale atomic clocks (CSACs). [2019-0151] [ABSTRACT FROM AUTHOR]

Wafer bonding is an attractive technology that can join homo/heterogeneous materials into one composite. It has a wide range of applications in the micro-electro-mechanical system (MEMS), integrated circuit, consumer and power electronics, micro/nanofluidics, etc. Since all devices on the same wafer are sealed and tested at wafer size, it brings lots of benefits compared with the component-level packaging, such as substantial savings in time, materials, and labor. In this review, we firstly introduce the low- and room-temperature Si bonding and their applications in MEMS fabrication. Subsequently, we present applications of the third-generation semiconductor bonding towards optoelectronics. Due to the research in the electro-optical modulation of lithium niobate (LiNbO3) has made revolutionary progress in recent years, we also show the bonding method towards single-crystal LiNbO3 thin-film fabrication. Finally, we set our sights on the bonding of infrared materials, which might be the next research hotspot for the emerging ultrasensitive sensors. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a hydrophilic sapphire wafer bonding method combining plasma-activation and high-temperature bonding process. It is successfully employed in two sapphire bonding structures, including sapphire direct bonding and sapphire indirect bonding based on an intermediate amorphous Al 2 O 3 (a-Al 2 O 3). Transmission electron microscopy (TEM) results show that the a-Al 2 O 3 turns to be the single crystalline phase due to the induction of the sapphire substrate after high temperature bonding at 1000 °C. Moreover, high bonding strength is achieved for sapphire/sapphire (9.91 MPa) and sapphire/Al 2 O 3 /sapphire (17.96 MPa) structures and exceeds that of the bulk sapphire. This sapphire bonded structure with cavity can be applied to fabricate optical devices and pressure and temperature sensors for extreme high temperature environments. • A hydrophilic sapphire wafer bonding method combining plasma-activation and high-temperature bonding process is demonstrated. • For sapphire/sapphire bonding, the interface achieves a seamless bond on the atomic-scale. • For sapphire/Al 2 O 3 /sapphire bonding, the amorphous Al 2 O 3 turns to be the single crystalline phase. • This sapphire bonded structure with cavity can be applied in extreme high temperature environments. [ABSTRACT FROM AUTHOR]

III-V materials can be a very good channel candidate for monolithic 3D (M3D) integration due to the potential of high-performance and lower process temperature as compared with Si, since a low process temperature is crucial to avoid degradation of bottom devices. For III-V M3D integration, material transfer techniques are important, and such processes should be enabled by low process costs on a large wafer scale. In this study, we propose an InGaAs channel transfer technique by wafer bonding, epitaxial lift-off and III-V layers grown on Si substrate. Effective mobility of fabricated MOS HEMTs using transferred InGaAs layer was 1.3 times higher than that of Si MOSFETs. The proposing channel transfer technique would be useful for M3D integration because it provides wafer scalability, cost-effectiveness, back-gate biasing, and etc. [ABSTRACT FROM AUTHOR]

High-quality Si/Si and Ge/Si wafer bonding is achieved by introducing an ultra-thin microcrystalline Ge interlayer on Si substrate. The bonded wafer with a high-crystallinity Ge interlayer can effectively transfer and absorb bubbles, achieving high bonding strength of Ge/Si and Si/Si bonded wafers with bubble-free and oxide-free bonded interface after low-temperature annealing. Different from the tunneling model appropriated for the bonded wafers with low-crystallinity interlayer, a carrier recombination model is constructed for these with high-crystallinity interlayer to describe the carrier migration behaviors at the bonded interface. Furthermore, five carrier transport models are established to illustrate the effect of different crystallinity of the Ge interlayer on the carrier transport. This work provides a practical and simple method to fabricate high-quality bonding materials, which is of great significance for the development of micro-electronics devices. • Hydrophilic bonding with an interlayer is used to fabricate high-quality Ge/Si and Si/Si films. • The evolution of bubbles and oxide layers at the bonding interface is studied. • Annealing at low temperature to obtain high bond strength was investigated. • Oxide-free, bubble-free bonding at room temperature is achieved. • The carrier transport mode between Ge layers with different crystallinity is established. [ABSTRACT FROM AUTHOR]

Heterogeneous integration of LiNbO 3 and GaAs at room temperature has been achieved by using an activated Si atom interlayer, which demonstrate effectiveness in the fabrication of GaAs based LiNbO 3 wafer. By using the activated Si atom interlayer as the adhesive layer, 4-inch LiNbO 3 wafer is successfully directly bonded to the surface of GaAs wafer. The wafer bonding rate reaches over 95%. After bonding, the LiNbO 3 /GaAs bonding pair is cut into 10 × 10 mm2 square bonded chips. After annealing, the maximum bonding strength of square bonded chips exceeds 22 MPa. This means that the bonding strength of LiNbO 3 /GaAs wafer can be comparable to that of bulk materials. The characterization results of the bonding interface confirm that the intermediate amorphous Si layer is effective in improving the bonding strength and quality of LiNbO 3 /GaAs heterojunction. Heterogeneous integration of LiNbO 3 with GaAs and other Ⅲ-Ⅴ compound semiconductor materials is conducive to reducing the area occupied by optical communication platforms and improving the overall efficiency of devices. • 4 inches high-quality LiNbO 3 /GaAs heterostructure was prepared by Si atom intermediate layer. • The bonding mechanism of LiNbO 3 /GaAs was analyzed. • The bonding strength of LiNbO 3 /GaAs is 22 MPa respectively. This is the best known result. • The surface chemical states of LiNbO 3 , GaAs, Si deposition and debonding surface were characterized by XPS spectrum. [ABSTRACT FROM AUTHOR]

We report a first demonstration of GaAs HBT-OI fabricated using epitaxy growth, wafer bonding and layer transfer technique. Excellent bonding yield was found on the 200 mm GaAs HBT-OI wafer with wafer bowing of less than 90 µm. A dc gain of 20, and cutoff frequency (fT) of 6.5 GHz was measured for a device with emitter finger of 6 × 18 µm2. Its ideality factors for collector and base were 1.19 and 1.44, respectively. These results showed that the method of GaAs HBT-OI fabrication can be used for future integration of III-V on a common Si platform with low RF power dielectric attenuation. [ABSTRACT FROM AUTHOR]

• Highly sensitive CMUTs were fabricated with nitride-to-oxide wafer bonding technique. • The technique provided outstanding device uniformity with reduced fabrication complexity. • CMUTs functionalized by graphene oxide showed high relative humidity sensitivity. In this paper, we present highly sensitive capacitive micromachined ultrasonic transducer (CMUT) based gravimetric humidity sensors that are fabricated with nitride-to-oxide wafer bonding technology. In contrast to conventional wafer bonding CMUT processes that use expensive silicon-on-insulator (SOI) wafers to produce resonating membranes, the proposed process employs low-pressure chemical vapor deposition (LPCVD) silicon nitride as the membrane material. The proposed process provides thinner and lighter membranes, and thus more sensitive CMUT resonators. Furthermore, additional benefits such as reduced fabrication complexity and more controllable membrane thickness are possible. Ten MHz CMUTs were designed, fabricated and functionalized by graphene oxide (GO) with three different concentrations. The device uniformities and resonance frequencies were characterized by a laser vibrometer and a vector network analyzer. Humidity sensing performance of the sensors was analyzed through the resonance shifts in a relative humidity (RH) range of 11.3%–93.6%. The CMUT coated with the highest concentration of GO (0.5 mg/ml) exhibited the highest sensitivity of up to 15.3 kHz/%RH. Decent repeatability and a short response/recovery time were achieved by all the CMUT sensors. This study demonstrates that the CMUT humidity sensors that are realized with nitride-to-oxide bonding technology can be an excellent candidate for humidity sensing due to their high sensitivity and CMOS-compatible fabrication process. [ABSTRACT FROM AUTHOR]

In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility ($\mu _{\text {eff}}$) of 160 cm2/ $\text {V} \cdot \text {s}$ was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher ${V}_{\text {th}}$ tunability and improvement of $\mu _{\text {eff}}$ by bottom-gate biasing. [ABSTRACT FROM AUTHOR]

In this paper, we employ an electron beam writer as metrology tool to investigate distortion of an exposed pattern of alignment marks in heterogeneously bonded InP on silicon. After experimental study of three different bonding and processing configurations which represent typical on-chip photonic device fabrication conditions, the smallest degree of linearly-corrected distortion errors is obtained for the directly bonded wafer, with the alignment marks both formed and measured on the same InP layer side after bonding (equivalent to single-sided processing of the bonded layer). Under these conditions, multilayer exposure alignment accuracy is limited by the InP layer deformation after the initial pattern exposure mainly due to the mechanical wafer clamping in the e-beam cassette. Bonding-induced InP layer deformations dominate in cases of direct and BCB bonding when the alignment marks are formed on one InP wafer side, and measured after bonding and substrate removal from another (equivalent to double-sided processing of the bonded layer). The findings of this paper provide valuable insight into the origin of the multilayer exposure misalignment errors for the bonded III-V on Si wafers, and identify important measures that need to be taken to optimize the fabrication procedures for demonstration of efficient and high-performance on-chip photonic integrated devices. Unlabelled Image • E -beam metrology study of processing-induced deformations for 2" InP bonded to Si. • Bonding-induced pattern deformation dominant for the BCB bonding case. • Processing-induced pattern deformation dominant for the direct bonding case. [ABSTRACT FROM AUTHOR]

This paper presents a low-temperature process to transfer devices on ultrathin silicon layers from a parent substrate to a foreign substrate or stack. MOS devices were fabricated on silicon-on-insulator (SOI) wafer. The device wafer was then temporarily bonded on a carrier wafer. The handle layer was etched and the remaining ultrathin silicon device layer of ~1.4 $\mu \text{m}$ was transferred to a foreign substrate using permanent bonding. Here, we explored two different bonding approaches, namely, 1) the gold–indium (Au–In) transient liquid phase (TLP) bonding and 2) the epoxy bonding. We demonstrate the advantages of epoxy bonding method over the TLP method. The unique characteristic of this epoxy bonding approach is its capability to vertically stack multiple thin silicon layers. Furthermore, we demonstrate three-layer stacking of the ultrathin silicon layers with functional metal–oxide–semiconductor field-effect transistors in each layer. Electrical characterization results of nMOS/pMOS devices in each layer is presented and compared for before and after transfer. Changes in measured device performance before and after stacking are studied using simulations. The maximum process temperature in this approach is 150 °C, which is considerably lower than those reported in the literature. This result demonstrates the feasibility of multilayer low-temperature stacking. [ABSTRACT FROM AUTHOR]

We propose a new simple and low-cost alignment method utilizing electric contact for die stacking on an interposer or a printed circuit board. Without any expensive aligning/bonding equipment assisted by microscopy, we successfully stacked and bonded two silicon dies on a printed circuit board achieving alignment accuracy of $20~\mu \text{m}$ by utilizing only cheap equipment: manual micropositioners, a stage, a stand, a heat gun, a hot plate, and a power supply. In the proposed method, conductive alignment marks are fabricated on the bonding surfaces, and the electric contact between them are used to characterize misalignment. Therefore, the proposed method does not require any expensive complex microscopy equipment for alignment. In addition, alignment can be quickly and simply examined in situ by detecting electrical conduction during bonding. In experiment, alignment accuracy better than $20~\mu \text{m}$ and 100% bonding yield was measured in testing of 1800 bonds connecting two silicon interposer dies which were stacked on a printed circuit board by the proposed method. [ABSTRACT FROM AUTHOR]

Graphical abstract Highlights • A de-bondable SiC SiC wafer bonding, compatible with RTA at ∼1273 K, has been accomplished via a Ni nano-film. • The SiC SiC bonding by Ni nano-film achieved at room temperature without any pressure is seamless and robust. • The interfacial precipitation of layered carbon material parallel to the SiC surfaces is considered as the reason of interface weakening and de-bonding. Abstract In this study, a de-bondable wafer bonding method for silicon carbide (SiC) that can sustain rapid thermal annealing (RTA) at ∼1273 K has been realized. Two SiC wafers were bonded via an intermediate nickel (Ni) nano-film at room temperature without any pressure, which was characterized as a seamless and robust bonding. After the RTA process, the strength of the bonding interface was dramatically decreased and the de-bonding could happen at the interface during pulling test. Both of the mechanisms of bonding and de-bonding have been investigated through interface analyses. The sufficient atomic diffusion between two deposited Ni nano-films together with the interfacial mixing between amorphous SiC and the Ni nano-film contribute to the strong bonding of SiC SiC. The interfacial precipitation of layered carbon material parallel to the SiC substrates is assumed to be the reason of the interface weakening and de-bonding after annealing. It is believed that the further development of this bonding and de-bonding technology will advance thin SiC device fabrication, where the RTA process at ∼1273 K is widely used. [ABSTRACT FROM AUTHOR]

Imaging methods and 2D sparse arrays have been extensively researched to realize real-time 3D volumetric imaging with higher frame rates. In this study, we developed a 3D plane-wave imaging method using an annular capacitive micromachined ultrasonic transducer (CMUT) array as a breakthrough technique for realizing 3D imaging with a limited number of elements. We adopted the double oxidation and wafer bonding processes for creating the cavity of a CMUT with a 2 µm silicon membrane. To ensure surface uniformity before the bonding process, we implemented an additional reactive ion etching process after the second oxidation. The characterization results showed that the resonant frequency of the proposed device was 6.2 MHz with 65 V collapse voltage. The demonstration of real-time 3D volumetric imaging was conducted in oil using a Vantage 64 ultrasound research system. A plane-wave imaging scheme was used to detect wire phantoms immersed in the oil, with 289 plane waves transmitted over a range of 20° from the center of the annular array. The reconstructed data were used to create three orthogonal cross sections of the target region. The − 6 dB lateral and axial resolutions were 0.56 mm and 0.35 mm for the wires positioned at 18 mm from the proposed device, which were narrow enough to detect a wire phantom of 380 µm diameter. The normalized frame rate was calculated and compared with that in a previous study. We verified that plane-wave imaging has advantages in real-time imaging when compared with the classic phased array and synthetic phased array. Thus, the annular CMUT array is a promising mechanism for real-time 3D imaging with higher frame rate than that possible with previous methods. [Display omitted] • A real-time 3D plane-wave imaging method using an annular CMUT array is proposed. • 3D imaging is achieved using a limited number of elements. • The method requires low number of transmissions and delivers high frame rate. • The imaging quality is superior to that achieved with conventional methods such as CPA and SPA imaging. [ABSTRACT FROM AUTHOR]

We report a high-quality germanium (Ge) and silicon (Si) wafer bonding based on an intermediate layer of 5 nm-thick microcrystalline Ge. The bubble evolution, crystalline state evolution, and oxide layer evolution at the wafer-bonded interface are investigated. The mechanisms of bubble elimination and oxide layer disappearance are systematically analyzed. The sputtered microcrystalline Ge film consists of an amorphous Ge (a-Ge) layer and a low-quality single-crystal Ge (c-Ge) layer. The bubbles can be eliminated by the loose structure of the low-quality c-Ge at the bonded interface. Thus, the bubble-free bonded interface can be obtained. Besides, the bonding strength decreases with the increase of the sputtering temperature. The pressure on the bonded wafers before post-annealing can eliminate large bubbles and improve bonding strength. It is worth mentioning that the oxide layer and the threading dislocations are not observed at the bonded interface. This study can give a guidance for the subsequent manufacture of high-performance Si-based Ge optoelectronic devices. [Display omitted] • High-quality Ge/Si bonding with microcrystalline Ge interlayer is proposed. • The crystallization of a-Ge layer improves bonding strength after post-annealing. • The oxide layer at bonded interface is destroyed when a-Ge layer becomes c-Ge. • The low-quality c-Ge interlayer is a gas transporter to eliminate the bubbles. • Above three results lead to the improvement of the Ge/Si bonding quality. [ABSTRACT FROM AUTHOR]

Impact ionization has been seen to effect pinchoff in wafer-bonded aperture vertical electron transistors (BAVETs) comprising an InGaAs channel wafer-bonded to a III-nitride (III-N) drift region. The InGaAs-III-N junction is referred to as the wafer-bonded interface (WBI). Field plating can work well to manage the peak field and related impact ionization; however, it comes with a tradeoff of increased on resistance. In this paper, another control knob to breakdown is explored in the critical field (ξCRIT_IMPCT) of a BAVET. Investigation focuses on the characteristics of devices that differ in their InAlAs doping profile, namely p-type, unintentional, or a combination of both. These devices are tested for the role of field plate, built-in voltage, and trap behavior on pinchoff. It is shown that the change of doping causes a dramatic change to the trap activity at WBI. These traps ionize and determine ξCRIT_IMPCT as ionization of traps that leads to an early onset of impact ionization in the channel, which weakens pinchoff in a BAVET. Passivating traps is proposed to be a method to improving pinchoff. Trap passivation of WBI is demonstrated if InAlAs is doped p-type rather than unintentionally. A consequent enhancement in pinchoff and breakdown voltage of a BAVET is also reported. [ABSTRACT FROM AUTHOR]

In this brief, we fabricated Ge (110)-oninsulator (-OI) structures on Si substrates via wafer bonding and epitaxial lift-off (ELO) process using Ge layer grown on GaAs for low-temperature layer stacking toward monolithic 3-D integration. We also systematically investigated the lateral etching behaviors of AlAs, which was used as a sacrificial layer in the ELO process, on GaAs (110) substrates. Fabricated Ge (110)-OI was analyzed by surface atomic force microscopy, X-ray diffraction, Raman shift, and transmission electron microscope analyses. We found that the 40-nm-thick ultrathin-body Ge (110)-OI has very high crystal quality, indicating our Ge stacking process is very stable. [ABSTRACT FROM AUTHOR]