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Dislocations are basic crystal defects and represent one-dimensional native nanostructures embedded in a perfect crystalline matrix. Their structure is predefined by crystal symmetry. Two- dimensional, self-organized arrays of such nanostructures are realized reproducibly using specific preparation conditions (semiconductor wafer direct bonding). This technique allows separating dislocations up to a few hundred nanometers which enables electrical measurements of only a few, or, in the ideal case, of an individual dislocation. Electrical properties of dislocations in silicon were measured using MOSFETs as test structures. It is shown that an increase of the drain current results for nMOSFETs which is caused by a high concentration of electrons on dislocations in p-type material. The number of electrons on a dislocation is estimated from device simulations. This leads to the conclusion that metallic-like conduction exists along dislocations in this material caused by a one-dimensional carrier confinement. On the other hand, measurements of pMOSFETs prepared in n-type silicon proved the dominant transport of holes along dislocations. The experimentally measured increase of the drain current, however, is here not only caused by an higher hole concentration on these defects but also by an increasing hole mobility along dislocations. All the data proved for the first time the ambipolar behavior of dislocations in silicon. Dislocations in p-type Si form efficient one-dimensional channels for electrons, while dislocations in n-type material cause one- dimensional channels for holes.

The electrical behaviour of only a few dislocations was analysed. Such small numbers of defined dislocations were produced by hydrophobic semiconductor wafer direct bonding. The dislocation networks were placed in the channel of SOI MOSFETs where the source and drain regions of these devices act as contacts. Varying the channel width allows one to control the number of dislocations measured. Analyses of nMOSFETs proved an increase of the drain current caused by dislocations by more than one order of magnitude, while a decrease of the current is obtained for pMOSFETs. This indicates that electrons are present on the dislocation core in p-type material. The concentration of electrons on dislocations was estimated to be about 200 electrons per micrometer dislocation length, corresponding to a distance of about 5 nm between free electrons. This distance agrees with the space between Coulomb islands proved by low-temperature measurements. The investigations refer to a metallic-like conductance along dislocations caused by a two-dimensional carrier confinement. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Schottky diodes prepared on silicon bonded wafers with dislocation network (DN) lying parallel to the sample surface at the depth of ∼2 μm were investigated by means of capacitance-voltage (CV), current-voltage (IV) measurements at 80 K under optical illumination. A model of the interpretation of CV and IV data is presented and discussed. It is shown that electron-beam induced current (EBIC) mapping under the proper chosen forward bias voltages allows one to trace the inhomogeneities of the potential barrier at DN. The observed non-uniformity of the DN barrier heights was ascribed to inhomogeneous distribution of small oxide precipitates lying at the dislocation network plane (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The direct bonding of Si wafers reproducibly forms dislocation networks (DN) with a microscopic structure defined by the mutual crystallographic orientation between the pair of wafers used for the bonding procedure. This allows studying the electrical and optical properties of specific dislocations. In the present work three different DN structures were investigated using transmission electron microscopy (TEM), photoluminescence (PL) and deep level transient spectroscopy (DLTS). The results show close correlation between the structural, electrical and optical properties of dislocations and opens a possibility to identify structural peculiarities of the dislocations responsible for the high intensity of photoluminescence. Namely, the obtained results suggest that PL at ∼0.8 eV is related to screw dislocations in DN. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The electrical and optical properties of dislocations in Si are reviewed, namely dislocation-related recombination and luminescence, transport of minority and majority carriers along dislocations or the electric field around dislocations. It is shown that Si wafer direct bonding allows well-controlled formation of dislocation networks, giving rise to adjustable dislocation properties. Ideas for novel Si devices utilizing dislocations as active components are presented. In particular, dislocation-based light emitters at about 1.5 μm wavelength are demonstrated. Concepts for dislocation-based conductive channels and fast FETs, manipulators of biomolecules or thermo-electric generators are sketched.

Dislocation networks (DNs) formed by silicon wafer bonding were studied by means of Electron Beam Induced Current (EBIC) and Photoluminescence (PL). The measurements were performed on p–n junction diode structures prepared by ion implantation. EBIC signal was observed not only inside the diode structure, but also far outside the diode area. This finding demonstrates the ability of the bonding interface to efficiently collect minority carriers and indicates a high electrical conductivity of the dislocation network. In addition, circular inhomogeneities of charge collection were observed. The contrast of those regions was bright at high beam energies and turned dark or vanished at lower energies. The contrast behavior of the circular areas can be explained by local variations of collection efficiency and recombination at the DN, which might be a result of different density of oxide precipitates. PL mappings at 0.794 and 1.081 eV revealed similar circular areas.

A new concept for Si-based light emitting diodes (LED) capable of emitting at 1.5 μm is proposed. It utilizes D-band radiation from dislocations in Si. Whether a dislocation network created in a reproducible manner by Si wafer direct bonding or dislocation loops produced by Si ion implantation are employed. It is also stated that dislocation loops do not lead to the strong band-to-band electroluminescence at 1.1 μm of p-n diodes, as it was predicted in the literature. A MOS-LED (Fig. A) and p-n LEDs emitting at 1.5 μm are demonstrated by the authors. The maximum efficiency that could be achieved at room temperature is close to 1%. Levels in the bandgap which are probably involved in the formation of the D1-line at 1.5 μm are revealed. Moreover, the observation of the Stark effect for the D1-line is reported. Namely, a red/blue-shift of peak position was observed in electro- and photo-luminescence when the electric field in the p-n LED was increased/lowered. This effect may allow realization of a novel Si-based light emitter with electric field modulated emission wavelength. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Semiconductor wafer bonding offers a new degree of freedom in the design of material combinations without the common restrictions of the structure of the materials bonded. It is already an established method for the industrial production of advanced substrates (SOI) applied as basic material in high-performance device fabrication. SOI, i.e. a thin device layer on an insulator, is a promising concept for further device developments. The advantages of SOI can be combined with mobility enhancing materials such as strained silicon (SSOI) or germanium on insulator (GOI). The bonding process is not limited to a certain wafer diameter and is applicable to different material combinations which are important to integrate different functions on a chip (system on a chip, SoC). (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or compressive strain in the channel region of MOSFETs. Biaxial strain is introduced by growing of thin silicon layers on SiGe buffers and their transfer to oxidized silicon substrates. The latter forms strained silicon on insulator (SSOI) wafers characterized by tensile strain only. Future CMOS device technologies require the combination of the global strain of SSOI substrates with local stressors to increase the device performance.

The paper reviews methods of hydrophobic wafer bonding. Hydrophobic surfaces are obtained by removing the oxide layer from the surfaces of crystalline silicon substrates. Bonding such surfaces causes the formation of a dislocation network in the interface. The structure of the dislocation network depends only on the misalignment (twist and tilt components). The different dislocation structures are discussed. Because wafer bonding offers a method to the reproducible formation of such networks, different applications are possible

Spectroscopic Ellipsometry was employed to study the etching process of uniaxially strained Si (sSi) layers obtained by direct wafer bonding of Si wafers in a mechanically benstate followed by thinning one of the Si wafers, the donor wafer, by the smart-cut process, keeping the other, the handle wafer intact The smart-cut process requires a high dose hydrogen implantation into the donor wafer prior to bonding. As a result of the implantation conditions a ∼600 nm uniaxially sSi layer could be transferred onto the handle wafer. In order to thin down and smooth the surface damage of the transferred layer induced by the implantation and splitting process, the samples were dipped in a solution of tetra-methyl ammonium hydroxide (TMAH). The thicknesses of the transferred sSi layers determined from ellipsometry were in good agreement with those obtained from Transmission Electron Microscopy (TEM), while the roughness values were matching those obtained from Atomic Force Microscopy (AFM). The etching rate has also been determined.

Regular dislocation networks formed as a result of the direct bonding of Cz-Si wafers with oxide remnants on the pre-bonding surfaces were investigated. Besides the dislocation network, oxide precipitates were detected at the bonding interface. The precipitate density across the network was ~5×1010 cm-2, except small irregularly distributed circular areas, several mm in diameter, where the density was remarkably lower (

The paper presents a critical analysis of Si light emitters made by ion implantation and describes novel concepts for IR light emitters based on silicon nanostructures that do not need Er doping. It is shown that dislocation networks which can be generated in a well controlled way by wafer direct bonding exhibit promising light emitting properties. The luminescence of the dislocation networks can be tailored by the choice of the misorientation of the bonded wafers. It is demonstrated that efficient D1 emission (1.55 μm) at 300 K or D3 emission (1.3 μm) can be obtained for specific misorientations. An enhancement of the luminescence is observed when applying a bias voltage across the network, caused by a changed occupation of the states at the network. Oxygen in the dislocation network is supposed to increase the intensity of the D1 luminescence. Si nanowires are discussed as another potential candidate for IR emitters. Among other lines, efficient luminescence around 1.55 μm is found at 300 K in nanowires. This emission line is attributed to extended defects within the nanowires.

In order to investigate the electrical properties at the surface of dislocation rich silicon, we conducted Electrostatic Force Microscopy on cross-sections of samples prepared by Wafer Direct Bonding. The applied methods, namely Scanning Kelvin Probe Microscopy and non-contact Scanning Capacitance Microscopy, yield a distinct contrast at the position of the dislocation area, i.e. the bonding interface, indicating strong electrical activity. For an explanation of the explicit electrostatic potential extracted from the experiment a simple model taking into account only an intrinsic charge distribution at the dislocation area appears to be insufficient. Instead, a more complex approach has to be used considering carrier generation and recombination by additional, dynamic mechanisms. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

SSOI substrates were successfully fabricated using He+ ion implantation and annealing to relax thin (< 500nm) SiGe buffer layers, bonding and layer transfer processes to realize strained-Si layers onto oxide layers. The reduced thickness of the SiGe buffer possess numerous advantages such as reduced process costs for epitaxy and for reclaim of the handle wafer if the layer splitting is initiated in the SiGe/Si interface. The electron mobilities in the fabricated SSOI layers were measured using transistors with different gate lengths. An electron mobility of ~530 cm2 /Vs was extracted, being much higher than in non-strained SOI substrates. Furthermore, an 80% drive current (IDSAT) improvement has been measured for long channel devices.

Uniaxial strain on wafer-level was realised by mechanically bending and direct wafer bonding of Si wafers in the bent state followed by thinning one of the Si wafers by the smart-cut process. This approach is flexible and allows to obtain different strain values at wafer-level in both tension and compression. UV micro-Raman spectroscopy was used to determine the strain in the thin transferred Si layers. Numerical modelling by 3D finite elements of the strain provided a good description of the experimental results.

Direct wafer bonding between high-density-plasma chemical vapour deposited (HDP-CVD) oxide and thermal oxide (TO) has been investigated. HDP-CVD oxides, about 230 nm in thickness, were deposited on Si(0 0 1) control wafers and the wafers of interest that contain a thin strained silicon (sSi) layer on a so-called virtual substrate that is composed of relaxed SiGe (∼4 μm thick) on Si(0 0 1) wafers. The surfaces of the as-deposited HDP-CVD oxides on the Si control wafers were smooth with a root-mean-square (RMS) roughness of 2 nm. After HDP-CVD oxide deposition on the sSi/SiGe/Si substrates, the RMS roughness of the oxide surfaces was also found to be the same, i.e., >2 nm. To use these wafers for direct bonding the RMS roughness had to be reduced below 1 nm, which was carried out using a chemo-mechanical polishing (CMP) step. After bonding the HDP-CVD oxides to thermally oxidized handle wafers, the bonded interfaces were mostly bubble- and void-free for the silicon control and the sSi/SiGe/Si(0 0 1) wafers. The bonded wafer pairs were then annealed at higher temperatures up to 800 °C and the bonded interfaces were still found to be almost bubble- and void-free. Thus, HDP-CVD oxide is quite suitable for direct wafer bonding and layer transfer of ultrathin sSi layers on oxidized Si wafers for the fabrication of novel sSOI substrates.

Fabrication of strained silicon on insulator (sSOI) substrates by wafer bonding and layer splitting is described in this paper. The sSi layer of 20 nm thickness is obtained on an 8 in. virtual substrate that consists of a plastically relaxed SiGe layer grown epitaxially on Si(0 0 1) by chemical vapor deposition (CVD). The plastic relaxation of the initially pseudomorphic SiGe layer is mediated by helium implantation into the Si wafer below the SiGe/Si(0 0 1) interface and subsequent annealing. A SiO 2 layer is grown by plasma enhanced (PE) CVD on the sSi/virtual substrate prior to wafer bonding. The PECVD oxide layer is used to compensate the thermal stress existing at the bonding interface during annealing. The SiO 2 /sSi/virtual substrate wafers are then implanted with hydrogen at a high dose (3.5 × 10 16 H 2 + cm −2 ) and subsequently bonded to Si(0 0 1) handle wafers. Subsequent annealing of the bonded wafer pair leads to the transfer of the implanted layer (containing the sSi layer) from the virtual substrate to the Si handle wafer. The final sSOI structure is realized by subsequent chemo-mechanical polishing followed by selective wet chemical etching. The sSOI substrate shows good thickness uniformity (∼20 nm) of the sSi layer over the entire 8 in. area and the strain measurements indicate a value of ∼0.66%.

The paper deals with possibilities of utilizing dislocation structures as active components of devices. The suggested means for controlled formation of dislocations is direct wafer bonding, giving rise to well defined dislocation networks with adjustable properties. It is shown that the networks allow building light emitting diodes based on the D line luminescence of the dislocations. A light emitter at about 1.5 mm wavelength is demonstrated, with an efficiency potential estimated at 1%. Immobilization of biomolecules on Si surfaces by Coulomb interaction with the dislocations in the network is another application discussed. Finally, the potential use of dislocation networks as insulating layers permeable to impurities to be gettered and as three-dimensional buried conductive channels in the Si wafer is addressed.

Different methods of preparing sSOI wafers have been analyzed. The initial virtual substrate wafers are characterized by a 17 - 20 nm thick strained silicon layer grown either on a thick relaxed SiGe layer on a graded buffer or on a thin SiGe buffer relaxed by He implantation. Bonding and layer transfer experiments using different oxide layers proved that strained silicon layers are completely transferred if designed PE-CVD oxide layers were used. For both types of virtual substrates the oxide layers are deposited on top of the strained silicon and bonded to non-oxidized (blank) silicon wafers. A perfect layers transfer is obtained for virtual substrates having thick SiGe buffer layers (type A) even at 350ºC, while annealing at 450ºC is required for substrates with thin SiGe buffer layers (type B). The lower annealing temperature for substrates of type A is caused by the lower activation energy for blistering. The hydrogen implantation is here into the SiGe. For type B substrates the hydrogen implantation is into the underlying Si requiring a higher temperature for layer splitting (higher activation energy for Si).

On-chip optical interconnects require a CMOS-compatible electrically pumped Si-based light emitter at about 1.5 μm. Dislocations in silicon offer a recombination centre for light emission at the desired energy. Here we report on the radiative properties of dislocation networks, created in a well controllable manner at a certain depth of silicon wafers. Dislocation networks, created by ion implantation and annealing, misfit dislocation in SiGe buffers and a novel concept of dislocations created by misoriented direct bonded Si wafers are discussed. We demonstrate that under a specific misorientation a dislocation network with efficient room temperature D1 (1.55 μm) emission might be generated.

Defined placement of biomolecules at Si surfaces is a precondition for a successful combination of Si electronics with biological applications. We aim to realize this by Coulomb interaction of biomolecules with dislocations in Si. The dislocations form charged lines and they will be surrounded with a space charge region being connected with an electric field. The electric stray field in a solution of biomolecules, caused by dislocations located close to the Si surface, was estimated to yield values up to few kVcm � 1 . A regular dislocation network can be formed by wafer direct bonding at the interface between the bonded wafers in case of misorientation. The adjustment of misorientation allows the variation of the distance between dislocations in a range from 10 nm to a few Am. This is appropriate for nanobiotechnology dealing with protein or DNA molecules with sizes in the nm and lower Am range. Actually, we achieved a distance between the dislocations of 10–20 nm. Also the existence of a distinct electric field formed by the dislocation network was demonstrated by the technique of the electron-beam-induced current (EBIC). Because of the relatively short range of the field, the dislocations have to be placed close to the surface. We positioned the dislocation network in an interface being 200 nm parallel to the Si surface by layer transfer techniques using hydrogen implantation and bonding. Based on EBIC and luminescence data we postulate a barrier of the dislocations at the as bonded interface

Ambient pressure plasma processes were applied for surface activation of semiconductor (Si, Ge and GaAs) and other wafers (glass) before direct wafer bonding for MEMS and engineered substrates. Surface properties of activated wafers were analysed. Caused by activation high bond energies were obtained for homogeneous (e.g. Si/Si) as well as for heterogeneous material combinations (for instance Si/Ge) after a subsequent low temperature annealing process at 200°C. The resulting bond energies are analogous or higher as obtained for low-pressure plasma activation processes. The advantages of the ambient pressure plasma processes are described; a technical solution is discussed demonstrating the low risk for contamination and radiation damage.

When mirror-polished, flat, and clean wafers are brought into contact, they are locally attracted to each other and adhere or bond. This phenomenon is known as semiconductor wafer bonding. Different adhesion forces (van der Waals forces, hydrogen bonding) are the reason for the bonding effect at room temperature. The different bonding mechanisms acting in dependence on the surface conditions (hydrophilic, hydrophobic) are reviewed. Variations of the properties of bonded interfaces (structural, mechanical, electrical) during annealing are discussed. The focus is on low-temperature bonding techniques. Reasons for the formation of interface defects are presented. Applications of semiconductor wafer bonding for future developments are briefly summarized.

A new concept for a Si light emitting diode (LED) capable of emitting efficiently at 1.55 μm or at 1.3 pm, respectively, is proposed. It utilizes radiation from a well-defined dislocation network created in a reproducible manner by direct Si wafer bonding. The wavelength of the light emitted from the network can be tailored by adjusting the misorientation between the Si wafers. That way dominance of radiation at 1.55 μm (D1 line) or at 1.3 μm (D3 line) was achieved. There are hints that decoration of the dislocations by oxygen enhances the intensity of the D1 radiation. A critical analysis of the light emitter proposed by W. L. Ng et al. [Nature 410, 192 (2001)] using band-to-band emission is given. Its application at the above wavelengths would require a few microns thick SiGe layer on top of the Si substrate.

Reproducible formation of well-controlled dislocation structures is a prerequisite to use dislocations as an active part of devices. Regular dislocation networks have been formed at the interface by Si wafer direct bonding. The barriers of interface were generally smaller than 100 meV. The temperature dependence of the electron-beam-induced current (EBIC) contrast of the interface indicates a deep state density of a few 10E5 per cm along the dislocation lines in the network. It is also found that the dislocation networks in Si can act as effective channel for carrier transport. Photoluminescence (PL) reveals that the D line spectrum related to the dislocation networks can be tailored by the bonding misorientation. So, the D1 line can be made the dominating feature in the PL spectrum. It is suggested that regular dislocation networks represent an interesting new nanosystem for future applications, such as accommodation biomolecules onto silicon, dislocation-based LED or buried nanowires.

Wafer bonding of strained silicon (sSi) layer to oxidized Si (0 0 1) handle wafers is described in this paper. The sSi resides on two types of relaxed SiGe layers, a thick one (2 μm in thickness) grown on top of a compositionally graded buffer and a thin one (∼180 nm) for which He implantation and annealing are used to induce plastic strain relaxation by misfit dislocations. The thick SiGe layer shows a pronounced cross-hatch pattern resulting in a high surface micro-roughness (>1 nm). For direct bonding this roughness is reduced to Spontaneous and void-free bonded interfaces were obtained when both types of substrates were brought in contact with the oxidized handle wafers at room temperature. The bonding energies obtained after annealing at moderate temperatures (e.g. 500 °C) are sufficiently high to withstand further processing involved in layer transfer.

RIE-plasma etching of sub-micron structures in 150-200-nm thick Cr layers deposited on 4-inch SiO"2/Si/SiO"2 wafers was investigated as a function of the gas composition, RF power, and resist type. An optimal recipe is obtained yielding a Cr etching rate of about 7 nm/min and a ratio of the resist to the Cr etching rates of about 2 in case of etching the sub-micron structures in Cr with a ZEP 520 resist mask. SEM investigations show nearly vertical sidewalls of features etched in Cr layers with a lateral size ranging from 0.3 to 0.5 @mm.

Strained silicon devices provide for an enhanced carrier mobility compared to that of unstrained silicon devices of identical dimensions. The device performance gets even better when using strained silicon on insulator material. We report experimental procedures based on wafer bonding, smart cutting and selective chemical etching to obtain thin strained silicon (∼15 nm) on insulator wafers. The starting material is an 8″ wafer with pseudomorphically grown strained silicon on a so-called virtual substrate as realized by epitaxial chemical vapor deposition of relaxed SiGe (grown with a grading rate of 10% Ge in the SiGe-alloy per 1 μm layer deposition) on a Si(0 0 1) substrate. The starting and bonded wafers are characterized: (i) structurally using transmission electron microscopy, (ii) topographically, using atomic force microscopy and (iii) the strain is quantified using UV-Raman spectroscopy.

Studies dealing with the bonding behavior of silicon wafers coated with thermal oxide, plasma-enhanced chemical vapor deposition (PE-CVD) oxide, PE-CVD oxynitride, PE-CVD nitride and low-pressure (LP) CVD nitride are presented. The PE-CVD layers require a chemo-mechanical polishing (CMP) before bonding to reduce the surface roughness. The bonding energies of the wafer pairs with different interface layers are similar to those of bonded hydrophilic silicon wafers. Infrared microscopy of patterned wafer pairs reveals interfaces which are almost free of bubbles. Presumably, the gas, which usually generates such interface bubbles, diffuses into the interface cavities. The tensile strengths of patterned wafer pairs including a PE-CVD oxide or a PE-CVD oxynitride interface layer are about twice as high as for patterned hydrophilic silicon wafer pairs.

The effect of plasma pretreatments (reactive ion etching in SF 6 and SF 6 /O 2 ) on Si/Si wafer direct bonding was investigated. Etching in SF 6 caused a bonding behaviour generally known from hydrophobic (HF etched) samples, whereas adding O 2 to the feed gas caused the Si(100) surfaces to become hydrophilic and spontaneous bonding was achieved. The structure of the bonded interfaces were analysed by high-resoluti on electron microscopy, ellipsometry, multiple internal reflection spectroscopy, and secondary ion mass spectroscopy. All the plasma treatments result in an interface structure analogous to that known from bonded hydrophobic wafer pairs. The interface does not involve an additional layer such as an SiO2 or an amorphous Si layer but small one-dimensional defects forming a disturbed layer about 1 to 2 nm thick.

Metallic impurities are detrimental to many silicon devices and limit the efficiency of multicrystalline silicon solar cells. Therefore they are a major subject of ongoing research. Photoluminescence spectroscopy is a promising technique for detecting precipitated metals in silicon because of its sensitivity to the minority carrier density and to specific types of defects; however the impact of impurities on the defect luminescence could not be clarified yet. In this letter we examine the role of micron-sized iron and copper precipitates in direct bonded wafers by micro-photoluminescence spectroscopy. Both kinds of precipitates are detectable by means of the reduced band-to-band luminescence. An element-specific effect on the defect luminescence is observed. The results are confirmed by X-ray fluorescence spectroscopy. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

In microsystems technologies, frequently complex structures consisting of structured or plain silicon or other wafers have to be joined to one mechanically stable configuration. In many cases, wafer bonding, also termed fusion bonding, allows to achieve this objective. The present overview will introduce the different requirements surfaces have to fulfill for successful bonding especially in the case of silicon wafers. Special emphasis is put on understanding the atomistic reactions at the bonding interface. This understanding has allowed the development of a simple low temperature bonding approach which allows to reach high bonding energies at temperatures as low as 150°C. Implications for pressure sensors will be discussed as well as various thinning approaches and bonding of dissimilar materials.

Multiple internal reflection spectroscopy (MIRS) was applied to analyse atomic bonds at deep (500 μm) interfaces of directly bonded Si/Si wafer pairs. It is shown that under the conditions used the polarized spectra contain information only about the interface layer a few nanometers thick. Examples are given of analysing the Si-H- and SiO-H vibration modes and bands of undissociated water in interfaces of bonded hydrophobic and hydrophilic wafer pairs, respectively, after annealing at temperatures between 200 and 1100 °C. Variations of the bonding behaviour (especially caused by alterations of the Si-H bonds) are discussed.

Two-dimensional arrangements of well-controlled numbers and types of dislocations were realized in thin SOI device layers by semiconductor wafer bonding. Remarkable improvements of nMOSFET performance are obtained if the defects are positioned on well-defined locations in the channel. An increase of the drain current (ID) was proved by one order of magnitude at room temperature. The increase of ID depends on the dislocation type. Mixed dislocations result in the highest increase of the drain current. Such MOSFETs operate also at cryogenic temperatures with excellent parameters (subthreshold swing of 21 mV/dec, etc.). Coulomb blockades related to dislocations are observed making it possible to realize single electron transistors for future cryogenic applications.

The bonding interface of bonded hydrophobic Si pairs has been found to be a strong gettering layer. By thinning one wafer of the pair, the location of the gettering layer with respect to the defect-free Si surface layer where devices are fabricated can be varied from more than 500 μm to deep-submicrons. Secondary ion mass spectrometry and simulation results suggest that F atoms at the interface are primarily responsible for the gettering effect via Au-F ion pairing. It appears that a significant segregation of Au to the hydrophobic bonding interface is observed during annealing at 900 °C. These results are compared to gettering of Au by a hydrophilic bonding interface.

Interfaces of bonded hydrophilic and hydrophobic wafer pairs are studied by multiple internal reflection spectroscopy after annealing at 1100°C. Si−Hx and SiO−H stretching modes are still present in bonded hydrophilic wafers. Interfaces of bonded hydrophobic wafers, prepared by joining HF-etched surfaces without defonized water rinsing, are characterized by the dominance of hydrides (SiH, SiH2, SiH3). Their concentration is about 100 times higher than for bonded hydrophilic wafers. Comparison with the ATR-spectra of HF-treated surfaces showed appreciable shifts in the peak positions indicating that Si−H bonds might be involved in the bonding process.

β-SiC layers produced on Si substrates by rapid thermal chemical vapor deposition have been transferred onto oxidized Si substrates by bonding and etchback. For SiC films with a mean surface roughness of about 20 A, room temperature bonding to smooth oxidized Si wafers is possible under the influence of an external force. For 4 in. diam substrates, bonding of ∼85% of the area was obtained. Sections of the SiC/Si layer of the bonded pair peeled off when the Si substrate of the SiC layer is thinned down to ∼150 μm and below. This is probably caused by the low interface fracture energy due to trapped air at the bonding interface and by outgassing from the thermal oxide of SiC in addition to the film stress. Multistep annealing at 1100 o C between KOH etches of the Si substrate can enhance the interface fracture energy of the bonded pairs. A densification step of the SiC thermal oxide after dry oxidation helps to reduce the trapped gas in the oxide. Auger and transmission electron microscope, results have verified that the transferred SiC layer retains its original properties

Strained silicon on insulators (sSOI) wafers with a supercritical thickness of 58 nm were produced using thin strain relaxed SiGe buffer layers, wafer bonding, selective etch back and epitaxial overgrowth. Raman spectroscopy revealed an homogeneous strain of 0.63 plusmn 0.03 % in the strained Si layer. Long channel n-type SOI-MOSFETs showed very large electron mobilities up to 1200 cm2/Vs in the strained Si devices. These values are more than two times larger than those of reference SOI n-MOSFETs. Mobility simulations with state of the art scattering models are then used to interpret the experiments.

A new concept for a Si light emitting diode (LED) capable of emitting at 1.5 mum efficiently is proposed. It utilizes radiation from a well-defined dislocation network created in a reproducible manner by Si wafer direct bonding. The wavelength of the light emitted from the network can be tailored by adjusting the misorientation between the Si wafers

A novel Si MOS-LED is demonstrated, which is fully compatible with Si technology. It is based on a dislocation network fabricated by wafer direct bonding. Light emission at 1.5 μm was observed when the network was near the Si/SiO2 interface close to/inside the accumulation layer induced by the gate voltage.

Spatial light modulators (SLMs) based on micromirrors for use in DUV lithography and adaptive optics require very high mirror planarity as well as mirror stability. The ideal mechanical properties of monocrystalline silicon make this material ideally suited for use in high precision optical MEMS devices. However, the integration of MEMS with CMOS poses certain restrictions on processing temperatures as well as on the compatibility of materials. The key to the successful fabrication of monocrystalline silicon micromirrors on CMOS is the silicon layer transfer process. Here, we discuss two carefully adapted wafer bonding processes that are CMOS compatible and that allow the transfer of a 300nm thick monocrystalline silicon thin film from a SOI donor wafer. One process is based on adhesive bonding using a patterned polymer layer, while the other process is based on direct bonding to a planarization layer of polished glass.

In silicon wafer bonding, the initial contact area spreads laterally with a typical speed on the order of 10 mm/s. We observed that this lateral bonding speed increases with decreasing ambient pressure, and is independent of the distance of the contact front to the rim of the wafers and independent of wafer thickness. From these results, we conclude that the lateral bonding speed is mainly determined by pressing the ambient gas out between the two wafers from a very localized area close to the propagating bonding front.

Bonded hydrophobic wafer pairs (PEW wafers) are applied as alternative substrates for optical devices (pin-diodes and complex MOEMS). Important parameters of diodes are analysed at temperatures up to 160/spl deg/C (dark current, photocurrent, CV-curves, rise time). Diodes produced on bonded hydrophobic wafer pairs show a similar or better behaviour than components prepared on the standard epitaxial wafers.

Wafers prepared by an HF dip without a subsequent water rinse were bonded at room temperature and annealed at temperatures up to 1100 °C. Based on substantial differences between bonded hydrophilic and hydrophobic Si wafer pairs in the changes of the interface energy with respect to temperature, secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM), we suggest that hydrogen bonding between Si‐F and H‐Si across two mating wafers is responsible for room temperature bonding of hydrophobic Si wafers. The interface energy of the bonded hydrophobic Si wafer pairs does not change appreciably with time up to 150 °C. This stability of the bonding interface makes reversible room‐temperature hydrophobic wafer bonding attractive for the protection of silicon wafer surfaces.

Wafer bonding started as a specific way to fabricate inexpensive thick (>1 /spl mu/m) film silicon-on-insulator (SOI) materials of high quality. In the meantime, also ultrathin SOI layers can be produced by wafer bonding and proper thinning techniques. In addition, silicon wafer bonding has shown to be a versatile technique for fabricating sensors and actuators. Especially in this area it is desirable to perform bonding at a temperature as low as possible. Wafer bonding may also be used to produce combinations of materials which may differ in terms of structure, crystallinity or lattice constant. The last feature allows the fabrication of III-V compound combinations which are not lattice matched and may be used for vertical cavity surface emitting lasers.

The further increase of the wafer diameter, required for high- volume production of integrated circuits, is combined with an increasing thickness of the wafers. The chip thickness, however, decreases in the same time to about 20 micrometer. Therefore techniques are necessary allowing the thinning of the whole wafer in a time and cost efficient way and with a high accuracy. The actual processing techniques and further trends for wafer thinning are summarized. The most important parameters [final surface structure (roughness), generation of subsurface defects, mechanical stresses] are discussed. Concepts of handling techniques and final processing steps of ultra-thin wafers are presented.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.