Search

This work presents an analytical model for the drain and gate currents of silicon nanowire and nanosheet MOS transistors valid in all operating regions in the temperature range from 300 to 500 K. Analytical models for the tunneling components as well as for the reversely biased drain‐to‐channel PN junction are presented. Also, the models accounting for the necessary modifications in the silicon physical quantities for high‐temperature operation, such as the maximum carrier mobility, the bandgap, and the intrinsic carrier concentration, are presented. The proposed model uses a single set of parameters, extracted at room temperature, to describe the high‐temperature operation of silicon nanowire MOSFETs. The model is validated with comparisons between modeled and experimental results for devices with different fin widths and operating temperatures, with good agreement. [ABSTRACT FROM AUTHOR]

This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation. [ABSTRACT FROM AUTHOR]

• The gate-induced drain leakage (GIDL) in stacked nanowire transistors for temperatures of operation between 300 K and 580 K is experimentally assessed for devices with different channel lengths and fin widths. • The temperature rise increases the current due to GIDL and its dependence on the device width. • For a fixed negative gate voltage the channel length reduction increases the GIDL current for nanowires independent of the temperature, except for devices suffering from threshold voltage roll-off due to short-channel effect. • Three-dimensional TCAD simulations showed that drain leakage is mainly composed of band-to-band tunneling rather than junction leakage, even at high temperatures. • The band-to-band generation rate intensity is larger in the bottom nanowire, with Ω-gate architecture than in the top GAA nanowire. • Band-to-band generation becomes higher as length is reduced and fin width is increased and is larger in the drain extension and gate overlap regions. • The temperature rise changes valence and conduction energy levels causing the reduction of the lateral distance between the two levels, favoring the transversal band-to-band tunneling. This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling. [ABSTRACT FROM AUTHOR]

• The gate-induced drain leakage (GIDL) in stacked nanowire and nanosheet transistors at high temperatures of operation is experimentally assessed for the first time. • The temperature rise increases the current due to GIDL and its dependence on the device width. • Temperature rise increases band-to-band generation in the overlap region between the drain and the gate, causing a larger GIDL current. • Device width increase weakens coupling, allowing the region where band-to-band tunneling occurs to extend to the interior of the undoped body, contributing to the rise of GIDL. This paper presents an experimental assessment of gate-induced drain leakage (GIDL) in stacked nanowire and nanosheet transistors for different temperatures of operation, in the temperature range between 300 K and 580 K. The temperature rise increases the GIDL current and its dependence on the device width due to the increase of band-to-band generation with temperature and weakening of electrostatic coupling. [ABSTRACT FROM AUTHOR]

This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistors connected in series with gates shortened, acting as a single device. The doping concentration of the two transistors in the structure is different, leading to higher threshold voltage of the transistor at the source side of the composite structure than that of the transistor at the drain side. By reducing the doping concentration level at the channel of the transistor at drain side of the composite structure, forcing it to work in saturation, part of the applied drain bias is absorbed and does not reach the transistor close to the source, which is the main responsible for the overall device characteristics. As a result, larger drain current level and transconductance are obtained in comparison to symmetric self-cascode (where both transistors present same doping level) apart from promoting output conductance reduction. The transconductance, output conductance, Early voltage, and intrinsic voltage gain are used as figures of merit to demonstrate and validate the advantages of the proposed structure. The influence of channel length and doping concentration are also evaluated. The A-SC configuration is fully compatible with any standard FD SOI MOSFET technology with multiple threshold voltages. A simulation analysis demonstrates the feasibility of the proposed asymmetric structure in a UTBB FD SOI technology. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which includes short-channel effects, and accounts for the dependences on the device dimensions, doping concentration, and quantum effects. It is validated with 3-D Technology Computer-Aided Design (TCAD) simulations for several device characteristics and biases as well as with the experimental results. [ABSTRACT FROM AUTHOR]

The aim of this paper is to analyze the substrate bias influence on the operation of junctionless nanowire transistors based on 3-D simulated and experimental results, accomplished by modeled data. The threshold voltage, the maximum transconductance, the subthreshold slope, the drain-induced barrier lowering (DIBL), and the $I_{{\rm ON}}/I_{{\rm OFF}}$ ratio are the key parameters under analysis. It has been shown that the negative back bias can reduce the short-channel effects occurrence, improving the $I_{{\rm ON}}/I_{{\rm OFF}}$ ratio and DIBL. [ABSTRACT FROM PUBLISHER]

This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model. [ABSTRACT FROM AUTHOR]

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors. [ABSTRACT FROM AUTHOR]

This Letter presents an analysis of the zero temperature coefficient (ZTC) bias in junctionless nanowire transistors (JNTs). Unlike in previous works, which had shown that JNT did not present a ZTC point, this work shows that ZTC may occur in JNTs depending mainly on the series resistance of the devices and its dependence on the temperature. Experimental results of drain current, threshold voltage, and series resistance are presented for both long and short channel n and p-type devices. [ABSTRACT FROM AUTHOR]

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature. [ABSTRACT FROM AUTHOR]

In the paper [1], the authors would like to make the following corrections. 1)

Equation (11) needs to be read as \begin{equation*} V_{G2} =V_{FB} -V_{FB} \frac {\ln [1\!+\exp (A_{1} (1\!-\!(V_{G} \!-\!Vy)/V_{FB} ))] }{\ln [1+\exp (A_{1} )] }. \end{equation*} [ABSTRACT FROM AUTHOR]

This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. The study has been performed for devices with different channel lengths and doping concentrations biased close to the threshold and deep in linear regime. It has been shown that the surface potential of JNTs is strongly influenced by the substrate bias even above threshold. Thus, the drain current noise spectral density and the effective trap density can be improved or degraded depending on the bias applied to the substrate of the devices. Additionally, it is shown that, the variation on the substrate bias enables the evaluation of traps with different activation energy ranges, which is more evident in heavier doped devices due to the higher threshold voltage sensitivity to the substrate bias. [ABSTRACT FROM AUTHOR]

This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire Transistors. The proposed method uses the subthreshold slope extraction combined with the substrate bias in order to induce a variation in the channel potential, such that the interface trap density can be extracted for a significant energy range. Three-dimensional TCAD numerical simulations have been performed to analyze the accuracy of the proposed method considering different concentrations and trap density profiles (uniform and exponential). The influence of the device width variation on the trap energy determination has been analyzed, showing that only for positive substrate biases the energy might be affected. The method precision was also analyzed, showing that the trap density extraction is only effectively affected for low N it values, which do not influence significantly the device performance. Finally, the method has been applied to experimental transistors with high-κ and silicon dioxide gate dielectrics showing consistent results. [ABSTRACT FROM AUTHOR]

Abstract: This work proposes a physically-based definition for the threshold voltage, VTH , of junctionless nanowire transistors and a methodology to extract it. The VTH is defined as the point of equal magnitude for the drift and diffusion components of the drain current. The methodology for VTH extraction uses the device transconductance over drain current ratio characteristics. An analytical model for the threshold voltage based on the same definition has also been developed. Both VTH extraction method and model have been validated through 3D simulations and have been applied to experimental devices. The proposed method has shown to provide a correct dependence on the temperature, while the double derivative of the drain current method overestimates this variation. [Copyright &y& Elsevier]

Highlights: [•] Current noise spectral density of JNTs with different gate dielectrics is evaluated. [•] Devices with SiO2 gate dielectric present lower trap density than the HfSiON ones. [•] Lorentzian noise is more clearly observed in SiO2 gate dielectric devices. [•] HfSiON dielectric devices present time constant higher than SiO2 ones. [Copyright &y& Elsevier]

• This work presents experimental results of the series resistance variability in junctionless and inversion-mode nanowire transistors. • Due to series resistance, drain-current variability is larger than Y-function variability both in junctionless and inversion mode nanowires. • The influence of source-drain series resistance is higher on drain-current variability for junctionless than inversion mode, presenting an increase of up to 50% depending on the width and channel length. • Results suggest that series resistance variation impacts junctionless more than inversion mode nanowire transistors. This work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors. [ABSTRACT FROM AUTHOR]