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The effects of total ionizing dose (TID) on MOSFETs fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology are analyzed. TID causes positive-trapped charge to accumulate in transistor isolation regions [e.g., the buried oxide (BOX)], thereby generating negative TID-induced threshold-voltage shifts $\Delta V_{\mathrm {th}}$ that facilitate nMOSFET turn-on and inhibit pMOSFET turn-on. Back-gate biasing options in the technology can be used to offset the threshold-voltage shifts. Applying a bias to the back gates of MOSFETs in a conventional-well back-gate configuration mitigates TID-induced $\Delta V_{\mathrm {th}}$ in nMOSFETs (where a negative bias is applied to the P-well back-gate), while enhancing the same in pMOSFETs (where a positive bias is applied to the N-well back-gate). To mitigate and potentially reverse TID-induced $\Delta V_{\mathrm {th}}$ of both nMOSFETs and pMOSFETs simultaneously, a single back-gate bias can be applied to MOSFETs in a common isolated P-well back-gate configuration. 3-D technology computer-aided design (3-D TCAD) device simulation results of the 22-nm FD-SOI technology confirm the conventional-well circuit-level radiation response and support the effectiveness of using the common isolated P-well back-gate configuration for TID mitigation. These results justify the utility of dynamically tuning back-gate bias according to actively monitored TID-induced $\Delta V_{\mathrm {th}}$ feedback. [ABSTRACT FROM AUTHOR]

An on-chip measurement circuit that was specifically designed to capture the high-speed transient characteristics of photocurrent is employed to measure total-ionizing-dose (TID)-induced leakage from 10 keV X-rays. This circuit uses a photocurrent-controlled oscillator (PCO) to produce an analog frequency, which provides linearity comparable to traditional, off-chip methods of TID measurement. The circuit was fabricated in a sub-50 nm, fully depleted silicon-on-insulator (FD-SOI) technology. TID-induced leakage currents were measured using the circuit and results were compared to off-chip direct measurements from identical transistor arrays. Additionally, potential in situ applications of this circuit in conjunction with a TID-compensating back-gate biasing technique are explored. [ABSTRACT FROM AUTHOR]

A method is presented to enhance single-event transient (SET) measurements by overcoming a common experimental limitation of minimum measurable pulse widths. As technology scales, SETs decrease in width and measurement circuits fundamentally cannot capture every fast transient capable of causing an error. A method has been developed to overcome this limitation by using a latch as a feedback-assisted fast transient capture circuit. Single-event upset (SEU) data are combined with SET data to extend pulsewidth acuity such that pulses faster than the minimum measurable SET pulsewidth are extracted. The method has been applied for a 14-/16-nm bulk FinFET technology node and predictions for logic single-event cross section reveal the impact of fast transients on the radiation response of logic circuits. Results including the extracted fast transients represent upper bound SEU cross sections. For high linear energy transfer (LET) particle irradiation, accounting for fast transients using the developed method results in negligible variation in logic SE cross section. However, for low LET particle irradiation, the method results in an order of magnitude increase in logic SE cross section. [ABSTRACT FROM AUTHOR]

Single-event transient (SET) data for the 14-/16-nm bulk finFET technology generation are presented and analyzed for variations in threshold voltage and number of fins in the transistor. The heavy-ion experimental data over a range of supply voltage allows for a comparison of the impact of drive current on the SET response of each transistor variant. The results show that the transistor drive current is a key factor for determining SET pulsewidths and cross sections for high linear energy transfer particle irradiation. Transistor variant data that result in matching transistor drive current show an excellent match for SET pulsewidths and cross sections. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) irradiation affects the single-event (SE) vulnerability of electronics by changing transistor leakage currents and/or effective threshold voltages ($\text{V}_{T}$). Characterization of SE response of flip-flop (FF) designs in a 14-/16-nm bulk FinFET technology after TID exposure has been carried out with alpha particle irradiations. Results show that SE cross section (SECS) first increase with total dose and then start to decrease after certain dose levels. These transition dose levels for SECS trend depend on supply voltage and FF design due to competing mechanisms associated with n-hit and p-hit SE transient (SET) pulse-widths and feedback loop delay. Similar trends were observed for SET-induced logic errors at high-frequency operations after TID exposure. [ABSTRACT FROM AUTHOR]

In this paper, a variety of flip-flop (FF) designs fabricated in a commercial 28-nm Fully-Depleted Silicon on Insulator (FDSOI) technology are evaluated for their single-event upset performance with ions and pulsed laser experiments. These FF designs consist of unhardened DFF, hardened DFF with stacked transistors in the inverters, and the layout-optimized DFFs. These DFFs were exposed to alpha particles and heavy ions (HIs). None of the hardened DFFs exhibit any errors up to a Linear Energy Transfer (LET) of 50 MeV*cm2/mg under normal irradiation, and a layout-based hardened DFF started to see errors at a LET of 50 MeV*cm2/mg with the tilt angle of 600. The testing data substantiates effective SEU reduction of these hardened designs. Two-photon absorption (TPA) laser experiments were carried to test these DFF designs, and the results showed that pulsed laser may not be a valid tool to evaluate the FFs designed with nano-scale SOI stacked structures. This brings new challenges in laser hardness assurance for RHBD designs. [ABSTRACT FROM PUBLISHER]

A persistent loss-of-lock error was experimentally observed in a 20 nm charge-pump phase-locked loop (PLL). Through circuit modeling and simulation, the observed error was attributed to a non-recoverable off-state leakage increase resulted from two-photon absorption (TPA) laser-induced damage. The laser-induced damage is consistent with results from 28 nm bulk transistors. [ABSTRACT FROM PUBLISHER]

The ambipolar-diffusion-with-cutoff (ADC) model is extended to estimate the single-event-induced collected charge for multiple transistors for circuits simulation. The proposed improvement in the model includes both parasitic-bipolar and charge-sharing effects for a given technology. Simulation results indicate excellent agreement between the proposed model and published TCAD data for 130, 90, 65, and 40 nm technology nodes. A comparison between ADC and both rectangular parallelepiped (RPP) and integral rectangular parallelepiped (IRPP) models indicates a 2.7\times and 2.5\times lower error in estimating collected charge when compared with TCAD data. The ADC average error was estimated to be 7.1 fC and for the RPP and IRPP about 19.1 fC and 17.5 fC, respectively, across the technologies for particles with the linear energy transfer range from 1 - 30~\MeV-cm^2/\mg. [ABSTRACT FROM PUBLISHER]

Accurate estimation of single event upset rates for complex combinational logic circuits is extremely challenging due to the difficulties involved in calculation of different masking factors. This paper introduces the concept of an effective value of the window of vulnerability which is calculated experimentally for 28 nm bulk CMOS combinational logic circuits. Results suggest that the window of vulnerability for different input conditions of the same circuit are similar but that of different circuits could differ. The difference in gate type and topology is identified as the key reason for the differences in window of vulnerability. The window of vulnerability due to alpha particle irradiation for different circuits is between 30–60 ps which compares reasonably with SET pulse-width distributions reported in the past. The effective value of the window of vulnerability could be used to simplify logic error rate calculations. [ABSTRACT FROM AUTHOR]

A novel RHBD technique utilizing charge sharing to mitigate single-event voltage transients in differential circuits is demonstrated experimentally. Differential charge cancellation (DCC) layout leverages the inherent common-mode rejection of differential circuits to mitigate voltage transients induced by ion strikes. A simple layout variation transforms normally single-ended error signals into common-mode signals that are mitigated by the differential signal path. This layout change maintains the matching achieved via a standard common-centroid layout but incurs negligible area penalty. [ABSTRACT FROM AUTHOR]

High-speed communication systems typically employ a mix of signal types and circuit topologies in order to optimize efficient data propagation. Current-mode logic is the industry standard for high-speed CMOS circuit design due to the inherent speed of current steering. However, current-mode output voltages are not rail-to-rail and therefore require a conversion to a full-swing signal for downstream CMOS logic. This interface between current-mode and CMOS logic is found to be vulnerable to single-event effects. A radiation-hardened-by-design solution is proposed for such interfaces. [ABSTRACT FROM AUTHOR]

A novel radiation-hardened-by-design (RHBD) technique that utilizes charge sharing to mitigate single-event voltage transients is employed to harden bias circuits. Sensitive node active charge cancellation (SNACC) compensates for injected charge at critical nodes in analog and mixed-signal circuits by combining layout techniques to enhance charge sharing with additional current mirror circuitry. The SNACC technique is verified with a bootstrap current source using simulations in a 90-nm CMOS process. Reductions of approximately 66% in transient amplitude and 62% in transient duration are observed for 60-degree single-event strikes with an LET of 40 MeV*cm^2/mg. [ABSTRACT FROM PUBLISHER]

Neutron- and proton-induced single-event upset cross sections of D- and DICE-Flip/Flops are analyzed for designs implemented in a 40 nm bulk technology node. Neutron and proton testing of the flip/flops show only a 30%–50% difference between D- and DICE-Flip/Flop error rates and cross sections. Simulations are used to show that charge sharing is the primary cause for the similar failures-in-time (FIT) rates. Such small improvement in the single-event performance of the DICE implementation over standard D-Flip/Flop designs may warrant careful consideration for the use of DICE designs in 40 nm bulk technologies and beyond. [ABSTRACT FROM AUTHOR]

Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal and angular incidence for designs where the pMOS transistors are in common n-wells or isolated in separate n-wells. Experimental data and simulations show that pulse quenching is more prevalent in the common n-well design than the separate n-well design, leading to significantly reduced SET pulsewidths and SET cross-section in the common n-well design. [ABSTRACT FROM AUTHOR]

Single event charge collection mechanisms in 90 nm triple-well NMOS devices are explained and compared with those of dual-well devices. The primary factors affecting the single event pulse width in triple-well NMOSFETs are the separation of deposited charge due to the n-well, potential rise in the p-well followed by the injection of electrons into the p-well by the source, and removal of holes by the p-well contact. Design parameters of p-wells, such as contact area, doping depth and placement, are varied to reduce single event pulse widths. Pulse width decreases as the area of the p-well contacts increases, the p-well contacts become deeper, and the p-well contacts are placed more frequently. Increasing the p-well-n-well junction depth also causes the full width half rail (FWHR) pulse width to decrease. [ABSTRACT FROM PUBLISHER]

In deep sub-micron technologies, scaling and closely packed interconnects magnify crosstalk effects causing a Single Event Transient (SET) pulse to affect multiple logic paths instead of the single hit path. Such events increase the vulnerable area and the SET susceptibility of complementary metal-oxide-semiconductor (CMOS) circuits. This paper analyses factors affecting the crosstalk pulse due to an Single Event Upset (SEU) in digital logic circuits for advanced technologies. Simulation results obtained substantiate that the effects of Single Event (SE) crosstalk increase as devices scale down, as the amount of Charge deposited to cause an upset increases, and as the interconnect length increases. [ABSTRACT FROM AUTHOR]