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This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation. [ABSTRACT FROM AUTHOR]

• The position of interface traps along the channel has been evaluated in Junciotnless transistors. • The effect of traps on the low frequency noise depends on the surface potential. • In JNTs, the surface potential varies along the channel with drain/gate biases. • JNTs low frequency noise is more sensitive to trap centers close to the source side. • The lower surface potential close to the source enables traps to be occupied for a longer time. Differently from inversion mode MOS transistors, Junctionless Nanowires surface potential presents a strong dependence on the gate and drain biases, when the devices are biased in partial depletion. For that reason, the position of interface trap centers along the channel could have a significant influence on the electrical characteristics of the devices. Therefore, this work has evaluated how the position of a single interface trap along the channel can affect the low-frequency noise response of Junctionless Nanowire Transistors. It has been shown that the trap centers closer to the source side of the devices are more likely to degrade the noise characteristics than those located closer to the drain, which has been attributed to the lower surface potential in this region, enabling traps to be at the same state (occupied or empty) for a longer time interval. [ABSTRACT FROM AUTHOR]

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature. [ABSTRACT FROM AUTHOR]

The improvement of subthreshold slope due to impact ionization is compared between “standard” inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope. [ABSTRACT FROM AUTHOR]

The electric field perpendicular to the current flow is found to be significantly lower in junctionless transistors than in regular inversion-mode or accumulation-mode field-effect transistors. Since inversion channel mobility in metal-oxide-semionductor transistors is reduced by this electric field, the low field in junctionless transistor may give them an advantage in terms of current drive for nanometer-scale complementary metal-oxide semiconductor applications. This observation still applies when quantum confinement is present. [ABSTRACT FROM AUTHOR]

• Analysis of the thermal cross-coupling effect in advanced UTBB transistors through 3D numerical simulations. • Study was performed through 3D numerical simulations validated with experimental data from the literature. • It could be observed that the temperature rise due to a self-heated device can affect the performance of a neighbor one according to the distance between them and to the its bias conditions. • By varying the distance between the devices from 1 μm to 50 nm, one can observe degradations in threshold voltage, subthreshold swing and in the maximum transconductance as well an increase in the thermal resistance of a neighbor device. • All thermal coupling effects are more pronounced for distances below 400 nm. The focus of this work is to perform a first-time analysis of the thermal cross-coupling of a device on a neighbor one in advanced UTBB transistors through 3D numerical simulations, validated with experimental data from the literature. In this work, it could be observed that the temperature rise due to a self-heated device can affect the performance of a neighbor one according to the distance between them and to the bias conditions. By varying the distance of the devices from 1 µm to 50 nm, it is shown an influence of the temperature rise due to a self-heated device in threshold voltage, subthreshold swing and in the maximum transconductance as well an increase in the thermal resistance of a neighbor device. [ABSTRACT FROM AUTHOR]

[Display omitted] • HEMTs are very attractive candidates for 5G applications. • Low frequency noise were performed on AlGaN/GaN HEMTs with different channel orientation. • LF noise is an important tool for studying reliability of GaN-based HEMTs. • Flicker noise is due to trapping in the AlGaN barrier of High-Electron-Mobility Transistors. • Noise Power Spectral Density of AlGaN/GaN High-Electron-Mobility Transistors. The performance of AlGaN/GaN High-Electron Mobility Transistors (HEMTs) fabricated on 〈1 1 1〉 silicon substrates has been experimentally investigated, aiming to verify the effect of different channel orientations on the main electrical parameters, such as drain current (I D), threshold voltage, transconductance (g m), and Drain-Induced Barrier Lowering (DIBL). Moreover, the noise Power Spectral Density (PSD) with different channel orientations has also been characterized in linear operation. No noticeable differences on the electrical and noise PSD characteristics have been observed between the GaN channel orientations (0°, 90° and 45°). [ABSTRACT FROM AUTHOR]

• Charge Pumping in JNTs is analyzed through experimental data and numerical simulations. • The Charge Pumping current increases linearly with the trap density. • The dependence allows for the proposition of an interface traps extraction method. • The comparison between experimental and simulated results shows the applicability of the method. This paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (N it). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for N it > 1 × 1011 cm−2. [ABSTRACT FROM AUTHOR]

• NBTI in JNTs is analyzed through experimental data and numerical simulations. • The impacts of the temperature and the trap density on NBTI are evaluated. • The increase in the oxygen precursors density leads to the saturation in the NBTI. • Temperature rise increases the degradation of threshold voltage due to NBTI. This paper deals with the behavior of degradation by NBTI effect in pMOS junctionless nanowire transistors (JNTs). The analysis has been performed through measurements followed by 3D numerical simulations and has shown that the increase in the oxygen precursors density close to the interface leads to the reduction of the saturation in the NBTI effect when the devices operate in partial depletion regime. Such effect can be associated to the change in the flatband voltage to more negative values as well as the threshold voltage with the increase in the precursor density. In the sequence of the work, it was shown that, as the operation temperature rises, there is an increase in the degradation of the threshold voltage due to NBTI, which is more pronounced for larger gate voltages. It was concluded that this effect could be associated to the increase in the recombination rate with the temperature, which enables the occupation of a larger amount of traps. [ABSTRACT FROM AUTHOR]