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Bottom-gated n-channel thin-film transistors (TFTs) were fabricated, using as channel material hydrogenated amorphous silicon (a-Si:H)/nanocrystalline silicon (nc-Si:H) bilayers, deposited at 230 °C by plasma-enhanced chemical vapor deposition, and SiN x as gate dielectric. The stability of these devices is investigated under three bias stress conditions: (i) gate bias stress ( V G = 25 V, V D = 0), (ii) on-state bias stress ( V G = 25 V, V D = 20 V) and (iii) off-state bias stress ( V G = −25 V, V D = 20 V). It is found that the TFT degradation mechanisms are strongly dependent on the bias stress conditions, involving generation of deep and tail states in the active area of the channel material, carrier injection (electrons or holes) within the gate insulator and generation of donor trap states at the gate insulator/channel interface. The common features and the differences observed in the degradation behaviour under the different bias stress conditions are discussed.

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated on amorphous silicon (a-Si)/nanocrystalline silicon (nc-Si) bilayers, deposited at 230 °C by plasma-enhanced chemical vapour deposition. The impact of the channel length on the electrical and low-frequency noise characteristics of the TFTs is investigated. The results show that the 1/ f noise can be interpreted in terms of carrier number fluctuations, except the long channel devices where the 1/ f noise is interpreted in terms of the Hooge’s mobility fluctuations model at low drain currents. The gate insulator trap density has been evaluated, demonstrating that the nc-Si extended underneath the n + drain contact area contributes to the measured noise.

The effect of the channel width dimension on the electrical characteristics of amorphous/nanocrystalline silicon bilayer thin-film transistors (TFTs) is investigated. For comparison, nanocrystalline silicon monolayer TFTs are also studied. The experimental results show that the leakage current is decreased and the back-channel conduction is suppressed in bilayer channel devices. The overall results demonstrate that the performance of bilayer TFTs is enhanced with decreasing the channel width, which is attributed to the corner effect

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/f noise measurements.

The effects of hot carriers on the characteristics of intrinsic offset gated n-channel polysilicon thin-film transistors (TFTs), with channel length L = 10 μm, have been studied in relation to the offset length Δ L . From the evolution of the transfer and output characteristics during stress, the degree of the device degradation is deduced. In devices with Δ L = 0.5 and 1 μm, the on-state current is substantially reduced, whereas the subthreshold region remains almost unaffected. In devices with Δ L = 2 μm, the transfer characteristics are shifted first positively after short stressing time and then negatively, the on-state current is still substantially reduced and well-defined kink is formed in the subthreshold region. The device degradation is found to become more pronounced as the gate offset length increases. A model explaining the post-stress performance of offset gated devices is presented.

Hot-carrier effects in n-channel polysilicon thin-film transistors (TFTs), with channel width W=10 /spl mu/m and length L=10 /spl mu/m, are investigated. An analytical model predicting the post-stress performance is presented, by treating the channel of the stressed device as a series combination of a damaged region extended over a length /spl Delta/L beside the drain and a region of length L-/spl Delta/L having the properties of the unstressed device. The apparent channel mobility is derived considering that the mobility of the damaged region is described with the mobility of amorphous Si TFTs, whereas the mobility of the undamaged region is described with the mobility of the virgin device. From the evolution of the static characteristics during stress, the properties of the damaged region with stress time are investigated.

The low-frequency noise in offset-gated polysilicon thin-film transistors (TFTs) is investigated. It is shown that the spectral density of the drain current fluctuations can be interpreted in terms of the carrier number fluctuations, considering the extrinsic transconductance of the device. The relation between the extrinsic transconductance of the offset-gated polysilicon TFT and the intrinsic transconductance of the self-aligned device was found to depend mainly on the polysilicon layer quality. An effective density of traps N/sub teff//sup */ was extracted which reflects the contribution to the noise of the active and passive channel. The extracted noise index N/sub teff//sup */ is lower when the polysilicon layer quality is improved (lower in-grain defect density).

A simple method to determine the Interface and bulk density of states in polycrystalline silicon thin-film transistors is presented. The energy distribution of the interface trap density has been extracted from analysis of the transfer characteristics in the subthreshold region of operation. Using the obtained interface state distribution, the energy distribution of the bulk traps has been determined by fitting the surface potential at each gate voltage with an analytical theoretical model. Both interface and bulk traps were found to consist of deep states with constant density near the mid-gap and band-tails with density increasing exponentially with the energy when the trap energy approaches the conduction band-edge.

The effects of hydrogenation on the performance and stability under electrical stress of p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) are investigated. The hydrogenation is performed in pure H 2 plasma or in plasma of 4% H 2 diluted in He gas. Devices hydrogenated in plasma of H 2 /He exhibit lower subthreshold swing with better uniformity and lower leakage current, which indicate passivation of mid-gap trap states arising from dangling bonds at the grain boundaries. Hot-carrier experiments demonstrate that the stability of p-channel TFTs is improved as the hydrogenation becomes more efficient due to the effective removal of donor-type trap states at the grain boundaries.

The stability of p-channel polycrystalline silicon thin-film transistors, hydrogenated in pure hydrogen plasma, is investigated. The hot-carrier induced degradation mechanisms are studied for operation in the saturation region and different gate bias voltages V g . During on-state stress at high | V g |, first an effective shortening of the channel length is observed due to trapping of hot electrons. As the stress proceeds further, donor-type interface states are generated, resulting in an increase of the electric field near the drain due to built-up of positive charge in these states by trapping of hot holes. During on-state stress at low | V g |, the transistor parameters are improved due to further passivation of grain boundary deep and tail states, caused by dissociation of hydrogen molecules by hot electrons near the drain region. During off-state stress, hot electrons are injected in the gate oxide near the drain causing an effective shortening of the channel length and a reduction of the minimum leakage current.

The effects of gamma-ray irradiation on the performance of polycrystalline silicon thin-film transistors are investigated. After irradiation, the threshold voltage of the TFTs is shifted negatively and well-defined kinks are formed in the subthreshold regions of the transfer characteristics, explained by the turn-on of back channel and sidewall leakage current paths. In the non-irradiated device, the leakage current I L is controlled by the reverse biased drain junction, while after irradiation I L is limited by the intrinsic resistance of the polysilicon material itself.

The effect of the SiO2/polycrystalline silicon (polysilicon) interface roughness on the stability of n-channel large grain polysilicon thin-film transistors (TFTs) is investigated. The positive gate voltage of 20 V is used in the bias stress experiments, with the source and drain grounded. It is shown that the current through the gate oxide and the stability of the TFT are directly related to the importance of the interface roughness. The evolution of the TFT parameters with stress duration indicates that the turn-on voltage Von and the subthreshold swing voltage S are degraded due to the generation of dangling bond midgap states, while the leakage current IL and the maximum transconductance Gm are degraded due to the generation of strain-bond tail states. Moreover, the parameters Von and IL are found to degrade faster than the parameters S and Gm, respectively, due to electron trapping in the gate oxide.

The effects of low gate voltage |V/sub g/| stress (V/sub g/=-2.5 V, V/sub d/=-12 V) and high gate voltage |V/sub g/| stress (V/sub g/=V/sub d/=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V/sub g/| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V/sub g/| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds.

Large-grain excimer laser-annealed polysilicon TFTs are studied. Due to the large grain size of the polysilicon film (about 2.5 /spl mu/m), we propose a model for the on-current (above threshold voltage) taking into account the number of grain boundaries within the channel. This linear-region model considers grain and grain boundaries as two noncorrelated regions within the channel of a polysilicon TFT. The trap density at the grain boundaries and the device parameters involved in this model are determined by fitting the experimental transfer characteristic in the linear regime. Moreover, we show that the proposed model provides reliable results within a temperature range from 150 K to 300 K. Finally, it serves to optimize the energy density of laser annealing and to make predictions about polysilicon TFT technology, since TFTs performances versus grain size plots can be obtained.

The leakage current I L of offset gate n- and p-channel excimer laser annealed polycrystalline silicon thin-film transistors (polysilicon TFTs) has been investigated experimentally. It has been found that the leakage current is almost independent of the polysilicon layer quality. In n-type polysilicon TFTs, I L arises from band-to-band tunneling due to extension of the drain junction to the gate end by diffusion of phosphorus ions from the drain contact within the offset region. In p-channel TFTs, I L first increases rapidly and then saturates at high drain voltages. This leakage current behavior is explained qualitatively by a model based on the change of the effective offset length, caused by the applied drain voltage on the positive ions of boron, diffused from the drain contact within the offset region.

Hot-carrier effects have been investigated in n-channel thin-film transistors fabricated on large grain polysilicon films. The bias-stress conditions for maximum device degradation have been determined by photon emission measurements. Under these bias-stress conditions, devices with identical transfer characteristics before stress, are either stable or exhibit strong degradation with reduced field effect mobility. We propose that the different degradation behavior is related with the quality of the grain boundaries and their position in the channel with respect to the drain junction. The results indicate that when a grain boundary is located closer to the drain region, it becomes more prone to degradation by the hot carriers generated in the high field region of the drain junction. Numerical simulations suggest that the device degradation is due to an increase of the grain boundary band tail states. In addition to this mechanism, the existence of a critical path for the current flow from source to drain has been proposed to explain the observed different degradation behavior of similar devices.

The influence of the material quality and thickness on the leakage current of polycrystalline silicon thin-film transistors is investigated. Improvement of the polycrystalline silicon layer (i.e., increase of the average grain size or decrease of the intragrain defect density) reduces only the leakage current at low electric fields in the drain region. At high electric fields, the leakage current is independent of the film quality and thickness due to the fundamental nature of the leakage current mechanisms. The experimental data indicate that Poole–Frenkel enhanced emission from traps at low electric fields and band-to-band tunneling at high electric fields are the dominant conduction mechanisms of the leakage current.

An analytical model of the above-threshold voltage transconductance of large grain polycrystalline silicon thin-film transistors (TFTs) is presented. The devices were fabricated on 50 nm thick polysilicon films prepared by combined solid phase crystallization (SPC) of amorphous silicon and excimer laser annealing (ELA) at various energy densities. The structural properties of the polysilicon films were investigated by transmission electron microscopy. The transconductance model includes exponential band tails for the grain boundary traps, the eAect of polysilicon/SiO2 interface scattering and the channel depth variation with gate voltage. Based on this model, the transconductance dependence on gate bias is investigated in devices with diAerent interface roughness. It is found that at low gate voltages, the transconductance increases with the gate bias due to the grain boundary barrier lowering eAect. The observed decrease of the transconductance at high gate biases is mainly related to the size of the interface roughness. ” 2000 Elsevier Science Ltd. All rights reserved.

Thin-film transistors (TFTs), fabricated on solid-phase-crystallized polycrystalline silicon (polysilicon) films subjected to laser annealing, were studied. For the resulting large-grain polysilicon TFTs, a model is proposed that takes into account two well-distinguished regions within the channel of the transistor: the intra-grain region and the grain boundaries. By using this model, we found that the extracted on-voltage is mainly grain-boundary dependent while the maximum transconductance is mostly intra-grain defect dependent. Moreover, with the aid of this model, the physics of the large-grain polysilicon TFTs becomes more evident and an optimal laser energy density was found for best device performance.

Experimental results of low frequency noise in polycrystalline silicon thin-film transistors (polysilicon TFTs) with varying gate dimensions (constant gate width W and varying gate length L) are presented. The power spectral density of the drain current fluctuations SI was found to depend linearly on the inverse of the effective gate area Ag,eff which is related to the gate area W×L and the number of grains present within the transistor channel. This result implies localization of the low frequency noise sources on the gate oxide-polysilicon interface and on the grain boundaries. The 1/Ag,eff scaling law must be taken into account for correct estimation of trap densities in polysilicon TFTs.

The structural and electrical properties of excimer laser annealed polycrystalline silicon thin-film transistors (polysilicon TFTs) are investigated in relation to the laser energy density. The devices were fabricated on 50 nm thick polysilicon films prepared by excimer laser crystallization (ELA) of amorphous silicon or by a combined solid phase crystallization (SPC) and ELA process. The structural properties of the polysilicon films have been investigated by transmission electron microscopy analysis. The effective density of states distributions in the polysilicon films and in the oxide traps near the oxide/polysilicon interface have been determined from low frequency noise measurements. The TFT performance parameters are compared with respect to their correlation with the structural properties of the polysilicon films and their electrically active defects, the basic variables being the starting material (amorphous silicon or SPC polysilicon) and the laser energy density.

A study on hot-carrier phenomena in high temperature processed undoped and hydrogenated n-channel polysilicon thin film transistors (TFTs) is presented. First, stress conditions are determined by photon emission measurements during impact ionization condition. Next four stress regimes are performed. We distinguish two modes of stress conditions according to drain voltage during stressing: High drain voltage stress (HDVS) and low drain voltage stress (LDVS). Each of these modes gives different results when applied to our TFTs. During HDVS condition, two regimes are observed. First, hot-hole injection into the oxide occurs synchronically with interface-state generation. At a second stage, this mechanism saturates and electron injection through the polySi–SiO2 barrier takes place with less interface states generated. In contrast, during LDVS conditions no saturation of interface-state generation is observed and two regimes of transconductance degradation appear. The distribution in the gap of the stress-induced interface states is calculated by a known method. Finally, on- and off-state current stress was studied. Off-stressing affects mainly the gate oxide and is not accompanied by measurable impact ionization phenomena and thus no considerable interface-state generation.

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO2-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.

Polycrystalline silicon thin-film transistor (polysilicon TFT's) characteristics are evaluated by using a low-frequency noise technique. The drain current fluctuation caused by trapping and detrapping processes at the grain boundary traps is measured as the current spectral density. Therefore, the properties of the grain boundary traps can be directly evaluated by this technique. The experimental data show a transition from 1/f behavior to a Lorentzian noise. The 1/f noise is explained with an existing model developed for monocrystalline silicon based on fluctuations of the inversion charge near the silicon-oxide interface. The Lorentzian spectrum is explained by fluctuations of the grain boundary interface charge with a model based on a Gaussian distribution of the potential barriers over the grain boundary plane. Quantitative analysis of the 1/f noise and the Lorentzian noise yield the oxide trap density and the energy distribution of the grain boundary traps within the forbidden gap.

The accurate knowledge of the effective channel length in a polysilicon thin film transistor (TFT) is of great importance. The reduction ΔL of the channel length is due to lateral diffusion from the source and drain contacts into the gate region. The usual method for determining ΔL is based on plotting the straight line 1/ID versus length mask Lm in the linear region and extrapolating the straight line to intersect the x-axis. We show that this method is approximate and leads to an underestimation of the reduction channel length due to the existence of the access resistance. We propose an alternative method based on the saturation current IDsat using the 1/IDsat versus Lm plots. We show that this method is more accurate especially when the access resistance of the device is important. The extracted parameters ΔL for n- and p-channel polysilicon TFTs are more compatible with the device performance.

The static bias-stress-induced degradation of hydrogenated amorphous/nanocrystalline silicon bilayer bottom-gate thin-film transistors is investigated by monitoring the turn-on voltage (V on) and on-state current (I on) in the linear region of operation. Devices of constant channel length 10 mum and channel width varying from 3 to 400 mum are compared. The experimental results demonstrate that the device degradation is channel-width dependent. In wide channel devices, substantial degradation of V on is observed, attributed to electron injection into the gate dielectric, followed by I on reduction due to carrier scattering by the stress-induced gate insulator trapped charge. With shrinking the channel width down to 3 mum, the device stability is substantially improved due to the possible reduction of the electron thermal velocity during stress or due to the gate insulator quality uniformity over small dimensions.

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.

The performance of n- and p-channel high-temperature processed polycrystalline silicon thin-film transistors (polysilicon TFTs) has been investigated by conduction and low-frequency noise measurements. The polysilicon films were doped by boron or phosphorus ion implantation at concentrations of about 6×1016 and 3×1017 cm−3, respectively, and hydrogenated by ion implantation of hydrogen. Undoped and nonhydrogenated polysilicon films were also used for comparison. Channel length reduction due to dopant diffusion from the source and drain contacts was found to affect the transistor conduction and its associated noise. Low-frequency noise measurements indicate that the noise power spectral density of the drain current is mainly due to carrier number with correlated mobility fluctuation. The experimental data reveal the presence of exponential band tails in both n- and p-channel hydrogenated undoped polysilicon TFTs. In nonhydrogenated boron doped n-channel devices, high density of band tails and deep levels a...

The off-state current in n- and p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) is investigated systematically by conduction measurements at various temperatures and low-frequency noise measurements at room temperature. It is demonstrated that the leakage current is controlled by the reverse biased drain junction. The main conduction mechanisms are due to thermal generation at low electric fields and Poole–Frenkel accompanied by thermionic filed emission at high electric fields. The leakage current is correlated with the traps present in the polysilicon bulk and at the gate oxide/polysilicon interface which are estimated from the on-state current activation energy data. Analysis of the leakage current noise spectral density confirms that deep levels with uniform energy distribution in the silicon band gap are the main factors in determining the leakage current. The density of deep levels determined from noise analysis is in agreement with the value obtained from conductance acti...

An improved analysis of the low frequency noise in polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented. The analysis takes into account an exponential energy distribution for the density of states and the flat-band voltage fluctuations for the origin of the drain current noise. Analysis of the drain current spectral density enables the characterization of the gate oxide/polysilicon interface and the active polysilicon layer quality.

Low-frequency noise measurements have been carried out in polycrystalline silicon thin-film transistors (polysilicon TFTs) with different interface roughnesses. Independently of the interface roughness, the drain current noise can be ascribed to carrier number fluctuations. In devices with a large interface roughness, a noise overshoot is observed at drain currents around 3μA, attributed to generation-recombination (g-r) centers. The traps responsible for the g-r noise are located within the gate oxide near the interface, created by the carriers injected into the gate oxide by the field enhanced at the rough polysilicon∕SiO2 interface. The g-r noise corresponds to a single trap level of density 3.8×1017cm−3 and time constant 20ms. Devices exhibiting g-r noise degrade more rapidly during electrical stress.

Results on the impact of hot-carrier effects on the transfer and low-frequency noise characteristics of n-channel poly-crystalline silicon thin-film transistors (polysilicon TFTs) are presented. After stressing at the condition of maximum substrate current, the experimental data show that TFTs suffer from substantial on-current reduction. Through numerical simulation, it is shown that the stress-induced degradation increases the density of the band tail traps in a region extending 200 nm from the drain and the series resistance on the drain side. It is found that the origin of the noise is reverted from carrier number fluctuation for the unstressed to the mobility fluctuation for the stressed device.

Hot-carrier effects in offset gated n-channel polycrystalline silicon thin-film transistors of channel length L=10 μm and intrinsic offset lengths ΔL=0.5 and 1 μm are investigated. The gate- and drain-bias conditions for maximum device degradation were determined from substrate current measurements. The experimental data show that hot-carrier stress provokes an anomalous threshold voltage and on-state current degradation, exhibiting a “staircase-like” degradation with stress time. These results lead to the conclusion that, at the initial stages of stress, a small offset region from the drain end is damaged due to charging of the grain boundaries. As the stress proceeds further and the grain boundary traps are filled with electrons generated by impact ionization, the damage is transferred to the neighboring offset region, resulting in a staircase-like degradation of the device parameters with stress time.

A model for the low frequency noise of polycrystalline silicon thin film transistors (polysilicon TFTs) is proposed. The model takes into account fluctuations of the grain boundary potential barrier induced by those of the grain boundary interface charge and fluctuations of carriers due to trapping in oxide traps located close to the interface. Using the proposed model, it is demonstrated that both grain boundary and oxide traps can be determined in polysilicon TFTs from noise measurements.

Statistical analysis was performed to investigate the performance and reliability of hydrogenated polysilicon thin-film transistors (TFTs) in relation to the hydrogenation process. The hydrogenation was performed in pure H/sub 2/ plasma and in plasma of 4% H/sub 2/ diluted in Ar or He gas. TFTs hydrogenated in H/sub 2//Ar or H/sub 2//He plasma have lower on-voltage and better uniformity compared to the nonhydrogenated devices due to passivation of grain boundary dangling bonds. Hot-carrier experiments demonstrate that electron trapping is the dominant mechanism at the early stages of the degradation process and generation of interface and grain boundary traps as the stress proceeds further. The overall results indicate that devices hydrogenated in H/sub 2//He plasma are the most reliable in terms of uniformity and hot-carrier stress.

In this letter, we present experimental data showing that hot-carrier stress in laser annealed polycrystalline silicon thin-film transistors provokes an anomalous turn-on voltage variation. Although under various hot-carrier stress intensities the maximum transconductance degradation shows the same power-time dependent law, turn-on voltage can exhibit different behaviors. This observation lead to the conclusion that turn-on voltage depends on two different degradation mechanisms: injection of hot carriers into the gate oxide and degradation of grain boundaries. We show that these two mechanisms may be distinguished since they obey different power-time dependent laws as a function of stress duration.

Hydrogenation effects in excimer laser annealed polysilicon thin-film transistors (TFTs) were studied. Hydrogen plasma formed from hydrogen diluted with Ar or He was used in order to passivate defects at the polysilicon/silicon oxide interface, as well as in the polysilicon material. It was found that, after hydrogenation, no more than a 10% increase in the carrier mobility is attained, accompanied by a threshold-voltage decrease, due to passivation of deep states at the polysilicon/silicon oxide interface and at the grain boundaries. However, the most important feature of hydrogenated devices is the improvement in the dispersion of their transfer characteristics. In addition, hot-carrier stress experiments showed that optimization of the type of dilution gas (Ar or He) and the relative concentration of hydrogen can be carried out in order to improve the device reliability.

Based on experimental studies of n-channel excimer-laser-annealed polycrystalline silicon thin-film transistors with gate ratio width/length varying from 0.5 to 2.5, we propose a reliable method to determine the threshold voltage Vt from linear extrapolation of the transconductance to zero. The results reveal that the determined values of Vt are independent of the device geometry and the applied drain voltage in the linear region, in contrast with the drain current linear extrapolation method. The values of Vt are correlated with the density of the total trap states derived from the subthreshold gate swing voltage.

The relationship between low-frequency drain current noise spectral density SI and grain-boundary potential barrier height Vb is investigated in high-temperature-processed polycrystalline silicon thin-film transistors. It is demonstrated that a general empirical relationship exists between SI and Vb indicating that the noise sources are located at the grain boundaries. The implications of the obtained relationship between SI and Vb from the practical viewpoint are discussed.

Thin-film transistors, fabricated on polycrystalline silicon films prepared by combined solid phase crystallization of amorphous silicon and excimer laser annealing processes, have been investigated by electrical and low frequency noise measurements in relation to the active layer thickness and the laser energy density. The device performance is improved with increasing the laser energy density until a critical value where the film is completely melted. By decreasing the active layer thickness from 50 to 25 nm, although the subthreshold characteristics are improved, the electron mobility and the threshold voltage are degraded. The noise data indicate that the degradation is related to electron trapping in both gate and substrate oxide interface traps.

The photon emission induced by the drain avalanche in polycrystalline silicon thin-film transistors (polysilicon TFTs) has been studied in wide drain and gate voltage ranges. As the photon emission phenomenon is closely related to hot-carrier effects, the gate and drain bias conditions for maximum device degradation have been determined from measurements of the emitted light intensity. In n-channel polysilicon TFTs, the effects of bias stressing at the maximum light emission are related to hot-hole trapping into the gate oxide near the drain and to formation of acceptor-like interface states consisted of midgap states and band tails.

Polycrystalline silicon thin-film transistors show a 1/fγ (with γ

The aim of our investigation is to determine the bulk and interface density of states in excimer laser annealed polycrystalline silicon thin film transistors (polysilicon TFTs). The exponential energy distribution of the band tail states in the bulk of the polysilicon layer is obtained from analysis of the space charge limited current in n + –i–n + structures. The density of traps at the gate oxide/polysilicon interface and the slope of the exponential band tail states in a thin layer adjacent to the channel/gate oxide interface are extracted from low-frequency noise measurements. The experimental results indicate that the degree of disorder is improved in the upper part of the polysilicon layer due to its columnar growth.

The drain leakage current in n-channel bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors is investigated systematically by conduction and low-frequency noise measurements. The presented results indicate that the leakage current, controlled by the reverse biased drain junction, is due to Poole-Frenkel emission at low electric fields and band-to-band tunneling at large electric fields. The leakage current is correlated with single-energy traps and deep grain boundary trap levels with a uniform energy distribution in the band gap of the nc-Si. Analysis of the leakage current noise spectra indicates that the grain boundary trap density of 8.5 times 1012 cm -2 in the upper part of the nc-Si film is reduced to 2.1 times 1012 cm-2 in the lower part of the film, which is attributed to a contamination of the nc-Si bulk by oxygen

A simple analytical expression for the above threshold voltage drain current is derived in nanocrystalline silicon thin-film transistors (TFTs), based on an exponential energy distribution of band tail states. When the characteristic temperature distribution of the band tails is equal to 1.5 times the lattice temperature, the derived expression leads to the basic “quadratic” metal-oxide-semiconductor current expression. By including the impact ionization effect and using the same trap distribution parameters, the model describes adequately the output characteristics of TFTs with different channel dimensions, making the proposed model suitable for the design of circuits with nc-Si TFTs.

A simple current-voltage model for polysilicon thin-film transistors (TFTs) is proposed, including the sixth-order polynomial function coefficients fitted to the effective mobility versus gate voltage data, the channel length modulation and the impact ionization effect. The model possesses continuity of current in the transfer characteristics from weak to strong inversion and in the output characteristics throughout the linear and saturation regions of operation. It has been applied in a number of long and short channel TFTs and the statistical distributions of the model parameters involved have been derived. The new model was adapted in the simulation program AIM-SPICE, with the extracted parameters used as input parameters of the new polysilicon TFT model

The origin of the leakage current in low-pressure chemically vapor deposited polycrystalline silicon (polysilicon) thin-film transistors is investigated by low-frequency noise measurements. The leakage current depends on the structure of the polysilicon layer. When the grain size is relatively large (about 120 nm), the noise spectra show a pure 1/f behavior caused by carrier fluctuation within the space charge region of the drain junction. For smaller grain size (about 50 nm), the observed 1/f1.5 spectra are attributed to thermal noise of the bulk polysilicon film.

The effects of hot carriers on the transfer characteristics of self-aligned and offset-gated polysilicon thin-film transistors (TFTs), with channel length L = 10 μm and offset length ΔL = 2 μm, are investigated. In the self-aligned device, the on-state current is substantially reduced, whereas the subthreshold slope remains almost unaffected. In the offset gated device, the transfer characteristic is shifted first positively and then negatively, the on-state current is still substantially reduced and well-defined kinks are formed in the subthreshold region. The device degradation is found to become more pronounced in the offset gated device. A model explaining the post-stress performance of the offset-gated device is presented.

Hot-carrier effects are investigated in offset gated polysilicon thin-film transistors of channel length L = 10 /spl mu/m and offset length /spl Delta/L = 0.5 and 1 /spl mu/m, and compared with those of self-aligned devices. The gate and drain bias conditions for maximum device degradation were determined from substrate current measurements. In offset gated devices, the experimental data show that the threshold voltage and the on-state current degrade exhibiting a "staircase-like" behavior with stress time. The results are explained in terms of grain boundary trap filling, with electrons generated by impact ionization in successive small offset regions from the drain end.