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In this study, we demonstrate multimemory functions of anAg/SiOx/n+-Si device, including nonvolatile (NV) write-once-read-many-times (WORM), NV bipolar, NV unipolar, and volatile resistive switching (RS) characteristics. The SiOx layer is grown using a dry oxidation process. Different RS features are obtained by modulating the compliance current during device operation. The resistance switch from the OFF to ON state, corresponding to a set process, is observed in the positive voltage region, which indicates that the Ag cations are responsible for the RS process. When the Ag/SiOx/n+-Si memory switches to the ON state, an Ag conductive bridge (CB) in the SiOx layer is indeed observed under transmission electron microscopy (TEM) examination. A CB-based model is used to explain the different RS behaviors of the Ag/SiOx/n+-Si resistive memory. [ABSTRACT FROM AUTHOR]

In this letter, a high-performance dual-function device fabricated using one single SiO2 resistive switching layer is demonstrated. The SiO2 layer is sandwiched between Ag and n+-Si to form an Ag/SiO2/n+-Si dual-function device with memory and selector features. As a memory device, it shows a high memory window of 107, and can continually operate over 104 cycles. Nonvolatility and stability are examined using a retention and a stress test for 104 s. Measurement at 85°C is performed to further confirm the reliability of the memory feature. As a selector, the device shows an extremely low leakage current of 0.1 pA, a high selectivity of 106, and a low turn-on energy consumption of 0.93 pJ. Moreover, it has steep turn-on and turn-off switching slopes of 1.7 mV/decade and 0.7 mV/decade. The reliability of the selector feature is confirmed by pulse operations and a stress test. [ABSTRACT FROM AUTHOR]

Write-once-read-many (WORM) memory effect is reported in the 19.68 Tex, 80:20 ratio polyethylene terephthalate (PET)-metal fiber spun electroconductive yarn. The yarn sample displayed a typical WORM memory behavior having electrical bistability with an OFF/ ON resistance ratio up to $10^{{9}}$ and a long retention period. As the polyester fibers transform from amorphous (resistive state) to semicrystalline (conductive state) upon the application of bias voltage, the charge conduction changes from electronic to ionic, above the glass transition temperature. Furthermore, ${I}-{V}$ curves were fit to explain the charge carrier transport mechanisms in the WORM behavior. Additionally, upon intentional mechanical perturbation, the sample could reset to its native high-resistive state (the phenomenon is termed as Reset WORM or ReWORM), ready for another WORM storage cycle. [ABSTRACT FROM AUTHOR]

An aluminum oxynitride (AlOx:N) resistive memory with a large ON/OFF ratio of 106 at a low read voltage of 0.5 V is proposed. The AlOx:N resistive switching (RS) layer is fabricated using a two-stage thermal oxynitridation process of an evaporated Al film. The Al/AlOx: N/n+-Si device shows write-once–read-many-times (WORM) characteristics and the writing operation is voltage-polarity-independent. The resistance states can be repeatably read $10^{4}\times $ and the data retention time is over 104 s. A high read-disturb immunity is also observed for over 104 s. Data retention and read-disturb characteristics measured at 85 °C predict a ten-year lifetime of the device. The carrier transport and the RS mechanisms are studied and illustrated. [ABSTRACT FROM AUTHOR]

We report on a room temperature Aerosol Jet printed two-terminal WSe2 crossbar architecture device on flexible substrate that achieves dual functionality of both a resistive random access memory (ReRAM), as well as a photosensor. As a ReRAM, the silver contacted WSe2 device exhibits forming free, sub 1-V switching voltage, and an on-off ratio of 2 orders. Furthermore, the WSe2 ReRAM exhibits both volatile and non-volatile switching behavior with a transition set current of ${2}~\mu \text{A}$ , translating to a low operating power of ${16}~\mu \text{W}$. As a photosensor with the same architecture, the transparent CNT electrodes contacted device allows incident light to pass through for photocurrent generation. The two terminals device allows photo sensitivity to be tuned by bias application. In such mode, a maximum photo responsivity of 1 A/W at a visible light wavelength of 660 nm is exhibited by the device at a bias of 1 V, allowing weak light signals to be amplified. In both cases, the WSe2 device retains its functionality even after bending down to a radius of 5 cm. The fabrication process can be up-scaled and has great potential to be used for conformal electronics system integration. [ABSTRACT FROM AUTHOR]

During the past few years, resistive random access memory (RRAM) have been widely studied for a large set of applications (neuromorphic computing, nonvolatile digital design, in-memory computation, etc.) due to its promising characteristics such as high-speed operations, nonvolatile retention, and low-power consumption. As a result, many SPICE RRAM models have been proposed to allow proper circuit-level simulations. However, physical design is a problem when it comes to full-custom RRAM-based layout and electronic design automation verification since no RRAM-based process design kits are publicly available. Consequently, evaluating the benefits and the metrics of RRAM-based systems at the circuit and chip levels in term of area is an issue. Indeed, many RRAM-based systems area results are based solely on the RRAM and transistor device count and not on the exact layout area, potentially leading to inaccurate results. In this paper, we propose an addon describing a CMOS compatible RRAM technology, for the NCSU FreePDK 45 nm. The addon comprises of the Stanford RRAM Verilog-A model, fitted on published experimental results as well as a set of design rule check and layout versus schematic rules for Calibre to ensure the correctness of the physical designs. We demonstrate the benefits of the proposed addon through three case studies to show that accurate RRAM-based systems area evaluations can be obtained at both circuit and chip levels. [ABSTRACT FROM AUTHOR]

We characterize SET-state current degradation induced by read operations in a tungsten oxide resistive memory cell. The current degradation exhibits a two-stage evolution. In the second stage, the current decline follows inverse power-law dependence on cumulative read-disturb time. We present an analytical model to derive the inverse power law. Our model includes oxygen ion activation, mobile oxygen ion hopping, and the reduction of oxygen vacancy density by re-oxidation. Voltage and temperature effects on read-disturb-induced degradation are characterized for comparison with the model. Our results show that the power factor in the inverse power law has exponential dependence on a read voltage. [ABSTRACT FROM AUTHOR]

We propose, demonstrate, and assess a nontunneling-based nMOS voltage-controlled negative differential resistance (V-NDR) concept for overcoming the intrinsic efficiency and reliability shortcomings of magnetic random access memory memories (MRAM). Using nMOS V-NDR circuits in series with MRAM tunnel junctions, we experimentally observe 40 times reduction in current during switching, enabling write termination and read margin amplification. Large scale Monte Carlo simulations also show 5X improvement in write energy savings and demonstrate the robustness of the scheme against device variability. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate in depth Forming, SET, and Retention of conductive-bridge random-access memory (CBRAM). A kinetic Monte Carlo model of the CBRAM has been developed considering ionic hopping and chemical reaction dynamics. Based on inputs from ab initio calculations and the physical properties of the materials, the model offers the simulation of both the Forming/SET and the Data Retention operations. It aims to create a bond between the physics at atomic level and the device behavior. From the model and experimental results obtained on decananometric devices, we propose an understanding of the physical mechanisms involved in the CBRAM operations. Using the consistent Forming/SET and Data Retention model, we obtained good agreement with the experimental data. Finally, the impact of each layer of the CBRAM on the Forming/SET behavior is decorrelated, allowing an optimization of the performance. [ABSTRACT FROM AUTHOR]

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1–7 pJ per bit and has a high programming endurance of up to 10^6\vphantom \sum ^R^R cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of <1~\mu \textA are achieved. [ABSTRACT FROM PUBLISHER]

In this letter, by utilizing the unique property of large hysteresis of threshold selector, a novel operation scheme is proposed to not only lower the voltages and power, but also remove the voltage matching constrains between resistive memory (RRAM) and selector. This makes threshold selector suitable for most of RRAM integration. [ABSTRACT FROM PUBLISHER]

In addition to the potential for memristors to be used in logic, memory, smart interconnects, and biologically inspired architectures that could transform traditional silicon-based computing, memristors may enable such transformative technologies on physically flexible substrates. The simple structure of a memristor, which generally consists of a thin film of oxide sandwiched between two metal contacts, contributes to its compatibility with existing and future large area flexible electronics. This is especially true considering that recent work has demonstrated the ability for titanium dioxide-based memristors to be deposited from solution at room temperature by using a sol gel technique on a flexible polymer substrate. The integration of memristors with traditional flexible devices (such as thin-film organic, zinc oxide, or amorphous-Si transistors) may enable the realization of a new paradigm in computing technology through lightweight, inexpensive, flexible electronics. [ABSTRACT FROM PUBLISHER]

This paper introduces a novel structure for filamentary-conduction-type resistance change memory. The new structure utilizes the fringing field from the top metal electrode to effectively confine the position of the filaments in the cell. Nanoscale (100–50 nm) memory cells are fabricated using nickel oxide (NiO) thin film as the resistance-switching layer to demonstrate the feasibility and functionality of the new structure. The fabricated nanoscale memory cells achieved low reset current (100–200 \mu\A), narrower distribution in low-resistance states, and higher on/off ratio than those of the standard structure. In addition, good scalability down to 50 nm was demonstrated. [ABSTRACT FROM AUTHOR]

For the applications of resistive random access memory (RRAM), we study the complementary resistive switch (CRS) behavior of a bilayer \Nb2\O5-x\/\NbOy RRAM. The CRS effect is explained by the redistribution of oxygen vacancies inside the two niobium oxide layers. Improved CRS effects were observed using W top electrode (TE) instead of Pt, which can be attributed to the oxygen barrier layer derived from a self-formed \WOx layer between the W TE and the \Nb2\O5-x oxide film. The niobium oxide-based CRS devices within a single memory cell can be directly integrated into a crossbar memory array without the need of extra diodes; this can significantly reduce the fabrication complexity. [ABSTRACT FROM AUTHOR]

For the high-density memory application of resistive random access memory (ReRAM), we study the complementary resistive switch (CRS) behavior of a \HfOx-based ReRAM with a \TiOx-based ReRAM. To control the operation voltages of the CRS device, we used ReRAMs having asymmetric set and reset voltages. Consequently, we achieved a wider voltage window for the read process, high switch speed, high reliability, and more than ten times readout margin from the heterodevice CRS. [ABSTRACT FROM AUTHOR]

The high performance of a resistive memory device based on electrochemical metallization is presented. With a solid electrolyte mixture consisting of zinc sulfide and silicon dioxide, the device combines the strengths of pure sulfide and pure oxide electrolytes, and exhibits various attractive characteristics such as forming-free switching, reasonably low currents, and high speed. Bipolar switching with an on/ off-state resistance ratio of about 100 is demonstrated by a direct-current quasi-static sweep. Pulse characterization shows that the device can be bistably SET and RESET using square pulses with pulsewidth down to 10 ns. Reliable endurance of \10^5 cycles and a stable retention time up to \10^6 \ \s are also achieved. [ABSTRACT FROM PUBLISHER]

We report on electrically induced multi-resistance states in \VO2/\HfO2/\VO2 heterostructures on silicon at room temperature. Through geometric confinement, the critical threshold voltage for the transition in each \VO2 layer can be tuned, and this leads to sharp current jumps as each layer undergoes a conductance transition. Consistent results are obtained in both voltage and current sweep conditions. The ability to realize variable resistance states in correlated oxide heterostructures fabricated on silicon could be of relevance to emerging information processing and storage schemes utilizing functional oxides. [ABSTRACT FROM PUBLISHER]

In this letter, we propose a model based on noise analysis for the filamentary switching mechanism in resistance random access memory having \ZrOx/\HfOx bilayer stacks. From the noise analysis results, we concluded that the current flowing during high-resistance state can be described as a trap-assisted current that flows through traps. It has been hypothesized that these traps are the cause of the instability of device parameters. To validate this, the noise analysis results of large-area devices were compared with those of small-area devices. As a consequence, we improved the uniformity of device parameters. [ABSTRACT FROM AUTHOR]

A scaling feasibility for the process integration of the \Ti/HfOx resistance memory with pillar structure is studied in this letter. An empirical model is successfully developed to correlate the forming voltage of devices to their cell sizes. The abnormal increase in the breakdown voltage and the absence of the resistance switching characteristic for the scaled devices (< 150 nm) are observed for the devices encapsulated with the \SiO2 film. This result is attributed to the reduction in the oxygen-gettering ability of the Ti top layer by the \SiO2 passivation layer. For scaled devices with the \Si3\N4 passivation layer, the Ti film retains the same oxygen-gettering ability as the large devices. A 0.5-V reduction in the forming voltage for the 50-nm devices by using the \S3\N4, instead of the \SiO2, layer is observed. The 50-nm devices with the \Si3\N4 encapsulating layer exhibits improved memory performances such as large on/off ratio (> 100), high temperature stability at 200 ^\circ\C for 500 min, and satisfactory endurance ( \10^4 cycles). [ABSTRACT FROM PUBLISHER]

An ultrahigh on/off -current ratio of \5 \times \10^9 is presented in a resistive memory device using Au nanoparticles (Au NPs)-incorporated poly(N-vinylcarbazole) (PVK) and poly(3, 4-ethylenedioxythiophene)–poly(styrenesulfonate) (PEDOT–PSS) stacking configurations as the active layer and Al as electrodes for nonvolatile-memory application. The investigation also suggests that the enhancement of the on/off-current ratio cannot be achieved by simply increasing the thickness of the PVK:Au NPs layer itself. This PVK:Au-NPs/PEDOT–PSS stacking-bilayer memory device also demonstrates good retention of high on /off-current ratio for at least 2 h and remains programmable at 125 ^\circ\C. [ABSTRACT FROM PUBLISHER]