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Summary: As transistor feature size is scaling down, the probability of charge sharing in a space‐radiation environment increases because of the reduced distance between adjacent transistors. The single‐event multiple‐node upset (SEMNU) caused by charge sharing is a major source of data errors in high‐density static random‐access memory (SRAM). In this paper, a radiation‐hardened SRAM using polarity hardening is proposed. Compared to other cells (RHPD‐12T, RSP14T, SEA14T, We‐Quatro, QUCCE12T, SARP12T, SIS10T, and 12T), the proposed RHC‐14T cell saves 8.47%, 91.34%, 162.71%, ‐20.63%, −20.50%, 113.18%, 63.27%, and 20.60% of the read‐delay time and 7.96%, 66.17%, 68.16%, 57.71%, 22.39%, 12.44%, 1,010.45%, and 13.43% of the write‐delay time, respectively. Moreover, this excellent performance entails only minimal power consumption. The proposed cell can work well in the radiation‐intensive space environment. [ABSTRACT FROM AUTHOR]

In this paper, a Tunnel FETs (TFETs) and MOSFETs hybrid integrated 9T SRAM (HI-9T) with data-aware write technique is proposed. This structure solves the problem of excessive static power consumption caused by forward p-i-n current in the conventional 7T TFET SRAM (CV-7T), and the problem of weakened writing ability caused by the use of the TFET-stacked structure of the most advanced combined access 10T TFET SRAM (CA-10T). The simulation results demonstrate that the static power consumption of HI-9T is reduced by three orders of magnitude compared with CV-7T at a 0.6 V supply voltage and the ability to maintain data is more stable. Compared with CA-10T, the write margin (WM) of HI-9T is increased by about 2.4 times and the write latency is reduced by 54.8% at 0.5 V supply voltage. HI-9T still has good writing ability under the 0.6 V supply voltage and the CA-10T cannot write normally. Therefore, HI-9T has good overall performance and is more advantageous in ultra-low power applications. [ABSTRACT FROM AUTHOR]

Frequent to-and-from data transfers in the von Neumann architecture limit the overall throughput. One of the promising approaches used to overcome von Neumann bottleneck is in-memory computing (IMC) that aims to embed computing in memory to reduce the transfer of memory-processor data. This study proposes a configurable 6-transistor (6T) static random access memory (SRAM) array with a multilevel shared structure for IMC. A multilevel shared structure can effectively improve the utilization rate of the module. In addition to the conventional SRAM operation, the configurable structure can also perform the sum of absolute differences (SAD) and Hamming distance (HD) calculations. To quickly identify the minimum value among multiple calculation results, a four-input sense amplifier (SA) is proposed. The performance of the proposed memory is simulated in a 65-nm CMOS process. The post-layout simulation results show good linearity of the multirow read in the SAD and HD modes. The mean time required by the four-input SA to obtain the result is 190 ps. The SAD and HD calculations yield consumptions of 67.44 fJ/byte and 0.64 fJ/bit, respectively, at 0.8 V. Furthermore, a single column-sharing comparator consumes 2.78 and 3.41 pJ at 0.8 V in the SAD and HD modes, respectively. [ABSTRACT FROM AUTHOR]

In‐memory computing (IMC) is a novel computing architecture that presents considerable potential in solving the data transmission and energy consumption problems faced by the von Neumann architecture. The compound Boolean logic operation (CBLO) is a crucial component of most advanced computing platforms. This study presents a static random‐access memory array structure comprising configurable embedded arithmetic logic units (ALUs), which can realize four types of CBLOs within a single cycle. The proposed structure can also form the ternary content addressable memory (TCAM) for ternary searching by configuring signal lines and sense amplifiers. The authors performed 5000 trials of the Monte Carlo simulation for four types of CBLOs. The results of all four types were observed to be accurate, and the delay of the TCAM was observed to be as low as 141 ps, which improves the parallelism of IMC, reduces power consumption, and significantly reduces calculation delay. [ABSTRACT FROM AUTHOR]

In-memory computing establishes a new and promising computing paradigm aimed at solving problems caused by the von Neumann bottleneck. It eliminates the need for frequent data transfer between the memory and processing modules and enables the parallel activation of multiple lines. However, vertical data storage is generally required, increasing the implementation complexity for the SRAM writing mode. This article proposes a 10-transistor (10T) SRAM to omit vertical data storage and improve the stability of in-memory computing. A cross-layout of the word line enables arrays with multirow or multicolumn parallel activation to perform vector logic operations in two directions. In addition, the novel horizontal read channel allows matrix transposition. By reconfiguring the data lines, sense amplifiers, and multiplexing read ports, the proposed SRAM can be regarded as a content-addressable memory (CAM), and its symmetry provides selectable data search by column or by row according to the application that easily fits the SRAM storage mode without additional data adjustments. A proposed self-termination structure aims to decrease search energy consumption by approximately 38.5% at 0.9 V at the TT process corner. To verify the effectiveness of the proposed design, a 4 Kb SRAM was implemented in 28-nm CMOS technology. The read margin of the proposed 10T SRAM cell is three times higher than that of the conventional 6-transistor cell. At 0.9 V, logic operations can be performed at approximately 300 MHz, and binary CAM search operations are achieved at approximately 260 MHz with around 1 fJ of energy consumption per search/bit. [ABSTRACT FROM AUTHOR]

Although multirow read is essential to achieve static random access memory (SRAM) in-memory computing (IMC), it may undermine circuit linearity and computational consistency across columns. In this study, we investigated the causes of nonlinearity and inconsistency. Based on detailed analyses, we proposed a cascade current mirror (CCM) peripheral circuit. Only four transistors were added to each bitline (BL) for voltage clamping and proportionally mirroring the read current. In addition, a 6T SRAM cell with double word lines operating with the CCM further reduced the delay and improved the computational consistency. We applied the structure to numerous prior studies and evaluated them using the 28-nm complementary metal–oxide semiconductor process. The measurement results show that the proposed CCM can reduce the integer nonlinearity by up to 70% at 0.8-V supply, and the computational consistency is substantially improved by 56.84% at 0.9-V supply. In addition, we verified the performance improvement through classification using a convolutional neural network, achieving 91% accuracy in the MNIST and 86% accuracy in the CIFAR-10. The area overhead was 1.77% in a $512\times512$ SRAM array when integrating the proposed CCM circuit. [ABSTRACT FROM AUTHOR]

Traditional von Neumann architecture, characterized by separate memory and processing units connected by a limited-capacity memory bus, faces challenges in handling tasks with high energy efficiency requirements. In contrast, the compute-in-memory (CIM) architecture offers a promising alternative, facilitating high parallelism in data processing while integrating storage functions, thereby significantly reducing memory access frequency and power consumption. This study presents a fully digital CIM macro featuring a novel self-write-back 12T cell. This bitcell is capable of performing Boolean logic operations and autonomously writing back results into the in-situ cell, thereby significantly improving energy efficiency.This can be used for binary logical operations between each pixel of two images without requiring additional storage area. A bidirectional read/write architectural design enables matrix transposition. This can achieve image rotation.Additionally, this novel 12T cell also offers the option to choose not to write back the results of logical operations, thereby providing the flexibility and configurability for image processing. Combined with an adder tree, it enables multiply-and-accumulate (MAC) operation for convolutional neural networks(CNNs). This can be used for feature extraction. We propose an 18T full adder structure with lower power-delay product than current state-of-the-art full adders, which is advantageous for improving the synthesis performance of the adder tree.The CIM macro supports a 4-bit × 4-bit MAC operation. The proposed CIM macro, designed and simulated using a 28 nm CMOS process with a 16 Kb static random access memory (SRAM), demonstrates promising results. At VDD = 0.9 V, the logic operation energy consumption is 1.35 fJ/bit with an energy efficiency of 740TOPS/W, and MAC operation energy consumption is 15.91 fJ/bit with an energy efficiency of 62.85 TOPS/W. [ABSTRACT FROM AUTHOR]

The computation of multiplication in memory is a promising approach to reduce latency and improve the energy efficiency of intelligence edge processors. However, the multiplication operation in the analog domain is associated with complex peripheral circuits and low accuracy. In this letter, an static random‐access memory (SRAM) array with embedded low area cost arithmetic and logic units is proposed, which realizes high‐speed and high‐precision multi‐bit multiplication. The calculation delay is as low as 164 ps. The maximum integral non‐linearity (INL) is only 0.340 least significant bit, which is 1/16 of that of analog domain multiplication. [ABSTRACT FROM AUTHOR]

The von Neumann architecture is approaching its limits in terms of scalability and power consumption. In-memory computation is a possible approach to mitigate this limitation. This brief proposes a configurable 8T static random access memory (SRAM) cell with double word lines and three read ports for in-memory computing. In addition to the normal SRAM function, XOR/XNOR and compound Boolean logic operations of three or four operands, such as AND-OR, AND-OR-INVERT, OR-AND, and OR-AND-INVERT, can be performed in one cycle by fully utilizing the three read ports to obtain 13.2-fJ/bit consumption at 0.6 V. The logic operation frequency is 793 MHz at 1.2 V. The proposed SRAM effectively resolves the bottleneck of the existing in-memory computation schemes that only support compound Boolean logic operations with more than two cycles. In addition, the proposed SRAM array scheme can be configured and used as a binary content-addressable memory or a ternary content-addressable memory for searching operations; it achieves 0.24 fJ/search/bit at 0.6 V in the worst case. At 1.2 V, the searching frequency is up to 813 MHz when searching 128 bits with 65-nm technology. [ABSTRACT FROM AUTHOR]

This article presents a new resistive random access memory (RRAM)-based average 7T1R nonvolatile static random access memory (nvSRAM). This multiple sharing (MS) 7T1R uses MS schemes in which some of the transistors play various roles. Therefore, the MS-7T1R can perform a decoupled read, enhance write capability, and improve the restore yield with a small area cost. Furthermore, the MS-7T1R can offer two alternative modes, i.e., a high speed and a stable mode. Compared with existing technologies, such as the previous 6T-based nvSRAMs, the results show that the proposed architecture provides a remarkable restore yield and ~154% improvement in the read static noise margin (at TT corner and stable mode). In addition, the read delay improves by ~23% (at TT corner and high-speed mode). The write “1” problem of the single bitline is effectively resolved with our proposed write strategy. The static write margin of “1” is improved by ~88.6% compared with the conventional 6T ($\beta =4$) at a power of 1.2 V. In addition, dynamic power is effectively reduced by the use of the single bitline and sub-word-line driver technology. [ABSTRACT FROM AUTHOR]

In this brief, we proposed, based on the polarity upset mechanism of single-event transient voltage of n-channel metal–oxide–semiconductor (nMOS) transistors, a novel radiation hardened by polar design (RHPD) 12T SRAM cell to enhance the reliability and operation speed for space applications. Simulation results in Semiconductor Manufacturing International Corporation (SMIC) 65-nm CMOS commercial standard process show that the proposed RHPD-12T cell can tolerate all single-node upsets. Meanwhile, compared with We-QUATRO, QUATRO, and dual interlocked storage cell (DICE), the write speed of the proposed cell can be reduced by ~41.8 and ~35.3%, and the static power consumption is reduced by ~41.6 and ~46.3%, respectively. Monte Carlo (MC) simulation has proved that under high frequency and low supply (0.6 V) voltage, RHPD-12T has the minimum write failure probability compared with five other SRAM cells. [ABSTRACT FROM AUTHOR]

With advances in semiconductor technology, the threshold voltage variation has worsened, which has a great impact on the speed and stability of static random access memory (SRAM). This paper proposes a pipeline replica bitline (RBL) delay technique designed to reduce the timing variation of SRAM sense amplifiers. This design takes full advantage of all cells in the RBL as replica cells (RCs). A tunable pipeline structure is applied to control the discharge of groups of RCs. The structure is designed based on theoretical analysis and fabricated using an SMIC 28-nm CMOS process. The measurement results show that the delay variation can be reduced by approximately 43% and 32% compared with the conventional RBL and multistage RBL, respectively. Furthermore, with slight tuning of the normal 28-nm foundry process, four wafers were obtained under extreme conditions to comprehensively test the proposed technique. The results show that the proposed technique is more stable than other techniques in any extreme condition. [ABSTRACT FROM PUBLISHER]

This Letter proposes a new scheme to eliminate the bit‐line leakage current of static random access memory. The proposed scheme utilises a four‐input sense amplifier to amplify the voltages of self‐compared bit‐line pairs. The bit‐lines of the proposed structure have no series capacitances and are directly connected to the sense amplifier input. By this way, read delay and error caused by the leakage current of bit‐lines will be eliminated. Simulation results in SMIC 28 nm CMOS process design kits show that the proposed scheme has better stability and can decrease delay time by 41.1% at 0.9 V supply voltage compared with the X‐Calibration technology. [ABSTRACT FROM AUTHOR]

In-memory computing (IMC) has been widely accepted to be an effective method to improve energy efficiency. To realize IMC, operands in static random-access memory (SRAM) are stored in columns, which contradicts SRAM write patterns and requires additional data movement. In this paper, an 8T SRAM array with configurable word lines is proposed, in where the operands are arranged in rows, following the traditional SRAM storage pattern, and therefore additional data movement is not required. The proposed structure supports three different computing modes. In the ternary multiplication mode, the reference voltage generation column is not required. The energy of computing is only 1.273 fJ/bit. In the unsigned multibit multiplication mode, discharge and charging paths are used to enlarge the voltage difference of the least significant bit. In the logic operation mode, different types of operations (e.g., IMP, OR, NOR, XNOR, and XOR) are achieved in a single cycle. The frequency of logic computing is up to 909 MHz. [ABSTRACT FROM AUTHOR]

The successful implementation of artificial intelligence algorithms depends on the capacity to execute numerous repeated operations, which, in turn, requires systems with high data throughput. Although emerging computing‐in‐memory (CIM) eliminates the need for frequent data transfer between the memory and processing blocks and enables parallel activation of multiple rows, the traditional structure, where each row has only one identical input value, significantly limits its further application. To solve this problem, this study proposes a dual‐SRAM CIM architecture in which two SRAM arrays are coupled such that all operands are different, thus rendering the use of CIM considerably more flexible. The proposed dual‐SRAM array was implemented through a 55‐nm process, essentially delivering a frequency of 361 MHz for a 1.2‐V supply and energy efficiency of 161 TOPS/W at 0.9 V supply. [ABSTRACT FROM AUTHOR]

In the emerging field of Computing-in-Memory (CIM), this study introduces a 28-nm CMOS-based Static Random Access Memory (SRAM) CIM macro capable of various computational modes, potentially offering a solution to the Von Neumann bottleneck. Beyond traditional SRAM read and write operations, to enhance the flexibility of the CIM macro, a 9T cell is proposed for performing AND, OR, and XNOR operations; a new capacitive weighting module is introduced to reduce the area of conventional ladder capacitors; and a redundant array-assisted Analog-to-Digital Converter (ADC) is proposed to improve linearity during ADC quantization. The proposed architecture can achieve multi-bit multiplication and accumulation (MAC), OR accumulation (ORA), and XNOR accumulation (XNORA). Simulated using a 28-nm CMOS process, the architecture demonstrated a minor standard deviation in BL voltage of 16.27 mV at the SS process corner, as evidenced by Monte Carlo simulation. At the TT process corner, the energy expenditure for MAC, XNORA, and ORA operations was 5.76, 5.85, and 5.82 fJ/op, respectively. [ABSTRACT FROM AUTHOR]

With technology scaling down, the charge sharing among multiple nodes has becoming significant, making Single Event Multiple Node Upsets (SEMNUs) has become one of the major concern in memory cell designs. In this paper, a design of polarity hardening memory cell (PH_14T) is proposed for mitigating Single Event Multiple Node Upsets (SEMNUs). Through the 3D TCAD mixed-mode simulation established that the high robustness against SEU and SEMNUs of the PH_14T cell. Additionally, Cadence Spectre simulation results demonstrated that the proposed PH_14T cell has smaller write access time, lower power consumption, and highest critical charge compared to radiation-hardened cells. Monte Carlo simulation further confirmed the high radiation tolerance and high reliability of the proposed cell against SNU and DNU. [ABSTRACT FROM AUTHOR]

In the emerging field of in-memory computing (IMC), this study proposes a dual-port static random access memory (SRAM) IMC architecture with the distinct capability of realizing XOR encryption (XORE), thus serving as a potential solution for the Von Neumann bottleneck. Beyond providing traditional SRAM read and write operations, the proposed architecture carries out additional tasks such as multi-bit multiply and accumulate (MAC) and XOR accumulation (XORA). The architecture was simulated using a 28-nm Complementary Metal Oxide Semiconductor Process, demonstrating a minor standard deviation of 9.41 mV in bit line voltage at the SS process corner, as evidenced by Monte Carlo simulation. Energy expenditure for the MAC, XORA, and XORE, was found to be 1.65, 1.46, and 9.02 fJ/ops respectively at the TT process corner. Furthermore, the presented architecture showed considerable energy efficiency, with MAC, XORA, and XORE operations achieving energy efficiency values of 604.9, 682.7, and 110.8 TOPS/W respectively, at a supply voltage of 0.9 V at the TT process corner. [ABSTRACT FROM AUTHOR]

The proposal of compute-in-memory (CIM) is a breakthrough for the traditional von Neumann architecture to achieve efficient computing research. This architecture has unique advantages in the computing field thanks to supporting multi-line computing and without data transmission between processor and memory. In this paper, an in-memory computing structure based on 9T SRAM unit is proposed, which can both operate on memory and computing mode. Compared with the previous works, thanks to the redundant units, the computational structure can directly complete XNOR operations and storage of the whole SRAM array in only one cycle, without the need of extra digital logic circuits (such as AND, OR circuits), which can significantly improve the parallelism of the computation. Meanwhile, the architecture can map the XNOR logical operation into the binary multiplication, and then add up the one-bit multiplication results through the addition tree, thus realizing the binary convolution calculation. A 64-bit × 64-bit (4 Kb) SRAM array with the proposed scheme is designed and simulated in 55 nm CMOS technology. Simulation results show excellent stability and write yields in SRAM memory mode at an operating frequency of 200 MHz. In computing mode, the SRAM array power consumption for logical operation is 52.68 fJ/bit at 1.2 V supply voltage. At a minimum supply voltage of 0.8 V, the power consumption is only 5.58 fJ/bit, with an energy efficiency 179.21 TOPS/W. [ABSTRACT FROM AUTHOR]

Artificial intelligence algorithms play important roles in image classification to speech recognition, which contains enormous Boolean logic and multiplication operations. Traditional von Neumann architecture separates computing and storage units, which leads to "power walls" and "memory walls" problems. In-memory computing (IMC) is a promising method to solve these problems. In this work, we propose an IMC macro based on customed 9T-SRAM, which can be configured in memory, Boolean logic and multiply-and-accumulate (MAC) modes. The 9T-SRAM adopts read/write decoupled and a tail transistor structure, which enhances the read stability and reduces power consumption. With the bias rows, Boolean logic results are obtained from the differential voltages on two bitlines, reducing the peripheral circuit for reference voltage generation. Furthermore, the bias rows replace analog to digital converter (ADC) to binarize the MAC result, reducing the area overhead. In a 55 nm process, simulations manifest the 9T-SRAM shows enhanced read static noise margin, and the macro exhibits stable IMC operations and high energy-efficiency. [ABSTRACT FROM AUTHOR]

With the reduction of MOS transistor process size, the ability of static random access memory (SRAM) to resist single event upset plays an important role in reducing the soft error rate of chips. In this paper, a novel Radiation Hardened By Design Cell (RHBD-14T) using source isolation technology to reduce the number of sensitive nodes is proposed, compared with the following latest radiation-hardened memory cells (WE-Quatro, RHPD-12T, SAR-14T, SEA-14T, QUCCE-12T, SARP-12T, EDP-12T, QCCS, SCCS and SERSC-16T), the proposed RHBD-14T saves 0.5%, −5.3%, 100.2%, 83.6%, −18.5%, −22.8%, 83.7%, 72%, −2.1%, 171% of read-delay time and −13.4%, −36.3%, −34.4%, 24.1%, 8.4%, 153.1%, 47.8%, 14.7%, −2.8%, −32.8% of write delay time, respectively. In addition, RHBD-14T has the smallest power consumption and the largest hold static noise margin (HSNM), read static noise margin (RSNM) and charge-SNM to power-area-delay (QSPAD), which means it is more suitable for radiation intensive space environment. [ABSTRACT FROM AUTHOR]

For low voltage CMOS static random access memory (SRAM) cells, the leakage current on bit-lines will slow down the reading operation and even lead to error reading. Herein we report a 4B4C circuit composed of 8T SRAM arrays, four bit-lines and four coupling capacitors to track and compensate the bit-line leakage current (BLLC). The assistant bit-lines are used to control the connection of capacitors. The coupling capacitors are used to compensate voltage losses caused by the BLLC, and improve the maximum tolerable current from primary bit-line. The timing diagram and output waveforms verify the compensatory effects of coupling capacitors. The 4B4C circuit shows fast reading operation and increases the maximum tolerable leakage current to 17.8 times compared with conventional circuit at FS process corner. The 4B4C circuit can keep 100% correct reading till 200 μA from Monte Carlo simulations. The 4B4C circuit enhances SRAM reading reliability and shows huge potential in very-large scale memory arrays. [ABSTRACT FROM AUTHOR]

This paper proposed a radiation-hardened memory cell (RHMC12T) by polar design for space applications. The proposed cell has the following advantages: (1) it can tolerate all single-node upset and partial double-node upset based on combining radiation hardened by polar design technology together with reasonable layout topology; (2) comparing with the state-of-the-art radiation hardened SRAM cells, simulation results show the proposed RHMC12T cell has lower write access time, higher wordline write trip voltage, larger static noise margin, and larger critical charge. And Monte Carlo simulation results have shown that RHMC12T has good robustness; (3) electrical quality metric is widely used to evaluate the overall performance of SRAM cells. And RHMC12T has the largest EQM compared with the state-of-the-art radiation hardened SRAM cells, which suggests the proposed RHMC12T exhibits good circuit performance (including write/read access time, static noise margin et al.) as well as good radiation resistance performance with sacrificing a large area overhead. [ABSTRACT FROM AUTHOR]

As the feature size of transistors scaling down, the integration density of memory circuits such as Static random access memory (SRAM) cells increases, and they are more sensitive to Single event effect (SEE). The Single event multiple node upset (SEMNUs) caused by charge sharing effect is becoming a major concern in memory circuit design. In this paper, a new radiation-hardened SRAM cell (NRHC-14T) is proposed on the basis of considering the radiation-hardened and the operating performance of the basic circuit. The circuit uses polarity hardening technology to reduce the number of sensitive nodes, and can recover from Dual-node upset (DNU) on the basis of all single-node upset (SNU) recovery. Compared to other radiation-hardened cells, NRHC-14T cell than We-Quatro, DICE, SAR14T, RSP14T, RHPD-12T, QUCCE12T, and SEA14T increased by 60.12 %, 9.22 %, 21.39 %, 84.34 %, 17.92 %, 100.58 %, and 129.48 % of the writing speed, and saved by 34.28 %, 57.14 %, 22.85 %, 11.43 %, 68.57 %, 34.28 %, and 79.99 % of the power consumption, respectively. In addition, NRHC-14T has better stability, the highest Critical charge (Q crit) and the best overall performance. The cell proposed in this paper can be well used to aerospace electronic devices and work stably in space radiation environment by virtue of its excellent radiation-hardened ability and good overall performance. • This paper presents a new radiation-hardened SRAM cell (NRHC-14T); • It has a fast read and write speed, will be strong stability; • It reduces the number of sensitive nodes to only three; • On the basis of resisting SNU, it can resist DNUs through reasonable layout. [ABSTRACT FROM AUTHOR]

Sense amplifiers (SA) are facing increasing offset problems and amplifying problems due to mismatch of transistors and variations. This paper presents a structure that cancels the offset which is based on the delay and offset relation. The proposed structure can measure the delay of an SA due to its own offset voltage, and convert it into the length of a correction signal. The correction signal discharges the input of the SA, which reduces the voltage of the input to cancel the offset of the SA. The proposed technique can be applied to both the conventional latch-type SA (CLSA) and the current-latched SA with an NMOS footswitch (CSANF). The schematic simulations based on the 28 nm complementary metal-oxide semiconductor process show that the proposed technique can achieve a more centralized offset distribution than the CLSA and the CSANF. Moreover, the offset voltage of the two types SA can be reduced by 71.42% and 65.95%, respectively. [ABSTRACT FROM AUTHOR]