A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC.

The proposal of compute-in-memory (CIM) is a breakthrough for the traditional von Neumann architecture to achieve efficient computing research. This architecture has unique advantages in the computing field thanks to supporting multi-line computing and without data transmission between processor and memory. In this paper, an in-memory computing structure based on 9T SRAM unit is proposed, which can both operate on memory and computing mode. Compared with the previous works, thanks to the redundant units, the computational structure can directly complete XNOR operations and storage of the whole SRAM array in only one cycle, without the need of extra digital logic circuits (such as AND, OR circuits), which can significantly improve the parallelism of the computation. Meanwhile, the architecture can map the XNOR logical operation into the binary multiplication, and then add up the one-bit multiplication results through the addition tree, thus realizing the binary convolution calculation. A 64-bit × 64-bit (4 Kb) SRAM array with the proposed scheme is designed and simulated in 55 nm CMOS technology. Simulation results show excellent stability and write yields in SRAM memory mode at an operating frequency of 200 MHz. In computing mode, the SRAM array power consumption for logical operation is 52.68 fJ/bit at 1.2 V supply voltage. At a minimum supply voltage of 0.8 V, the power consumption is only 5.58 fJ/bit, with an energy efficiency 179.21 TOPS/W. [ABSTRACT FROM AUTHOR]