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This paper presents a detailed investigation of the quasi-static capacitance-voltage (QSCV) technique in pseudo-metal-oxide-semiconductor field effect transistor (pseudo-MOSFET) configuration for evaluating the interface quality of bare silicon-on-insulator (SOI) wafers, without processing dedicated metal-oxide-semiconductor (MOS) test devices. A physical model is developed that is capable of explaining the experimental results. In addition, frequency effects are used to validate the equations by a systematic comparison between experimental and calculated characteristics, as well as by a direct comparison with the standard high-low frequency approach. An extraction procedure for interface trap density based solely on QSCV experimental results is proposed, and limits of the procedure are discussed. The proposed experimental and analytical procedure is demonstrated by characterizing SOI structures with different geometries and with different qualities of surface passivation of the top silicon film. [ABSTRACT FROM AUTHOR]

Low-frequency noise (LFN) measurements are largely used for interface quality characterization in MOSFETs. In this work, a detailed investigation of LFN technique applied to pseudo-MOSFETs in bare silicon-on-insulator (SOI) substrates is provided. A physical model capable to describe the experimental results is proposed and validated using different die areas and inter-probe distances. The effective silicon area contributing to the noise signal, the impact of defects induced by probes and the possibility to extract interface trap density are addressed. [ABSTRACT FROM AUTHOR]

The parasitic bipolar effect is investigated in fully-depleted silicon-on-insulator (FD SOI) n-type MOSFETs with ultra-thin films (5–10 nm). Our measurements show that at low drain bias the drain leakage current is governed by the gate current. Beyond V D > 1.0 V, leakage current amplification is observed in short-channel 10-nm thick devices. With film thickness shrinking, the current amplification is suppressed. We explain this amplification by the turn-on of the lateral parasitic bipolar transistor. TCAD simulations confirm that the parasitic bipolar is activated due to holes generated by band-to-band tunneling at the drain side and accumulated in the floating body. An effective method for the extraction of bipolar gain is proposed based on the comparison of leakage current in short- and long-channel devices. The experimental method is validated through simulations. [ABSTRACT FROM AUTHOR]

SOI technology offers ample room for scaling, performance improvement, and innovations. The current status is reviewed by focusing on several technological options for boosting the transport properties in SOI MOSFETs. The impact of series resistance, high-K dielectrics, and metal gate in advanced transistors is discussed. Carrier mobility measurements as a function of channel length and temperature reveal the beneficial effect of strain, mitigated however by various types of defects. The experimental data is exclusively collected from state-of-the-art, ultrathin body, fully depleted MOSFETs. Simple models are presented to clarify the mobility behavior. [ABSTRACT FROM AUTHOR]

Abstract: Low-frequency noise (LFN) is generated by interactions of the channel carriers with interface traps and oxide charges. Therefore, noise measurements on silicon on insulator (SOI) wafers can give important information about the state of the interfaces and their defect density. Here, noise measurements at wafer level were performed using the pseudo-MOSFET (Ψ-MOSFET) configuration. 1/f noise behavior in relatively thick and ultra-thin SOI layers is obtained. No probe pressure dependence of the noise is observed. The influence of wafer surface states is showed and further confirmed in passivated SOI samples. Origins of noise generation are discussed. [Copyright &y& Elsevier]

In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO 2 /Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials. [ABSTRACT FROM AUTHOR]

In this work we investigate a non-invasive, non-destructive characterization technique for monitoring the quality of film, oxide and interfaces in silicon-on-insulator (SOI) wafers. This technique is based on optical Second Harmonic Generation (SHG). The principles of SHG and the experimental setup will be thoroughly described. The experimental parameters best suited for testing SOI wafers with SHG are identified. SOI geometry, as well as the passivation of the top surface, both have an impact on the observed SHG signal. The back-gate bias applied on the substrate is shown to modulate the SHG signal. [ABSTRACT FROM AUTHOR]