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Abstract During deep reactive ion etching (DRIE), microscale etch masks with small opening such as trenches or holes suffer from limited aspect ratio because diffusion of reactive ions and free radicals become progressively difficult as the number of DRIE cycle increases. For this reason, high aspect ratio structures of microscale trenches or holes are not readily available with standard DRIE recipes and microscale holes are more problematic than trenches due to omnidirectional confinement. In this letter, we propose an optimization for fabrication of high aspect ratio microscale hole arrays with an improved cross-sectional etch profile. Bias voltage and inductively coupled plasma power are considered as optimization parameters to promote the bottom etching of the high aspect ratio hole array. In addition, flow rates of octafluorocyclobutane (C $$_{4}$$ 4 F $$_{8}$$ 8 ) and sulfur hexafluoride (SF $$_{6}$$ 6 ) for passivation and depassivation steps, respectively, are considered as optimization parameters to reduce the etch undercut. As a result of optimization, the aspect ratio of 20 is achieved for 1.3 μm-diameter hole array and etch area reduction at the bottom relative to the top is improved to 21%.

• Flat oxide layers are fabricated on silicon substrates by seed-guided laser processing. • Defect is firstly generated on silicon substrate, function as a high optical absorption. • Laser oxidation mechanisms are analyzed to tune the oxide layer morphology. • The flat oxide layers serve as an etch stop layers. • Three-dimensional silicon gratings are fabricated by deep reactive ion etching. Laser oxidation provides a flexible maskless functional three-dimensional silicon structure fabrication strategy. Here, oxide layers are fabricated on silicon substrates by high-repetition-rate femtosecond laser irradiation. Formation mechanisms of the femtosecond laser oxidation are analyzed to tune the oxide layer morphology. When the laser fluence is high, the oxidation process is accompanied by laser ablation, so the oxide layer is always on top of laser ablated groove. To obtain the flat oxide layer, defect is firstly generated on silicon substrate by the laser irradiation at a high laser fluence of 126 mJ/cm2, function as a high optical absorption. It is called seed as it can assist to achieve lower fluence laser oxidation at 38 mJ/cm2 and result in a flat oxide layer. Full width at half-maximum of the oxide layer is also reduced. The laser fabricated oxide layers are used as etching masks. Three-dimensional silicon gratings are fabricated by deep reactive ion etching, which demonstrate desirable beam diffraction properties. [ABSTRACT FROM AUTHOR]

During deep reactive ion etching (DRIE), microscale etch masks with small opening such as trenches or holes suffer from limited aspect ratio because diffusion of reactive ions and free radicals become progressively difficult as the number of DRIE cycle increases. For this reason, high aspect ratio structures of microscale trenches or holes are not readily available with standard DRIE recipes and microscale holes are more problematic than trenches due to omnidirectional confinement. In this letter, we propose an optimization for fabrication of high aspect ratio microscale hole arrays with an improved cross-sectional etch profile. Bias voltage and inductively coupled plasma power are considered as optimization parameters to promote the bottom etching of the high aspect ratio hole array. In addition, flow rates of octafluorocyclobutane (C 4 F 8 ) and sulfur hexafluoride (SF 6 ) for passivation and depassivation steps, respectively, are considered as optimization parameters to reduce the etch undercut. As a result of optimization, the aspect ratio of 20 is achieved for 1.3 μm-diameter hole array and etch area reduction at the bottom relative to the top is improved to 21%. [ABSTRACT FROM AUTHOR]

Deep reactive ion etching (DRIE) technology is one of the most important technologies in the processing of microelectronic devices and microelectromechanical system. As a necessary process in semiconductor integration, it has been widely studied in the past decades. It is known that the traditional DRIE process typically uses a plasma etching reactor equipped with inductively coupled plasma (ICP) sources to generate a high-density plasma so as to achieve high aspect ratio trenches with relatively small roughness. A cryogenic temperature control unit is typically employed as well. Here, however, we use a parallel plate RIE with rather simple structure, which is not usually used for DRIE, to obtain high aspect ratio silicon etching. With no ICP sources and no sophisticated temperature control unit, the system and experiment are now much more cost effective. Through the optimization of the processing, the etching rate of silicon can reach 440 nm/min. Finally, a 45 μm deep trench is etched in silicon with good perpendicularity. This method will greatly reduce the equipment related cost, especially for those applications that do not have extremely stringent requirement on the final etching accuracy. [ABSTRACT FROM AUTHOR]

• The deep reactive ion etching (DRIE) of in-plane silicon microneedles is presented. • A needle sharpening process is developed using sacrificial layers (remaining unetched silicon). • The wedge-shaped needle is sharpened to conical structure tapering from the base to the apex. • The sharp microneedles have been demonstrated to be sufficiently robust for skin penetration. The deep reactive ion etching (DRIE) of in-plane silicon microneedles with open capillary microfluidic network is presented. The in-plane needle design allows easy fabrication of long needles for accessing abundant dermal fluids and improves the correlation with blood biomarkers. However, the anisotropic DRIE yields wedge-shaped (not sharp) needle tip. We developed a sharpening process using the sacrificial layers (remaining unetched silicon layer below the needle shaft) to facilitate the buildup of the concentration gradient of the etching species during the wet etching sharpening process, resulting in the relatively fast etching rate at shaft top than the bottom. As a result, the wedge-shaped structure is sharpened to conical structure, tapering smoothly from the base to the apex. Such sharp microneedles have been demonstrated to be sufficiently robust to penetrate porcine skins, with needles being intact after repetitive penetrations. The fabricated silicon devices are treated with oxygen plasma for making the surface hydrophilic, such that the capillary fluid is introduced within the open microfluidic network. [ABSTRACT FROM AUTHOR]

We fabricated silicon (100) membranes of 3 mm in diameter on the surface of silicon-on-insulator (SOI) substrates and investigated the characteristics of the membranes. The handle layer of one SOI substrate was etched using deep reactive ion etching process with the buried oxide (BOX) layer that remained together with the device layer. The BOX layer of the other SOI substrate was removed using C4F8-based plasma etching after the handle layer etching. The surfaces of both silicon (100) membranes were observed using the scanning white light interferometer system at room temperature. Both silicon (100) membranes have dome-like deformations. The silicon (100) membranes are effectively flattened by etching the BOX layer under the device layer. Both silicon (100) membranes were cooled from room temperature to 4 K by a Gifford-McMahon refrigerator. Wrinkles appeared on the surfaces of both silicon (100) membranes when the temperature dropped to about 200 K. However, the wrinkles disappeared below about 180 K. This phenomenon indicates the wrinkles at low temperature would depend on the properties of the silicon (100) of the device layers and independent of the properties of the BOX layers under the silicon (100) membranes. [ABSTRACT FROM AUTHOR]

This paper reports an advanced deep reactive ion etching (DRIE) process for realizing ultra-deep (>500- $\mu \text{m}$ ) and ultra-high aspect-ratio (UHAR) silicon structures (AR > 40 for 1-mm through-trench etch, $\text {AR}\approx 80$ for 500- $\mu \text{m}$ through-trench etch, and AR > 20 for 500- $\mu \text{m}$ through-hole etch), with straight sidewalls across a wide range of feature sizes. The challenges of making such structures are overcome by continuously ramping critical parameters of the Bosch DRIE process throughout the process, including the 380-kHz bias power during etch step, the etch/passivation step duration, and the chamber pressure. The masking material capable of enduring the long DRIE process is also discussed; 10- $\mu \text{m}$ and 25- $\mu \text{m}$ wide trenches are etched to a depth of >750- $\mu \text{m}$ and >1000- $\mu \text{m}$ , respectively, in 1-mm-thick silicon wafers with straight sidewall profiles and flat trench bottoms. Deeper trenches are expected to be etched beyond a 1-mm thick wafer with thicker and/or higher selectivity masking materials. We have also demonstrated etching of circular holes of diameters as small as 25- $\mu \text{m}$ to a depth of >500- $\mu \text{m}$ , and potentially with 10–15 $\mu \text{m}$ diameter holes. This advanced DRIE process offers opportunities for applications ranging from through-silicon via in 3-D CMOS integration to emerging micro- and meso-scale microelectromechanical system applications that demand ultra-deep and UHAR DRIE. [2017–0298] [ABSTRACT FROM AUTHOR]

We present two simple methods, with parallel and serial gas flows, for the stacking of microfabricated silicon fuel cells with integrated current collectors, flow fields and gas diffusion layers. The gas diffusion layer is implemented using black silicon. In the two stacking methods proposed in this work, the fluidic apertures and gas flow topology are rotationally symmetric and enable us to stack fuel cells without an increase in the number of electrical or fluidic ports or interconnects. Thanks to this simplicity and the structural compactness of each cell, the obtained stacks are very thin (~1.6 mm for a two-cell stack). We have fabricated two-cell stacks with two different gas flow topologies and obtained an open-circuit voltage (OCV) of 1.6 V and a power density of 63 mW·cm−2, proving the viability of the design.

The cryogenic process and the Bosch process are two widely used processes for reactive ion etching of high aspect ratio silicon structures. This paper focuses on the cryogenic deep etching of 400-nm pitch silicon gratings with various etching mask materials, including polymer, Cr, SiO2, and Cr-on-polymer. The undercut is found to be the key factor limiting the achievable aspect ratio for the direct hard masks of Cr and SiO2, while the etch selectivity responds to the limitation of the polymer mask. The Cr-on-polymer mask provides the same high selectivity as Cr and reduces the excessive undercut introduced by direct hard masks. By optimizing the etching parameters, we etched a 400-nm pitch grating to \approx 10.6~\mu \textm depth, corresponding to an aspect ratio of $\approx 53$ . [2016-0106] [ABSTRACT FROM AUTHOR]

Fabrication of 3-D microstructures is one of the most challenging aspects of silicon micromachining. In this paper, we present a novel microfabrication method using one single-step deep reactive ion etching process with gray-scale e-beam lithography mask that offers deeply etched (>350- \mu \textm deep) dual-angle 3-D microneedles with control over the height and shape of the structures. Moreover, we found that the shape of the e-beam lithography patterns can determine the general configuration and features of the final etched microneedles, and that the etching process parameters have the most impact on the microneedles’ shape, such as size and vertical base angle. Large arrays of $20\times 20$ microneedles with height uniformity of better than 3% are fabricated. [2014-0209] [ABSTRACT FROM PUBLISHER]

In recent years, optical stimulation in neuroscience has emerged as an alternative to electrical stimulation. In this work, we present the concept and optical simulation of an optrode capable of delivering focused infrared light to brain tissue, while simultaneously recording electrical signals from the surrounding area. The system combines the advantages of silicon microfabrication and silicon's transparency in the near-infrared. For efficient coupling into the probe and controlling the illuminated volume in the brain, silicon microlenses were simulated using MATLAB. The lens system can focus light in 2-D, with configurable focal length and spot size. [ABSTRACT FROM AUTHOR]

A batch fabrication process for nanoelectromechanical systems (NEMS) based on sidewall transfer lithography (STL) is demonstrated. The STL is used to form nanoscale flexible silicon suspensions entirely by conventional photolithography. A two-step process for combining microscale and nanoscale features is used to fabricate double-ended and single-ended electrothermal actuators with a minimum feature width of 100 nm and an aspect ratio of 40:1. All devices are fabricated by deep reactive ion etching in 4.5-μm-thick silicon using bonded silicon-on-insulator material. The process could allow low cost fabrication of nanoscale sensors and actuators. [ABSTRACT FROM AUTHOR]

We present two simple methods, with parallel and serial gas flows, for the stacking of microfabricated silicon fuel cells with integrated current collectors, flow fields and gas diffusion layers. The gas diffusion layer is implemented using black silicon. In the two stacking methods proposed in this work, the fluidic apertures and gas flow topology are rotationally symmetric and enable us to stack fuel cells without an increase in the number of electrical or fluidic ports or interconnects. Thanks to this simplicity and the structural compactness of each cell, the obtained stacks are very thin (~1.6 mm for a two-cell stack). We have fabricated two-cell stacks with two different gas flow topologies and obtained an open-circuit voltage (OCV) of 1.6 V and a power density of 63 mWcnT2, proving the viability of the design. [ABSTRACT FROM AUTHOR]

Abstract: Hard X-ray grating interferometry has shown promising results in phase and scattering imaging, as well as in metrology applications. Recently, the technique has been extended to two dimensions, recording the full phase gradient vector and a directional scattering signal. Here, we present a process for fabricating the key optical elements required for this technique: phase and absorption gratings with periods of few micrometers and high aspect ratios, with a particular focus on two-dimensional grating structures. The fabrication process is based on deep reactive ion etching in silicon and electroplating of gold. [Copyright &y& Elsevier]

We present recent advances in modeling, design, and fabrication of in-plane multilayer optical resonators fabricated by high aspect ratio etching of silicon. We first revisit the model of Gaussian beam divergence proposed by A. Lipson to correct a mistake that leads to an underestimation of the losses affecting this type of resonator. Secondly, we discuss the influence of surface roughness at the silicon-air interfaces of multilayered structures. Roughness profiles-measured by white light interferometry on the sidewalls of silicon trenches etched by deep reactive ion etching (DRIE)-are presented. The single absorbing layer model of Carniglia is used to predict the influence of the measured roughness ( nm RMS). This model is combined with the corrected model for Gaussian beam divergence and is compared with recent experimental results obtained for a new generation of deep-etched Fabry-Perot refractive index sensors. These sensors are fabricated using the contour lithography method, which is demonstrated to greatly improve the predictability of their optical characteristics. The combined model for roughness and divergence is found to correspond remarkably well with the experimental results, with predictions of loss and finesse of the resonances within an average error of 1.3 dB and 25%, respectively. We therefore expect the models and the simulations presented in this article to become a useful tool for the design of devices based on deep-etched multilayer resonators. [ABSTRACT FROM PUBLISHER]

In this paper, a novel Mach-Zhender interferometer for spectroscopy applications is presented. The interferometer is fully integrated on an silicon on insulator wafer using deep reactive ion etching technology, the moving mirror is coupled to a comb drive microelectromechanical systems (MEMS) actuator. Optical propagation inside the MEMS structure is modeled and the diffraction effect is studied. Practical results show the complementary nature of the two outputs and a resolution of 25 nm at 1.55 \mum is reported when using the interferometer as an Fourier transform infrared spectrometer. The complementary nature of the interferometer can be further used for source noise reduction. [ABSTRACT FROM PUBLISHER]

Abstract: An effective fabrication method combining deep reactive ion etching and galvanic etching for silicon micro–nano hierarchical structures is presented in this paper. The method can partially control the morphology of the nanostructures and enables us to investigate the effects of geometry changes on the properties of the surfaces. The forming mechanism of silicon nanostructures based on silver nanoparticle galvanic etching was illustrated and the effects of process parameters on the surface morphology were thoroughly discussed. It is found that process parameters have more impact on the height of silicon nanostructure than its diameter. Contact angle measurement and tilting/dropping test results show that as-prepared silicon surfaces with hierarchical structures were superhydrophobic. What’s more, two-scale model composed of micropillar arrays and nanopillar arrays was proposed to study the wettability of the surface with hierarchical structures. Wettability analysis results indicate that the superhydrophobic surface may demonstrate a hybrid state at which water sits on nanoscale pillars and immerses into microscale grooves partially. [Copyright &y& Elsevier]

It is mentioned about the parametric experiments for deep reactive ion etching (DRIE) method for n type, <100> oriented, 100mm (milimeter) Silicon as a subtrate and SU8-3050 negative photo resist as a mask material in this study. DRIE process is performed in plasma that is produced by two RF (Radio Frequency) power sources with the additional specific etch gases under the high vacuum atmosphere. DRIE method is widely used in micro electro mechanical systems (MEMS) industry to produce high aspect ratio micro structure with etch rates. The effects of six different DRIE variables on Si and SU8 etch rate were observed within this experimental study. This variables are: Chamber pressure (mTorr), RF plasma power (Watt), RF platen power (Watt), SF6 gas flow rate (ml/s) as main etch gas, O2 gas flow rate (ml/s), He gas flow rate ml/s. The experiment was performed with ICP plasma etching device in Istanbul Technical University Micro Electromechanic Systems for Biological Applications (BIO-MEMS) Laboratory. The results were measured by a stylus profile meter device. [ABSTRACT FROM AUTHOR]

Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops. [ABSTRACT FROM PUBLISHER]

Abstract: A methodology developed for measuring Young’s modulus and the full stress–strain curve on micron-sized specimens was extended here to measure Poisson’s ratio. A dog-bone type specimen was used within a small loading machine with a maximum load of 5N. The specimen was fabricated from single crystal silicon (SC-Si) with the specimen gage and loading direction in the 〈001〉 orientation. A silicon on insulator (SOI) wafer was used with a deep reactive ion etching (DRIE) based process. Geometrical parameters of the initial cross-sectional area of the gage were measured by means of image processing on environmental scanning electron microscope (ESEM) images. The test setup also consists of an optical microscope with a monochromatic camera and a data acquisition system. The strains were obtained through the displacement field which was determined by means of digital image correlation (DIC). A speckle pattern was placed on the specimen gage. SC-Si was chosen to study since it is expected that on both the micro and macro-scales, Young’s modulus and Poisson’s ratio will have the same value. Hence, the accuracy of the method may be examined. The average value of Young’s modulus E =131.4±2.1GPa was obtained with the micro-specimens and is consistent with values determined on the macro-scale (E =130GPa). The average value of Poisson’s ratio on the micro-scale was found as ν =0.23±0.03 which is lower than the macro-scale value of ν =0.28. The failure stress was determined to be σ f =1.46±0.10GPa. Results for Young’s modulus reflect the reliability of the methodology which is suitable for characterization of a large variety of materials exploited in micro-devices for both sensing and actuation. The reasons for the low values measured for ν were investigated through emulations of determining the strains. An improvement in the image acquisition system is suggested. [Copyright &y& Elsevier]

In the MEMS industry today, device reliability is commonly evaluated by simulating the loads applied to a device using finite element (FE) analysis and setting a threshold for the allowable first principal stress (S1). This is a potentially misleading practice for the analysis of brittle structures, but it is used because better reliability tools have not been validated and adopted for MEMS design. In this paper, we detail and validate pragmatic FE-based MEMS analysis capabilities: local (device feature) failure probability prediction and surface-specific failure probability intensity (FPI, \mu\m^-2) plotting, which quantitatively identify the most probable locations of fracture on a MEMS device and provide a more meaningful and higher contrast visualization versus corresponding plots of S1. To validate prediction effectiveness, fractographic analysis was completed on micromirrors (a representative MEMS device) loaded in two distinct complex stress states (primarily, tension or torsion) until failure, thus determining the locations of fracture initiation and their relative probabilities. Our method improves the simulation-driven design of brittle microstructures by providing not only the failure probability of the total structure but also probable failure locations as a function of load, all of which are essential for intelligent design iteration. [ABSTRACT FROM PUBLISHER]

Abstract: The purpose of this work is to describe an original process that has been designed for the fabrication of a microfluidic converter. The fabrication is based on deep reactive ion etching of silicon and low temperature full wafer adhesive bonding. The technology development includes an improvement of the bonding process in order to produce an adaptive strength of SU-8 bond which not only ensures absence of debonding failures during the silicon deep etching procedure and the subsequent dicing procedure, but also avoids the potential SU-8 overflow leakage into channels due to the bonding step. Besides, the originality of the work is not only in the process but also in the design of the device. Common actuation method for microfluidic system is either based on closed-channel continuous-flow microfluidic (CMF) or droplet-based microfluidic (DMF). Both of them have advantages and disadvantages, and their integration on a single system is in dire need. In this paper, we briefly discuss the concept of microfluidic converter, integrating CMF with DMF, which can: (i) continuously preload reagents, (ii) independently manipulate several droplets, (iii) recombine and export samples into closed-channel continuous flow, making it ideal for interfacing to liquid-handling instruments and micro-analytical instruments. [Copyright &y& Elsevier]

Abstract: This paper presents 3-D MEMS-fabricated lithium rechargeable batteries relying on structured silicon rods as anodes in order to increase the effective electrode surface area. A new method of fabricating silicon micro/nano rod arrays with controllable diameters in the range of 300–8000nm is proposed. Different sizes of silicon rod-arrays as anodes were successfully incorporated into an all-solid-state battery construction. The structured architecture of the silicon electrodes allowed for a heightened surface area as well as improvement in cycle life and capacity over comparable planar electrodes. Structured rod array electrodes showed a first cycle coulombic efficiency over 80% which is more than double that of conventional powder composite silicon electrodes. Galvanostatic cycling of structured silicon rod electrodes showed highly reversible capacity for high current densities. Variation of rod diameter and current density revealed that decreasing the rod diameter leads to higher capacity and more stable cycling of batteries. [Copyright &y& Elsevier]

During deep reactive ion etching of silicon used for through silicon via or deep trench isolation processing, the bevel of the wafer is also etched away. The etching of the bevel results in a deep step at the litho edge bead removal or in a degraded bevel shape, source of yield loss or processing issues. Two methods are proposed here to prevent the bevel degradation during deep reactive ion etching using an oxide hard mask. In one case this oxide mask is deposited in the second case the oxide hard mask is grown. [ABSTRACT FROM AUTHOR]

This paper presents a novel dielectric waveguide based G-band interconnect. By using a new transition of microstrip line to dielectric waveguide, the interconnect achieves low insertion loss and wide bandwidth. The measured minimum insertion loss is 4.9 dB with 9.7 GHz 1-dB bandwidth. Besides, the structure is based on standard micromachined processing and easy to integrate with conventional packaging. [ABSTRACT FROM PUBLISHER]

Abstract-We describe and validate a new failure prediction methodology specifically designed for single-crystal microelectromechanical systems (MEMS) devices under general service loadings. The methodology uses experimental data efficiently generated from fracture testing of simple test specimens to calculate a series of Weibull parameters descriptive of specific surface conditions. These data, combined with finite element modeling, are used to predict the fracture probability for any MEMS device fabricated by the same processes under any type of loading. We demonstrate the accuracy of our method by comparing predicted fracture probabilities against actual fracture test results for a micromirror in two distinct multiaxial loading configurations. [ABSTRACT FROM AUTHOR]

Communication systems such as those used on satellite platforms demand high performance from individual components that make up the various systems and sub-systems. Switching and routing of RF signals between various modules is a routine and critical operation that determines the overall efficiency of the entire system. In this paper, we present the design and fabrication aspects of a direct contact RF MEMS switch designed to operate in the X band (8-12 GHz) with a target insertion of about 0.5 dB and isolation better than 30 dB. The actuation voltage is expected to be around 50V. The die size is designed to be 3mm (H) x 3mm(W) x 2mm(H). The switch is built from a low residual stress device layer of a highly conducting (0.005 Ohms-cm) silicon on insulator (SOI) wafer. After subsequent lithographic steps, the wafer is bonded to a Pyrex glass wafer which has been previously patterned with gold transmission lines and pull in electrodes. Being built from a single crystal silicon structure, the mechanical robustness of the actuator is much greater than the those in similar membranebased devices. A 6 mask fabrication process utilizing Deep Reactive Ion Etching to achieve high aspect ratio stiction free structures was developed and implemented. Devices from the first fabrication run are being analysed in our laboratory. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, a novel design of silicon micro/nanopillars based multilayer water-cooled heat sink is presented, which enhances the overall thermal performance of electronics/MEMS components by a noteworthy amount. Heat dissipation rate of electronic devices is significantly increased by the silicon micro/nanopillars, which are grown in the microchannels by utilizing the micromasking effect in deep reactive ion etching. Due to the smaller diameter (0.5–2μm) and larger height (∼100μm), the surface area of these silicon pillars is very high, which results in enhanced convective heat transfer rate, and thus improved thermal performance. Gold thin films of varying thicknesses were used as etching mask during the fabrication of silicon microchannel and silicon nanopillars. Effects of etching mask type, mask thickness, platen power and substrate temperature on controlling the physical dimensions and the density of silicon pillars in the microchannels, are presented. A simple thermal model is developed to compare the heat dissipation characteristics of the heat sink, with and without the silicon pillars. The analytical analysis shows that the heat dissipation rate of the heat sink with silicon pillars can be increased by 16% than that of without silicon pillars. The effects of pillar diameter, height, and pillar density, on overall thermal resistance and the heat dissipation rate are also shown. [Copyright &y& Elsevier]

The design and performance of a silicon-based RF detector coil for use in magnetic resonance (MR) spectroscopy applications is described. The coil is fabricated using microelectromechanical systems (MEMS) technology by deep reactive ion etching (DRIE) of an oxidized silicon substrate carrying electroplated conductors. The DRIE step simultaneously forms a sample trough and creates a trepan cut around the coil so that it may be detached from the substrate by cleaving short sections of sprue. A single-turn coil with Q-factor ~16 at 63.6 MHz is demonstrated and MR spectroscopy experiments are described. An accurate numerical model based on the time-domain finite integration technique is used to investigate the effect on the Q-factor of deliberately structuring the substrate to limit the volume of silicon exposed to RF energy. The model is compared with known analytic approximations, and good agreement is obtained. [ABSTRACT FROM PUBLISHER]

Electrolytic conductivity measurements of fluids currently require sample volumes greater than a milliliter. Many applications would benefit from accurate measurements of nano- to microliter sample volumes. However, polarization and nonlinear electrode impedance effects, along with stray impedance and temperature effects, strongly affect measurements of the solution conductance for microliter and smaller sample volumes. MEMS-based silicon electrolytic conductivity probes, down to 100-μm wide, with integrated temperature sensors, have been designed and fabricated to overcome these effects. Several electrode configurations were tested: plain electrode pairs, electrode pairs plated with platinum black, plain four electrode sets, and four electrode sets plated with platinum black were investigated. The same accuracy as normal scale probes has been achieved with these sensors over almost three orders of magnitude in solution concentration and electrolytic conductivity ranges. [ABSTRACT FROM PUBLISHER]

Large-scale high power-density power sources, such as jet engines and turbines for electric power generation, are commonplace in engineering, yet no sources of corresponding power-density exist on a smaller scale. The MIT Microengine Project is an effort to address this situation by utilizing micro-electromechanical systems (MEMS) technology to construct a family of microscale devices such as gas turbine engines, microrockets, micropumps, and electrical micromotors and microgenerators that attempt to bring the advantages of macro-scale engines to a more portable scale. Fabrication aspects of the project are discussed in this article, with emphasis on the challenges involved in fabricating complex pieces of microturbomachinery that must sustain combustion pressures and temperatures, high rotational speeds, and be machined to micron tolerances. [Copyright &y& Elsevier]

The high aspect-ratio combined poly- and single-crystal silicon micromachining technology (HARPSS) and its application to fabrication of precision MEMS inertial sensors are presented. HARPSS is a single wafer, all silicon, front-side release process which is capable of producing 10–100''s of microns thick, electrically isolated, 3-D poly- and single-crystalline silicon microstructures with various size air-gaps ranging from sub-micron to tens of microns. High aspect-ratio (>50:1) polysilicon structures are created by refilling 100''s of microns deep trenches with polysilicon deposited over a sacrificial oxide layer. This technology provides features required for precision micromachined inertial sensors. The all-silicon feature of this technology improves long term stability and temperature sensitivity while fabrication of large area, vertical electrodes with sub-micron gap spacing will increase the sensitivity by orders of magnitude. [Copyright &y& Elsevier]

The design, fabrication, and characterization of an electrostatically tunable optical Fabry-Perot (FP) filter with hybrid integration of grating and slot structures are presented. Using deep reactive ion etching, antireflection grating (ARG) structures are created at the inner wall of the FP resonator to enhance the performance of a tunable FP filter. The moving parts are released by etching the buried oxide layer using hydrofluoric acid vapor. The optical tuning range of the device is 19 nm. Attributed to the ARG structures, the light propagates effectively through the FP resonator. Thus, the Q-factor of the resonant peak is enhanced more than threefold when an FP resonator with ARG structures is compared with an FP resonator using one-slot (Si/air/Si) structure. With the optimized design, an FP resonator comprising of the ARG and two-slot structures shows record-breaking Q-factor, i.e., 9762. [ABSTRACT FROM AUTHOR]

We present a method to produce small pitch gratings for X-ray interferometric imaging applications, allowing the phase sensitivity to be increased and/or the length of the laboratory setup to be minimized. The method is based on fabrication of high aspect ratio silicon microstructures using deep reactive ion etching (Bosch technique) of dense grating arrays and followed by conformal electroplating of Au. We demonstrated that low resistivity Si substrates (<0.01 Ohm·cm) enable the metal seeding layer deposition step to be avoided, which is normally required to initiate the electroplating process. Etching conditions were optimized to realize Si recess structures with a slight bottom tapering, which ensured the void-free Au filling of the trenches. Vapor HF was used to remove the native oxide layer from the Si grating surface prior to electroplating in the cyanide-based Au electrolyte. Fabrication of Au gratings with pitch in the range 1.2–3.0 µm was successfully realized. A substantial improved aspect ratio of 45:1 for a pitch size of 1.2 µm was achieved with respect to the prior art on 4-inch wafer-based technology. The fabricated Au gratings were tested with X-ray interferometers in Talbot–Laue configuration with measured visibility of 13% at an X-ray design energy of 26 keV. [ABSTRACT FROM AUTHOR]

This work presents a novel two-axis gimbaled mirror for optical scanning applications. This scanner has been implemented using the molded surface-micromachining and bulk etching release (MOSBE II) process. Thus, the vertical comb-drive actuators are employed to realize the large stroke. The thin-film electrical routings are employed to drive the actuators individually. The rib-reinforced structures are exploited to increase the stiffness of mirror plate and supporting frame. In addition, the moving space created by backside deep reactive ion etching enables the mirror to perform large out-of-plane angular motion. The measured radius of curvature of reinforced mirror plate is 0.43 m. The maximum scanning angle of two driving axis are plusmn3.8deg at 55 V and plusmn2.4deg at 100 V, respectively. The resonant frequencies associated with the scanning modes are 5.8 and 7.8m kHz, respectively. In addition, the two-dimensional scanning images such as Lissajous patterns are also demonstrated [ABSTRACT FROM PUBLISHER]

A novel micromachined resonator at 45 GHz based on a defect in a periodic electromagnetic bandgap structure (EBG) and a two-pole Tchebyshev filter with 1.4% 0.15 dB equiripple bandwidth and 2.3 dB loss employing this resonator are presented in this letter. The periodic bandgap structure is realized on a 400 μm thick high-resistivity silicon wafer using deep reactive ion etching techniques. The resonator and filter can be accessed via coplanar waveguide feeds. [ABSTRACT FROM PUBLISHER]