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Low Vt Ni fully silicided (FUSI) devices are demonstrated making use of Al implantation for pMOS and Yb or Yb+P implantation for nMOS combined with Ni-silicide phase engineering. When Yb(+P) and Al implantation are followed by a high temperature anneal, significant segregation of Yb or Al toward the Ni-FUSI/SiON interface is observed and large Vt shifts of 450 mV (330 mV) and 200 mV are obtained for nMOS NiSi FUSI/SiON devices and pMOS Ni-rich FUSI/SiON devices, respectively, as compared to the undoped reference devices. The Vt shifts are preserved down to the shortest gate lengths. For both Al and Yb, the Vt shifts are explained by the dopants reacting with and modifying the dielectric. Thus, the low Vt dual implantation approach proposed achieves a low-cost "dual dielectric" implementation without the need of dual deposition of dielectrics or capping layers. In the case of Yb implantation followed by a high temperature anneal, a significant reduction in the inversion dielectric thickness is observed, indicating that the reaction between Yb and SiON results in the formation of a high-κ dielectric. The Yb diffusion and reaction at the interface can be engineered using a P complaint. [ABSTRACT FROM AUTHOR]

The kinetics of Ni3Si2 formation in the Ni2Si–NiSi thin film reaction were determined from simultaneous in situ x-ray diffraction (XRD) measurements, performed using a synchrotron source, and sheet resistance measurements. Samples consisted of 90 nm Ni/100 nm polycrystalline-Si/SiO2 stacks, of interest for fully silicided gate applications, on (100) Si. After initial formation of a Ni2Si/NiSi bilayer, these films reacted to form Ni3Si2. The evolution of sheet resistance and of the intensity of XRD peaks were used to extract the fraction of Ni3Si2 formed during ramp and isothermal annealings. A Kissinger analysis was performed for ramp annealing with ramp rates of 1, 3, 5, 9, and 27 °C/s, obtaining the activation energy of Ni3Si2 formation, Ea=1.92±0.15 eV. A Kolmogorov-Johnson-Mehl-Avrami analysis was performed for isothermal anneals, finding an Avrami exponent of 2.1±0.2, suggesting two-dimensional growth. This is consistent with a nucleation controlled process for Ni3Si2 formation, with nucleation sites at different positions in the thin film, and subsequent lateral two-dimensional propagation of the transformation front parallel to the film surface. Implications for Ni fully silicided gate applications are discussed. [ABSTRACT FROM AUTHOR]

The Ni silicidation of polycrystalline-Si/SiO2 gates with 25 nm linewidth was studied by x-ray diffraction and compared to that of blanket films. The authors found direct evidence of a linewidth effect in Ni full silicidation (FUSI), with formation of Ni-richer silicides at short gate lengths, and attribute it to the excess availability of Ni from regions surrounding the gate. On blanket films, the end silicide phase can be controlled by the deposited Ni (tNi) and polycrystalline-Si (tSi) thicknesses (e.g., tNi/tSi∼0.55, 1.09, 1.37, and 1.64 for stoichiometric NiSi, Ni2Si, Ni31Si12, and Ni3Si, respectively). In contrast, they demonstrate that on 25 nm lines, the resulting films can contain Ni31Si12 and Ni3Si even for deposited tNi/tSi as low as 0.6. They found, however, that the phase formation sequence and required thermal budgets were similar on 25 nm lines (tNi/tSi∼0.6 and 1.2) to those on blanket films with thicker Ni (tNi/tSi∼1.7). This suggests that the nucleation and phase formation kinetics of Ni silicides, including Ni31Si12 and Ni3Si, are not significantly affected by the small dimensions. They also demonstrated NiSi FUSI phase control down to 25 nm, by controlling the reacted Ni to Si ratio through the reaction thermal budget. These results indicate that Ni FUSI is an attractive option for future nodes. [ABSTRACT FROM AUTHOR]

In this letter, nMOSFETs using a NiSi:Yb fully suicide (FUSI) electrode are demonstrated for the first time. We report that the integration of NISI:Yb FUSI into our reference n-FETs with the respective SiON/HfSiON gate dielectrics results in a Vt reduction from 0.55/0.52 down to 0.30/0.43 V, without degradation of the gate dielectric integrity, channel interface states, and long channel devices mobility. [ABSTRACT FROM AUTHOR]

The effective work function (WF) of Ni3Si2 was evaluated on HfSixOy and SiO2 dielectrics. Ni3Si2 forms, in thin film Ni–Si diffusion couples with Ni to Si composition ratios between 1 and 2, after formation of a Ni2Si/NiSi stack and by its reaction at moderate thermal budgets (comparable to those used in back end processing of complementary metal-oxide-semiconductor circuits). Ni3Si2 formation limits, on the Ni-rich side, the process window for NiSi fully silicided (FUSI) gates (NiSi at interface with dielectric) to reacted Ni–Si ratios <1.5. The WF of Ni3Si2 was found to have similar values and behavior to that of NiSi, both on SiO2 (showing similar modulation with dopants) and on HfSixOy, in contrast to Ni-richer silicides such as Ni2Si and Ni31Si12 which do not exhibit significant WF modulation with dopants on SiO2 and have considerably higher WF on HfSixOy. This suggests that the chemistry and structure of the original NiSi/dielectric interface are not modified significantly by the subsequent growth of Ni3Si2 and implies that its formation may be tolerable when targeting NiSi FUSI gates, thereby expanding the process window for this application. [ABSTRACT FROM AUTHOR]

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni31Si12 FUSI gates on p-channel MOS (PMOS) with good Vt control to short gate lengths (LG = 50 nm, linear Vt of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NISi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni2Si or Ni31Si12 on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni2Si or Ni31Si12 FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% Ion improvement at Ioff = 100 nA/µm) was obtained for Ni31Si12 compared to Ni2Si FUSI gates, as well as a Vt reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS. [ABSTRACT FROM AUTHOR]

The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni2Si, and Ni31Si12. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and Vt control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni2Si processes with excessive thermal budgets, resulting in significant Vt shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth Vt rolloff characteristics was demonstrated for NiSi, Ni2Si, and Ni31Si12 FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni2Si are less than or equal to 25 °C, whereas a single-phase Ni31Si12 is obtained over an ∼ 200 °C temperature range. [ABSTRACT FROM AUTHOR]

The presence of Ni can significantly promote the CoSi–CoSi2 transformation process reducing the transformation temperature and, in consequence, the thermal budget of silicidation. In this work, silicidation of the Si/Co0.95Ni0.05/Ti system was investigated. Four point probe (4PP), Auger electron spectroscopy (AES), X-ray diffraction (XRD), Rutherford backscattering spectroscopy (RBS), and transmission electron microscopy (TEM) were used to characterise the silicide films. It was found that Co–Ni silicide can be formed at lower temperatures compared to the pure Co/Ti process, at the same time keeping important properties such as sheet resistance and roughness close to those of pure CoSi2. [Copyright &y& Elsevier]

Abstract: An overview of silicides and germanides for nano-CMOS applications is presented. The historical evolution describing the migration from the use of Ti silicide to Co silicide to Ni silicide as contacting material is first discussed. These changes in silicide material were mainly motivated by the inability to form the target low resistivity silicide phase in small structures due to low nucleation density. This issue was found first for the low resistivity C54 TiSi2 at linewidths below 200nm and later for the low resistivity CoSi2, at linewidths below 40nm. A detailed description of scalability and thermal stability issues for NiSi is then presented. No nucleation issues were found in small structures for NiSi, which grows by diffusion or interface limited kinetics with Ni as main moving species. However, silicidation can be excessive in small structures due to Ni diffusion from surrounding areas, resulting in thicker films than targeted in small devices. This can be controlled by using a silicidation process with two rapid thermal processing steps, the first one to control the amount of Ni reacted and the second one to convert the silicide to the target low resistivity monosilicide phase. One of the main issues for applications of NiSi is its low thermal stability: thin NiSi films agglomerate at relatively low temperatures. The process window and thermal stability of Ni and Pt-based films reacted with Si, Si:Ge and Si:C substrates is reviewed. Addition of Ge is shown to degrade thermal stability while addition of C or Pt improves it. Contact resistivity considerations and implementation of dual band-edge silicides are discussed, as well as promising results for the extension of Ni-based silicides to future nodes. Finally a brief overview of germanides is presented discussing NiGe and PdGe as main candidates. [Copyright &y& Elsevier]

Abstract: A systematic analysis of the different methods of work function (WF) tuning for gate stacks using fully silicided (FUSI) gate electrodes is presented. We show that FUSI gates have the potential to meet the WF requirements for future nodes, including high performance applications, achieving band edge WF, with total WF range of up to ∼900 meV. The introduction of dopants (such as Sb, As, P, B) by ion implantation is shown to be effective to tune the WF of NiSi or Ni3Si2 on SiO2 or SiON by ∼550 meV, but is ineffective on HfSiON or for Ni-richer silicides. Different silicide phases can be used for Ni FUSI gates on HfSiON dielectrics, taking advantage of the higher WF of metal-rich silicides, achieving a WF range of ∼400 meV. This method is not effective, however, on SiON dielectrics. The introduction of Lanthanides by several techniques (such as dielectric cap deposition, ion implantation into poly-Si, or at metal deposition) that result in the modification of the dielectric, is found, for Ni FUSI gates, to achieve low WF (∼4.0 eV) suitable for NMOS. Similarly, incorporation of Al can be used to achieve PMOS type WF, as well as the use of metal-rich Ni and/or Pt based FUSI gates (with WF as high as 5.0 eV). [Copyright &y& Elsevier]

Abstract: NiPt (10% Pt) and Pt were investigated as alternatives to Ni for contact formation to SiGe source/drain. The germanosilicide phase formation and morphology were studied by means of sheet resistance measurements, XRD (X-ray diffraction) analysis and SEM (scanning electron microscopy) inspection. From isochronal and isothermal anneals it is found that NiPt- and Pt-germanosilicide have better thermal stability compared to Ni-germanosilicide. NiPt-germanosilicide degrades morphologically, while still in the monogermanosilicide phase. [Copyright &y& Elsevier]