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We demonstrate coherent optical frequency dissemination over a distance of 972 km by cascading two spans where the phase noise is passively compensated for. Instead of employing a phase discriminator and a phase locking loop in the conventional active phase control scheme, the passive phase noise cancellation is realized by feeding double-trip beat-note frequency to the driver of the acoustic optical modulator at the local site. This passive scheme exhibits fine robustness and reliability, making it suitable for long-distance and noisy fiber links. An optical regeneration station is used in the link for signal amplification and cascaded transmission. The phase noise cancellation and transfer instability of the 972-km link is investigated, and transfer instability of 1.1 × 10−19 at 104 s is achieved. This work provides a promising method for realizing optical frequency distribution over thousands of kilometers by using fiber links. [ABSTRACT FROM AUTHOR]

This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246. [ABSTRACT FROM AUTHOR]

In this paper, we present the high-speed phase frequency detector where the phase characteristics are enhanced. This PFD has a simple structure where the dead zone is annihilated and blind zone is highly reduced. This PFD generates UP and DN signal only when it gets the distinct phase difference. With the reduction of the reset time, the proposed PFD function is in the order of 1.5 M H z − 4 G H z operating frequency. The design shows the improvement by completely eliminating the dead zone. However, the blind zone is minimised to 74.6 p s in the phase characteristics which improves the output phase noise as −132.9 d B c / H z at 1 M H z offset frequency. The power consumption is minimised upto 417.3 μ W @ 4 G H z operating frequency. The design is simulated in standard 0.18 \mum CMOS technology node with 1.8 V power supply. Furthermore, the achieved frequency band is applicable for high-speed and low-power PLL application such as Zigbee, Wifi, Bluetooth and 4 G communication. [ABSTRACT FROM AUTHOR]

This paper utilizes Taguchi design of experiments and Pareto analysis of variance statistical approaches to demonstrate circuit optimization. The phase-frequency detector (PFD) circuit based on dynamic logic has been chosen for optimization. For various MOSFETs of PFD, three levels and three factors of power supply and width of PMOS and NMOS ( V DD , w p , and w n ) are considered to be critical performance governing factors. The Taguchi technique determines the level of significance of a factor that influences a given performance parameter. The crucial factor for a given response is determined via ANOVA analysis. The optimum values for the parameters V DD , w p , and w n are likewise determined using this procedure to maximize the circuit's overall performance. Taguchi DoE and Pareto Anova analyses have been performed using the Minitab software. Simulating the circuit with GPDK 180 nm CMOS technology using these methods ensures that the acquired parameters are correct for best performance. The Cadence Virtuoso tool has been used to conduct pre-layout and post-layout simulations. The simulation outcomes are reasonably close to the ANOVA predicted result. Phase noise, power dissipation, and frequency of operation of the proposed PFD are − 1 5 9. 5 6 dBc/Hz, 9.83 μ W, and 10.21 GHz, respectively, and it occupies a chip area of 300.41 μ m 2 . The proposed PFD is used to implement a charge-pump PLL which performs effectively with a settling time of 2.59 μ s. [ABSTRACT FROM AUTHOR]

A low‐noise fully‐integrated charge‐pump phase‐locked loop (CPPLL) for 5G applications is presented in this letter. The PLL architecture includes a phase and frequency detector (PFD), a charge pump (CP), a low‐pass filter (LPF), a voltage‐controlled oscillator (VCO), and a programmable divider. To achieve low phase noise, class‐C VCO, TSPC logic, and other methods are employed in the PLL circuit design. Fabricated in 65 nm technology, the PLL measures a tuning range of 5.91–8.94 GHz. The minimum and maximum measured phase noise are −125 dBc/Hz and −116.6 dBc/Hz @1 MHz. The size of CPPLL core area is 0.8 mm by 0.95 mm without the pads while having a 50‐mW power consumption. [ABSTRACT FROM AUTHOR]

The phase frequency detector/charge pump is a significant source to raise the in-band phase noise of the phase-locked loop (PLL). The proposed CMOS-based pass transistor phase frequency detector (PT-PFD) solves the cycle skipping issue by improving the blind zone which in turn improves the phase noise performance. At the same time, in order to further improve the performance of the PLL, charge pump is integrated with the proposed design. In this case, the reset time has been reduced and thus the proposed PFD/CP functions up to the frequency of 1.5 MHz – 4.2 GHz. In addition, the modified pass transistor PFD architecture contains an advantage of less number of transistor count which consumes low power, i.e., 317.37 μ W . The design is based on standard 0.18 μ m CMOS process technology with the supply voltage of 1.8 V. Moreover, the proposed design has completely eliminated the dead zone, and blind zone is minimized up to 44.23 ps which improves the phase noise to −133.8 dBc/Hz at 1 MHz offset frequency. The PFD/CP proposed herein just requires lower power consumption while producing less noise in charge pump phase-locked loop (CPLL) application. [ABSTRACT FROM AUTHOR]

A novel phase frequency detector design is introduced in this study, which removes dead and blind zone issues by eliminating reset path, therefore accelerating the acquisition process. High speed, low power and minimal phase noise are all characteristics of the proposed circuit. The circuit is designed in the Cadence Virtuoso environment and is implemented in CMOS GPDK 180 nm library using a 1.8 V supply voltage. Post-layout simulations have been conducted to ensure that the findings are accurate. The circuit's robustness is tested over process, voltage and temperature fluctuations. The suggested PFD achieves a phase noise of − 1 5 9. 1 7 dBc/Hz, which is significantly lower than other published circuits. This PFD dissipates 10.25 μ W of power at its maximum operating frequency of 10 GHz. The PFD encompasses an area of 275 μ m2. The proposed PFD outperforms other PFD circuits in the literature, making it ideal for applications requiring minimal jitter, low power, etc. [ABSTRACT FROM AUTHOR]

In this work, a novel phase frequency detector (PFD) architecture using pass transistor logic is proposed. The circuit does not have a reset path, resulting in the elimination of blind zone and dead zone. The ϕ -V characteristics of the PFD were found to have better linearity across the range of − π to π due to the absence of blind and dead zones. The Taguchi and ANOVA statistical techniques were used to optimize the PFD. The optimized PFD exhibited a phase noise of −142.24 dBc/Hz, consumed 5.64 μ W of power and had a maximum operating frequency of 5.25 GHz, and a delay of 10.65 ps. Using this PFD, a GHz-range synthesizer was designed, and its performance characteristics were obtained from circuit simulations using CADENCE Virtuoso. The synthesizer had a power consumption of 4.25 mW at a supply of 1.8 V, achieved a lock time of 2. 95 μ s , and could generate frequencies ranging from 0.1 GHz to 4.75 GHz while occupying a chip area of 0.013 mm 2. Moreover, the work introduced a new figure of merit, FoM. The synthesizer has potential applications in various devices such as radio receivers, televisions, mobile phones, satellite receivers, and GPS systems. • The simple circuit of Phase Frequency Detector avoids the use of reset path to achieve zero dead zone and high operating frequency. • Pass transistor logic employed to the second stage of PFD which enhance the operating frequency and simplify the circuit. • Taguchi DoE and ANOVA optimization methodology have been used to find out the sizes of MOS transistors and supply voltage to achieve optimized results. • Optimized PFD has lower phase noise, low power dissipation, lesser delay and high maximum operating frequency thus beneficial for low power and high speed frequency synthesizer applications. • Significant high speed, low power dissipation, low THD and lesser chip area of Frequency synthesizer making it suitable for use in high-speed devices such as radio receivers and GPS systems. [ABSTRACT FROM AUTHOR]

This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer- $N$ phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, the proposed signal source shows a −73.1-dBc reference spur, −113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and −90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fsrms at 40.96 GHz and 122 fsrms (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is −3.24 dBm, and the power consumption is 372 mW. [ABSTRACT FROM AUTHOR]

We demonstrate the coherent transfer of an ultrastable optical frequency reference over a 490 km noisy field fiber link. The fiber-induced phase noise power spectrum density per-unit-length at 1 Hz offset frequency can reach up to 510 rad2â‹...Hzâˆ'1â‹...kmâˆ'1, which is much higher than the fiber noise observed in previous reports. This extreme level of phase noise is mainly due to the fiber link laying underground along the highway. Appropriate phase-locked loop parameters are chosen to complete the active compensation of fiber noise by measuring the intensity fluctuation of additional phase noise and designing a homemade digital frequency division phase discriminator with a large phase detection range of 212 Ď€ rad. Finally, a noise suppression intensity of approximately 40 dB at 1 Hz is obtained, with fractional frequency instability of 1.1 Ă— 10âˆ'14 at 1 s averaging time, and 3.7 Ă— 10âˆ'19 at 10000 s. The transfer system will be used for remote atomic clock comparisons and optical frequency distribution over a long-distance communication network established in China. [ABSTRACT FROM AUTHOR]

The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer- $N$ phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection and lock detection. Implemented in 40-nm CMOS technology, the proposed PLL shows a −75-dBc reference spur, −101.5-dBc/Hz PN at a 1-MHz offset, and a minimum integrated jitter of 121.9 fsrms (10 kHz–100 MHz) at 38.2 GHz with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB. [ABSTRACT FROM AUTHOR]

5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control. It provides one ration frequency ranged from 4.68 GHz to 5.36 GHz for the local oscillator in RF frontend circuits. Adopting a phase detector that only delivers phase error raw data when phase error is investigated and reduces the updating frequency for DCO handling code achieves a decreased reference spur. Since an all-digital phase-locked loop is designed, the prototype not only optimized the chip dimensions, but also precludes the influence of process shrinks and has the advantage of noise immunity. The elements of novelties of this article are low phase noise and low power consumption. With 1.8 V supply voltage and locking at 5.22 GHz, measured results find that the output signal power is −8.03 dBm, the phase noise is −110.74 dBc/Hz at 1 MHz offset frequency and the power dissipation is 16.2 mW, while the die dimensions are 0.901 × 0.935 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated analog phase‐locked loop (PLL) fractional‐N frequency synthesizer for 5G wireless communication and Internet‐of‐Everything (IoE) applications. To demonstrate the effectiveness of this frequency synthesizer, we apply it to three wireless communication standards. Contrary to using Verilog or VHDL to implement the programmable frequency divider, we propose a new approach in the transistor level with a new divide‐by‐2/3 circuit, dynamic asynchronous resettable D and JK flip‐flops, and the OR & AND gates to customize the divider for low‐power, low‐jitter, and fast‐lock time applications. In addition, we have designed a new frequency phase detector (PFD) to overcome the dead region issue. An ultra‐low phase noise and low‐power voltage control oscillator (VCO) is exploited from our previous work with the flicker noise corner frequency around 10 kHz to achieve the lowest possible phase noise. The implementation is done in 180‐nm standard CMOS technology. It covers two frequency ranges including 2.4 to 2.48 GHz and 5 to 5.825 GHz for these wireless communication standards. According to simulations in the worst case, the lock time, rms‐jitter, in‐band fractional spur, power consumption, and jitter‐power figure‐of‐merit of the frequency synthesizer is 18 μs, 56 fs, −63 dBc, 4 mW, and −259, respectively. [ABSTRACT FROM AUTHOR]

In this article, we develop the theory of a special type of optoelectronic phase-locked loop (PLL). The output signal of this type of PLL is in the electrical domain and its reference oscillator, typically a mode-locked laser, operates in the optical domain. The PLL uses a balanced optical microwave phase detector (BOMPD). In order to model the optoelectronic PLL, the nonlinear characteristic function and the gain of the BOMPD are derived analytically. Using the results of the phase detector analysis, the theory of an optoelectronic PLL using such a phase detector is developed. Based on the theoretical analysis, a broadband optoelectronic frequency synthesizer with a programmable frequency range from 2 to 20 GHz is designed and implemented. Phase noise measurements show that the optoelectronic PLL frequency synthesizer achieves an integrated rms-jitter (1 kHz–100 MHz) of less than 4 fs in the frequency range from 5 to 20 GHz with a typical value of 4 fs and a minimum of 3 fs. This is the first reported wideband PLL frequency synthesizer achieving sub-10-fs integrated rms-jitter (1 kHz–100 MHz) in the frequency range from 3 to 20 GHz. A comparison with best-in-class laboratory-grade frequency synthesizers in this frequency range shows that this synthesizer achieves lower phase noise than any electronic frequency synthesizer for offset frequencies larger than 2 kHz. [ABSTRACT FROM AUTHOR]

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6 GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18- μ m CMOS technology with supply voltage of 1.8 V. The output clocks with cycle-to-cycle jitter of 2.13 ps at 1.6 GHz. The phase noise of VCO is − 137 dBc/Hz at an offset of 100 MHz and total power consumed by the proposed PLL is 2.63 mW at 1.6 GHz. [ABSTRACT FROM AUTHOR]

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6 GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180 nm CMOS process with supply voltage of 1.8 V. The phase noise of VCO is − 1 3 7 dBc/Hz at an offset frequency of 100 MHz. The reference clock of 25 MHz synthesizes the output clock of 1.6 GHz with rms jitter of 0.642 ps. [ABSTRACT FROM AUTHOR]

This paper explores a speed and power improved dead zone free, low gate count CMOS phase frequency detector with charge pump (PFD-CP) for clock and data recovery application. Implemented in 90 nm CMOS technology, the proposed circuit configuration estimates a layout area of 420.66 μm2 and burns a low power as small as 172.10 μW when simulated with 5 GHz frequency at a power supply of 1.2 V at Cadence Virtuoso platform. With the elimination of reset path available in conventional PFD, this architecture doesn't only become blind zone free, but it also offers a lower phase noise and output noise of − 142.46 dBc/Hz and − 131.145 dBc/Hz respectively at 1 MHz offset. We have also studied the performance metrics with skew and without skew at different extreme corners for schematic and post layout to manifest the variation awareness and robustness of the circuit. The scalability of the circuit arrangement is also endorsed at lower CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents a delay line frequency discriminator and phase detector/charge pump (PD/CP)-based phase noise measurement (PNM) circuit with wide bandwidth, great sensitivity, and reliable on-chip integration. A delay-locked loop is integrated to automatically align the PD input phases, and a dc offset cancellation circuit is embedded to overcome the circuit mismatches. This PNM demonstrates −61/−81 dBc single tone sensitivity and −110.35/−138.60 dBc/Hz phase noise sensitivity at 100 kHz/1 MHz-offset, respectively, for a 10-GHz clock. The PNM errors are 0.35/1.12 dB at 100 kHz/1 MHz, respectively, compared with the signal analyzer’s (Agilent N9030A) PNM results. The PNM bandwidth is 110 MHz. This proof-of-concept design is fabricated in a 65-nm CMOS technology with the chip area of 1.5 mm $\times1.3$ mm. The circuit consumes 97.7 mW of power. [ABSTRACT FROM PUBLISHER]

Timing jitter is closely related to the phase noise of ultrafast laser pulse train under different mode-locking regimes. Investigations have been made towards timing jitter for pulse-to-pulse Cr:LiSAF femtosecond laser, for usage as a seed laser in synchrotron light source. The laser produced about 180 fs of pulses with an 83.27 MHz pulse repetition rate, which corresponds to a 1.80 m cavity length. Mode-locking was passively achieved using semiconductor saturable absorber mirror (SESAM) optimized for low threshold and stability operation. Active timing-jitter stabilization to an external high precision electronic oscillator was attained with a cavity length control loop using a piezoelectric actuator. Phase noise detection has been evaluated using a timing stabilizer system (CLX-1100) and a phase detector (AD8302). According to the results, the AD8302 phase detector has superior timing jitter sensitivity than the CLX-1100 timing stabilizer system. Ultra low-noise oscillator was introduced to improve the performance of the CLX-1100 timing stabilizer system, which has been evaluated from the phase noise of spectral density and reflected in the root mean square timing jitter. The low timing jitter of the laser pulses was sufficient to accomplish the synchrotron of the radiation source. [ABSTRACT FROM AUTHOR]

Optical fibers have been recognized as one of the most promising host material for coherent optical frequency transfer over thousands of kilometers. In the pioneering work, the active phase noise cancellation (ANC) technique has been widely used for suppressing the fiber phase noise introduced by the environmental perturbations, in which an ideal phase detector with high resolution and unlimited detection range is needed to extract the fiber phase noise, in particular for noisy fiber links. We demonstrate the passive phase noise cancellation (PNC) technique without the need of phase detector could be preferable for noisy fiber links. To avoid the effect of the radio frequency (RF) from the time base at the local site in the conventional active or passive phase noise cancellation techniques, here we introduce a fiber-pigtailed acousto-optic modulator (AOM) with two diffraction order outputs (0 and −1 order) with properly allocating the AOM-driving frequencies allowing to cancel the time base effect. Using this technique, we demonstrate transfer of coherent light through a 260 km noisy urban fiber link. The results show the effect of the RF reference can be successfully removed. After being passively compensated, we demonstrate a fractional frequency instability of 4. 9 × 1 0 − 14 at the integration time of 1 s and scales down to 1 0 − 20 level at 10,000 s in terms of modified Allan deviation over the 260 km noisy urban fiber link. The frequency uncertainty of the retrieved light after transferring through this noise-compensated fiber link relative to that of the input light achieves (0. 41 ± 4. 7) × 1 0 − 18 . The proposed technique opens a way to a broad distribution of an ultrastable frequency reference with high coherence without any effects coming from the RF reference and enables a wide range of applications beyond metrology over fiber networks. • Passive phase noise cancellation is demonstrated via a noisy fiber network. • By using a two-orders AOM, the effect of the time base can be avoided. • A delay-induced PNC compensate limitation model is demonstrated. [ABSTRACT FROM AUTHOR]

Wideband and low phase noise microwave synthesizers are of critical significance for various applications. Phase-locked loop (PLL) based microwave synthesizers are widely used. Normally, the phase noise of the PLL based microwave synthesizer is limited by the phase noise of the reference, phase detector, frequency divider and voltage-controlled oscillator (VCO). It is challenging to achieve a pure electronic microwave synthesizer with wide frequency coverage and low phase noise, simultaneously. Here, we propose a photonic microwave synthesizer which incorporates an ultra-low phase noise fiber mode-locked laser (MLL) based reference and a wideband frequency tunable optoelectronic oscillator (OEO) based VCO in a hybrid optoelectronic sub-sampling PLL. The frequency of the OEO can be locked to the harmonics of the repetition-rate of the fiber MLL, which combines the distinct advantages of the low phase noise of MLL and the wideband frequency tuning of OEO. A sub-sampling phase detector formed by a balanced optical microwave phase detector (BOMPD) eliminates the use of RF frequency divider and maintains low residual phase noise. We attain an X- and Ku-band photonic microwave synthesizer with over an octave frequency coverage from 8 GHz to 18 GHz, frequency synthesis step of 60.74 MHz and phase noise of -80 dBc/Hz at 100 Hz offset and -100 dBc/Hz at 1 kHz offset for 10 GHz output. The characteristics of the optoelectronic sub-sampling phase detector, the phase-locking dynamics of the hybrid optoelectronic PLL, and the phase noise of the synthesized RF signals are both theoretically and experimentally investigated. The experimental results agree well with the theoretical models. Our approach is promising to achieve wideband and low phase noise microwave synthesis. • A photonic microwave synthesizer by using an optoelectronic PLL is demonstrated. • A fiber mode-locked laser and a wideband optoelectronic oscillator are synchronized. • The performance of the synthesizer is theoretically and experimentally investigated. • X- and Ku-band signals with phase noise of -100 dBc/Hz at 1 kHz offset are achieved. [ABSTRACT FROM AUTHOR]

Output phase noise for edge-combining delay-locked loops (DLLs) is derived in this study, which is obtained by decomposing the synthesized output waveform into a noise-free signal and a corresponding noise perturbation on it. The noise-free signal, which is affected by the systematic errors as the phase offset between phase detector inputs or delay mismatches among delay cells, possesses a periodic steady-state solution, and therefore leads to output spur. The noise perturbation, on the other hand, will be upconverted to the frequency-multiplied output based on this solution. A general analysis approach is provided that can be applied to the case such as the change of the frequency multiplication factor or the variation of the output duty cycle. The theory is verified by a programmable edge-combining DLL, which has been realized in a CMOS 90-nm technology. The predicted output phase noise has close agreement with simulation results, as well as the measurement data when the frequency multiplication factor changes. [ABSTRACT FROM PUBLISHER]

A 2 GHz sub‐harmonically injection‐locked phase‐locked loop (SILPLL) with a self‐aligned injection window is presented. The SILPLL adopts a mixer‐based self‐align technique to automatically adjust the injection timing, overcoming the speed limitation of the phase detection. Circuit techniques such as a symmetrical mixer and a V/I converter with mismatch cancellation are adopted to improve injection timing accuracy. Fabricated in a 180 nm CMOS technology, the SILPLL exhibits −127 dBc/Hz phase noise at 1 MHz offset and draws 6.9 mA current from a 1.8 V power supply. The measured root‐mean‐square jitter integrating from 1 kHz to 40 MHz is 214 fs and the reference spur is −61 dBc. [ABSTRACT FROM AUTHOR]

In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter (TDC) is designed to enhance the jitter and locking time performance. The proposed ADPLL utilizes a low power and high resolution 3-bit flash TDC with foreground calibration to suppress the issues of process, voltage and temperature (PVT) spreads and achieves low jitter and low power ADPLL. To obtain the fast locking, a proposed dynamic bang-bang PFD is used. The proposed ADPLL takes only 5 iterations to achieve the locking from unlocked state. Additionally, ADPLL employs a wide range and low phase noise voltage controlled oscillator (VCO) based on inverters to obtain a reduced jitter in ADPLL. The proposed ADPLL is designed in 180-nm SCL digital CMOS technology at 1.8 V supply. It consumes a total power of 5.94 mW at 1.8 V. From the post layout simulations, the achieved FoM and periodic jitter is −227.6 dB and 1.71 ps respectively at an output frequency of 1.6 GHz. The achieved phase noise of proposed ADPLL is −131.2 dBc/Hz at offset of 100 MHz. [ABSTRACT FROM AUTHOR]

A phase-locked loop (PLL) architecture based on a 2D phase comparator matrix is introduced. In its general form, multiple phases of the input reference clock are compared with multiple phases of the feedback clock, allowing for wider bandwidth (BW) and lower phase noise generation of the PLL. Based on matrix phase detector architecture, a 6.25 GHz PLL achieving 5 GHz BW and exhibiting 55 fs-rms jitter is designed in 28 nm CMOS bulk technology. [ABSTRACT FROM AUTHOR]